1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef SCSI_BSG_MPI3MR_H_INCLUDED 20 #define SCSI_BSG_MPI3MR_H_INCLUDED 21 #include <linux/types.h> 22 #define MPI3MR_IOCTL_VERSION 0x06 23 #define MPI3MR_APP_DEFAULT_TIMEOUT (60) 24 #define MPI3MR_BSG_ADPTYPE_UNKNOWN 0 25 #define MPI3MR_BSG_ADPTYPE_AVGFAMILY 1 26 #define MPI3MR_BSG_ADPSTATE_UNKNOWN 0 27 #define MPI3MR_BSG_ADPSTATE_OPERATIONAL 1 28 #define MPI3MR_BSG_ADPSTATE_FAULT 2 29 #define MPI3MR_BSG_ADPSTATE_IN_RESET 3 30 #define MPI3MR_BSG_ADPSTATE_UNRECOVERABLE 4 31 #define MPI3MR_BSG_ADPRESET_UNKNOWN 0 32 #define MPI3MR_BSG_ADPRESET_SOFT 1 33 #define MPI3MR_BSG_ADPRESET_DIAG_FAULT 2 34 #define MPI3MR_BSG_LOGDATA_MAX_ENTRIES 400 35 #define MPI3MR_BSG_LOGDATA_ENTRY_HEADER_SZ 4 36 #define MPI3MR_DRVBSG_OPCODE_UNKNOWN 0 37 #define MPI3MR_DRVBSG_OPCODE_ADPINFO 1 38 #define MPI3MR_DRVBSG_OPCODE_ADPRESET 2 39 #define MPI3MR_DRVBSG_OPCODE_ALLTGTDEVINFO 4 40 #define MPI3MR_DRVBSG_OPCODE_GETCHGCNT 5 41 #define MPI3MR_DRVBSG_OPCODE_LOGDATAENABLE 6 42 #define MPI3MR_DRVBSG_OPCODE_PELENABLE 7 43 #define MPI3MR_DRVBSG_OPCODE_GETLOGDATA 8 44 #define MPI3MR_DRVBSG_OPCODE_QUERY_HDB 9 45 #define MPI3MR_DRVBSG_OPCODE_REPOST_HDB 10 46 #define MPI3MR_DRVBSG_OPCODE_UPLOAD_HDB 11 47 #define MPI3MR_DRVBSG_OPCODE_REFRESH_HDB_TRIGGERS 12 48 #define MPI3MR_BSG_BUFTYPE_UNKNOWN 0 49 #define MPI3MR_BSG_BUFTYPE_RAIDMGMT_CMD 1 50 #define MPI3MR_BSG_BUFTYPE_RAIDMGMT_RESP 2 51 #define MPI3MR_BSG_BUFTYPE_DATA_IN 3 52 #define MPI3MR_BSG_BUFTYPE_DATA_OUT 4 53 #define MPI3MR_BSG_BUFTYPE_MPI_REPLY 5 54 #define MPI3MR_BSG_BUFTYPE_ERR_RESPONSE 6 55 #define MPI3MR_BSG_BUFTYPE_MPI_REQUEST 0xFE 56 #define MPI3MR_BSG_MPI_REPLY_BUFTYPE_UNKNOWN 0 57 #define MPI3MR_BSG_MPI_REPLY_BUFTYPE_STATUS 1 58 #define MPI3MR_BSG_MPI_REPLY_BUFTYPE_ADDRESS 2 59 #define MPI3MR_HDB_BUFTYPE_UNKNOWN 0 60 #define MPI3MR_HDB_BUFTYPE_TRACE 1 61 #define MPI3MR_HDB_BUFTYPE_FIRMWARE 2 62 #define MPI3MR_HDB_BUFTYPE_RESERVED 3 63 #define MPI3MR_HDB_BUFSTATUS_UNKNOWN 0 64 #define MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED 1 65 #define MPI3MR_HDB_BUFSTATUS_POSTED_UNPAUSED 2 66 #define MPI3MR_HDB_BUFSTATUS_POSTED_PAUSED 3 67 #define MPI3MR_HDB_BUFSTATUS_RELEASED 4 68 #define MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN 0 69 #define MPI3MR_HDB_TRIGGER_TYPE_DIAGFAULT 1 70 #define MPI3MR_HDB_TRIGGER_TYPE_ELEMENT 2 71 #define MPI3MR_HDB_TRIGGER_TYPE_MASTER 3 72 enum command { 73 MPI3MR_DRV_CMD = 1, 74 MPI3MR_MPT_CMD = 2, 75 }; 76 struct mpi3_driver_info_layout { 77 __le32 information_length; 78 __u8 driver_signature[12]; 79 __u8 os_name[16]; 80 __u8 os_version[12]; 81 __u8 driver_name[20]; 82 __u8 driver_version[32]; 83 __u8 driver_release_date[20]; 84 __le32 driver_capabilities; 85 }; 86 struct mpi3mr_bsg_in_adpinfo { 87 __u32 adp_type; 88 __u32 rsvd1; 89 __u32 pci_dev_id; 90 __u32 pci_dev_hw_rev; 91 __u32 pci_subsys_dev_id; 92 __u32 pci_subsys_ven_id; 93 __u32 pci_dev : 5; 94 __u32 pci_func : 3; 95 __u32 pci_bus : 8; 96 __u16 rsvd2; 97 __u32 pci_seg_id; 98 __u32 app_intfc_ver; 99 __u8 adp_state; 100 __u8 rsvd3; 101 __u16 rsvd4; 102 __u32 rsvd5[2]; 103 struct mpi3_driver_info_layout driver_info; 104 }; 105 struct mpi3mr_bsg_adp_reset { 106 __u8 reset_type; 107 __u8 rsvd1; 108 __u16 rsvd2; 109 }; 110 struct mpi3mr_change_count { 111 __u16 change_count; 112 __u16 rsvd; 113 }; 114 struct mpi3mr_device_map_info { 115 __u16 handle; 116 __u16 perst_id; 117 __u32 target_id; 118 __u8 bus_id; 119 __u8 rsvd1; 120 __u16 rsvd2; 121 }; 122 struct mpi3mr_all_tgt_info { 123 __u16 num_devices; 124 __u16 rsvd1; 125 __u32 rsvd2; 126 struct mpi3mr_device_map_info dmi[1]; 127 }; 128 struct mpi3mr_logdata_enable { 129 __u16 max_entries; 130 __u16 rsvd; 131 }; 132 struct mpi3mr_bsg_out_pel_enable { 133 __u16 pel_locale; 134 __u8 pel_class; 135 __u8 rsvd; 136 }; 137 struct mpi3mr_logdata_entry { 138 __u8 valid_entry; 139 __u8 rsvd1; 140 __u16 rsvd2; 141 __u8 data[1]; 142 }; 143 struct mpi3mr_bsg_in_log_data { 144 struct mpi3mr_logdata_entry entry[1]; 145 }; 146 struct mpi3mr_hdb_entry { 147 __u8 buf_type; 148 __u8 status; 149 __u8 trigger_type; 150 __u8 rsvd1; 151 __u16 size; 152 __u16 rsvd2; 153 __u64 trigger_data; 154 __u32 rsvd3; 155 __u32 rsvd4; 156 }; 157 struct mpi3mr_bsg_in_hdb_status { 158 __u8 num_hdb_types; 159 __u8 rsvd1; 160 __u16 rsvd2; 161 __u32 rsvd3; 162 struct mpi3mr_hdb_entry entry[1]; 163 }; 164 struct mpi3mr_bsg_out_repost_hdb { 165 __u8 buf_type; 166 __u8 rsvd1; 167 __u16 rsvd2; 168 }; 169 struct mpi3mr_bsg_out_upload_hdb { 170 __u8 buf_type; 171 __u8 rsvd1; 172 __u16 rsvd2; 173 __u32 start_offset; 174 __u32 length; 175 }; 176 struct mpi3mr_bsg_out_refresh_hdb_triggers { 177 __u8 page_type; 178 __u8 rsvd1; 179 __u16 rsvd2; 180 }; 181 struct mpi3mr_bsg_drv_cmd { 182 __u8 mrioc_id; 183 __u8 opcode; 184 __u16 rsvd1; 185 __u32 rsvd2[4]; 186 }; 187 struct mpi3mr_bsg_in_reply_buf { 188 __u8 mpi_reply_type; 189 __u8 rsvd1; 190 __u16 rsvd2; 191 __u8 reply_buf[1]; 192 }; 193 struct mpi3mr_buf_entry { 194 __u8 buf_type; 195 __u8 rsvd1; 196 __u16 rsvd2; 197 __u32 buf_len; 198 }; 199 struct mpi3mr_buf_entry_list { 200 __u8 num_of_entries; 201 __u8 rsvd1; 202 __u16 rsvd2; 203 __u32 rsvd3; 204 struct mpi3mr_buf_entry buf_entry[1]; 205 }; 206 struct mpi3mr_bsg_mptcmd { 207 __u8 mrioc_id; 208 __u8 rsvd1; 209 __u16 timeout; 210 __u32 rsvd2; 211 struct mpi3mr_buf_entry_list buf_entry_list; 212 }; 213 struct mpi3mr_bsg_packet { 214 __u8 cmd_type; 215 __u8 rsvd1; 216 __u16 rsvd2; 217 __u32 rsvd3; 218 union { 219 struct mpi3mr_bsg_drv_cmd drvrcmd; 220 struct mpi3mr_bsg_mptcmd mptcmd; 221 } cmd; 222 }; 223 #ifndef MPI3_NVME_ENCAP_CMD_MAX 224 #define MPI3_NVME_ENCAP_CMD_MAX (1) 225 #endif 226 struct mpi3_nvme_encapsulated_request { 227 __le16 host_tag; 228 __u8 ioc_use_only02; 229 __u8 function; 230 __le16 ioc_use_only04; 231 __u8 ioc_use_only06; 232 __u8 msg_flags; 233 __le16 change_count; 234 __le16 dev_handle; 235 __le16 encapsulated_command_length; 236 __le16 flags; 237 __le32 data_length; 238 __le32 reserved14[3]; 239 __le32 command[MPI3_NVME_ENCAP_CMD_MAX]; 240 }; 241 struct mpi3_nvme_encapsulated_error_reply { 242 __le16 host_tag; 243 __u8 ioc_use_only02; 244 __u8 function; 245 __le16 ioc_use_only04; 246 __u8 ioc_use_only06; 247 __u8 msg_flags; 248 __le16 ioc_use_only08; 249 __le16 ioc_status; 250 __le32 ioc_log_info; 251 __le32 nvme_completion_entry[4]; 252 }; 253 #define MPI3MR_NVME_PRP_SIZE 8 254 #define MPI3MR_NVME_CMD_PRP1_OFFSET 24 255 #define MPI3MR_NVME_CMD_PRP2_OFFSET 32 256 #define MPI3MR_NVME_CMD_SGL_OFFSET 24 257 #define MPI3MR_NVME_DATA_FORMAT_PRP 0 258 #define MPI3MR_NVME_DATA_FORMAT_SGL1 1 259 #define MPI3MR_NVME_DATA_FORMAT_SGL2 2 260 struct mpi3_scsi_task_mgmt_request { 261 __le16 host_tag; 262 __u8 ioc_use_only02; 263 __u8 function; 264 __le16 ioc_use_only04; 265 __u8 ioc_use_only06; 266 __u8 msg_flags; 267 __le16 change_count; 268 __le16 dev_handle; 269 __le16 task_host_tag; 270 __u8 task_type; 271 __u8 reserved0f; 272 __le16 task_request_queue_id; 273 __le16 reserved12; 274 __le32 reserved14; 275 __u8 lun[8]; 276 }; 277 #define MPI3_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x08) 278 #define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) 279 #define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK_SET (0x02) 280 #define MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) 281 #define MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) 282 #define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06) 283 #define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07) 284 #define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_ACA (0x08) 285 #define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK_SET (0x09) 286 #define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_ASYNC_EVENT (0x0a) 287 #define MPI3_SCSITASKMGMT_TASKTYPE_I_T_NEXUS_RESET (0x0b) 288 struct mpi3_scsi_task_mgmt_reply { 289 __le16 host_tag; 290 __u8 ioc_use_only02; 291 __u8 function; 292 __le16 ioc_use_only04; 293 __u8 ioc_use_only06; 294 __u8 msg_flags; 295 __le16 ioc_use_only08; 296 __le16 ioc_status; 297 __le32 ioc_log_info; 298 __le32 termination_count; 299 __le32 response_data; 300 __le32 reserved18; 301 }; 302 #define MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE (0x00) 303 #define MPI3_SCSITASKMGMT_RSPCODE_INVALID_FRAME (0x02) 304 #define MPI3_SCSITASKMGMT_RSPCODE_TM_FUNCTION_NOT_SUPPORTED (0x04) 305 #define MPI3_SCSITASKMGMT_RSPCODE_TM_FAILED (0x05) 306 #define MPI3_SCSITASKMGMT_RSPCODE_TM_SUCCEEDED (0x08) 307 #define MPI3_SCSITASKMGMT_RSPCODE_TM_INVALID_LUN (0x09) 308 #define MPI3_SCSITASKMGMT_RSPCODE_TM_OVERLAPPED_TAG (0x0a) 309 #define MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC (0x80) 310 #define MPI3_SCSITASKMGMT_RSPCODE_TM_NVME_DENIED (0x81) 311 #define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200) 312 #define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100) 313 #define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080) 314 #define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0x0040) 315 #define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0x0020) 316 #define MPI3_PEL_LOCALE_FLAGS_SAS (0x0010) 317 #define MPI3_PEL_LOCALE_FLAGS_EPACK (0x0008) 318 #define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0x0004) 319 #define MPI3_PEL_LOCALE_FLAGS_PD (0x0002) 320 #define MPI3_PEL_LOCALE_FLAGS_VD (0x0001) 321 #define MPI3_PEL_CLASS_DEBUG (0x00) 322 #define MPI3_PEL_CLASS_PROGRESS (0x01) 323 #define MPI3_PEL_CLASS_INFORMATIONAL (0x02) 324 #define MPI3_PEL_CLASS_WARNING (0x03) 325 #define MPI3_PEL_CLASS_CRITICAL (0x04) 326 #define MPI3_PEL_CLASS_FATAL (0x05) 327 #define MPI3_PEL_CLASS_FAULT (0x06) 328 #define MPI3_BSG_FUNCTION_MGMT_PASSTHROUGH (0x0a) 329 #define MPI3_BSG_FUNCTION_SCSI_IO (0x20) 330 #define MPI3_BSG_FUNCTION_SCSI_TASK_MGMT (0x21) 331 #define MPI3_BSG_FUNCTION_SMP_PASSTHROUGH (0x22) 332 #define MPI3_BSG_FUNCTION_NVME_ENCAPSULATED (0x24) 333 #endif 334