1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __AMDGPU_DRM_H__ 20 #define __AMDGPU_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define DRM_AMDGPU_GEM_CREATE 0x00 26 #define DRM_AMDGPU_GEM_MMAP 0x01 27 #define DRM_AMDGPU_CTX 0x02 28 #define DRM_AMDGPU_BO_LIST 0x03 29 #define DRM_AMDGPU_CS 0x04 30 #define DRM_AMDGPU_INFO 0x05 31 #define DRM_AMDGPU_GEM_METADATA 0x06 32 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 33 #define DRM_AMDGPU_GEM_VA 0x08 34 #define DRM_AMDGPU_WAIT_CS 0x09 35 #define DRM_AMDGPU_GEM_OP 0x10 36 #define DRM_AMDGPU_GEM_USERPTR 0x11 37 #define DRM_AMDGPU_WAIT_FENCES 0x12 38 #define DRM_AMDGPU_VM 0x13 39 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 40 #define DRM_AMDGPU_SCHED 0x15 41 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 42 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 43 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 44 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 45 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 46 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 47 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 48 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 49 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 50 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 51 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 52 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 53 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 54 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 55 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 56 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 57 #define AMDGPU_GEM_DOMAIN_CPU 0x1 58 #define AMDGPU_GEM_DOMAIN_GTT 0x2 59 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 60 #define AMDGPU_GEM_DOMAIN_GDS 0x8 61 #define AMDGPU_GEM_DOMAIN_GWS 0x10 62 #define AMDGPU_GEM_DOMAIN_OA 0x20 63 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA) 64 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 65 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 66 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 67 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 68 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 69 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 70 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 71 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 72 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 73 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 74 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 75 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 76 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 77 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 78 struct drm_amdgpu_gem_create_in { 79 __u64 bo_size; 80 __u64 alignment; 81 __u64 domains; 82 __u64 domain_flags; 83 }; 84 struct drm_amdgpu_gem_create_out { 85 __u32 handle; 86 __u32 _pad; 87 }; 88 union drm_amdgpu_gem_create { 89 struct drm_amdgpu_gem_create_in in; 90 struct drm_amdgpu_gem_create_out out; 91 }; 92 #define AMDGPU_BO_LIST_OP_CREATE 0 93 #define AMDGPU_BO_LIST_OP_DESTROY 1 94 #define AMDGPU_BO_LIST_OP_UPDATE 2 95 struct drm_amdgpu_bo_list_in { 96 __u32 operation; 97 __u32 list_handle; 98 __u32 bo_number; 99 __u32 bo_info_size; 100 __u64 bo_info_ptr; 101 }; 102 struct drm_amdgpu_bo_list_entry { 103 __u32 bo_handle; 104 __u32 bo_priority; 105 }; 106 struct drm_amdgpu_bo_list_out { 107 __u32 list_handle; 108 __u32 _pad; 109 }; 110 union drm_amdgpu_bo_list { 111 struct drm_amdgpu_bo_list_in in; 112 struct drm_amdgpu_bo_list_out out; 113 }; 114 #define AMDGPU_CTX_OP_ALLOC_CTX 1 115 #define AMDGPU_CTX_OP_FREE_CTX 2 116 #define AMDGPU_CTX_OP_QUERY_STATE 3 117 #define AMDGPU_CTX_OP_QUERY_STATE2 4 118 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 119 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 120 #define AMDGPU_CTX_NO_RESET 0 121 #define AMDGPU_CTX_GUILTY_RESET 1 122 #define AMDGPU_CTX_INNOCENT_RESET 2 123 #define AMDGPU_CTX_UNKNOWN_RESET 3 124 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1 << 0) 125 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1 << 1) 126 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1 << 2) 127 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1 << 3) 128 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1 << 4) 129 #define AMDGPU_CTX_PRIORITY_UNSET - 2048 130 #define AMDGPU_CTX_PRIORITY_VERY_LOW - 1023 131 #define AMDGPU_CTX_PRIORITY_LOW - 512 132 #define AMDGPU_CTX_PRIORITY_NORMAL 0 133 #define AMDGPU_CTX_PRIORITY_HIGH 512 134 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 135 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 136 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 137 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 138 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 139 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 140 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 141 struct drm_amdgpu_ctx_in { 142 __u32 op; 143 __u32 flags; 144 __u32 ctx_id; 145 __s32 priority; 146 }; 147 union drm_amdgpu_ctx_out { 148 struct { 149 __u32 ctx_id; 150 __u32 _pad; 151 } alloc; 152 struct { 153 __u64 flags; 154 __u32 hangs; 155 __u32 reset_status; 156 } state; 157 struct { 158 __u32 flags; 159 __u32 _pad; 160 } pstate; 161 }; 162 union drm_amdgpu_ctx { 163 struct drm_amdgpu_ctx_in in; 164 union drm_amdgpu_ctx_out out; 165 }; 166 #define AMDGPU_VM_OP_RESERVE_VMID 1 167 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 168 struct drm_amdgpu_vm_in { 169 __u32 op; 170 __u32 flags; 171 }; 172 struct drm_amdgpu_vm_out { 173 __u64 flags; 174 }; 175 union drm_amdgpu_vm { 176 struct drm_amdgpu_vm_in in; 177 struct drm_amdgpu_vm_out out; 178 }; 179 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 180 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 181 struct drm_amdgpu_sched_in { 182 __u32 op; 183 __u32 fd; 184 __s32 priority; 185 __u32 ctx_id; 186 }; 187 union drm_amdgpu_sched { 188 struct drm_amdgpu_sched_in in; 189 }; 190 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 191 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 192 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 193 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 194 struct drm_amdgpu_gem_userptr { 195 __u64 addr; 196 __u64 size; 197 __u32 flags; 198 __u32 handle; 199 }; 200 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 201 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 202 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 203 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 204 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 205 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 206 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 207 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 208 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 209 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 210 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 211 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 212 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 213 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 214 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 215 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 216 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 217 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 218 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 219 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 220 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 221 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 222 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 223 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 224 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 225 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 226 #define AMDGPU_TILING_SCANOUT_SHIFT 63 227 #define AMDGPU_TILING_SCANOUT_MASK 0x1 228 #define AMDGPU_TILING_SET(field,value) (((__u64) (value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT) 229 #define AMDGPU_TILING_GET(value,field) (((__u64) (value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK) 230 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 231 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 232 struct drm_amdgpu_gem_metadata { 233 __u32 handle; 234 __u32 op; 235 struct { 236 __u64 flags; 237 __u64 tiling_info; 238 __u32 data_size_bytes; 239 __u32 data[64]; 240 } data; 241 }; 242 struct drm_amdgpu_gem_mmap_in { 243 __u32 handle; 244 __u32 _pad; 245 }; 246 struct drm_amdgpu_gem_mmap_out { 247 __u64 addr_ptr; 248 }; 249 union drm_amdgpu_gem_mmap { 250 struct drm_amdgpu_gem_mmap_in in; 251 struct drm_amdgpu_gem_mmap_out out; 252 }; 253 struct drm_amdgpu_gem_wait_idle_in { 254 __u32 handle; 255 __u32 flags; 256 __u64 timeout; 257 }; 258 struct drm_amdgpu_gem_wait_idle_out { 259 __u32 status; 260 __u32 domain; 261 }; 262 union drm_amdgpu_gem_wait_idle { 263 struct drm_amdgpu_gem_wait_idle_in in; 264 struct drm_amdgpu_gem_wait_idle_out out; 265 }; 266 struct drm_amdgpu_wait_cs_in { 267 __u64 handle; 268 __u64 timeout; 269 __u32 ip_type; 270 __u32 ip_instance; 271 __u32 ring; 272 __u32 ctx_id; 273 }; 274 struct drm_amdgpu_wait_cs_out { 275 __u64 status; 276 }; 277 union drm_amdgpu_wait_cs { 278 struct drm_amdgpu_wait_cs_in in; 279 struct drm_amdgpu_wait_cs_out out; 280 }; 281 struct drm_amdgpu_fence { 282 __u32 ctx_id; 283 __u32 ip_type; 284 __u32 ip_instance; 285 __u32 ring; 286 __u64 seq_no; 287 }; 288 struct drm_amdgpu_wait_fences_in { 289 __u64 fences; 290 __u32 fence_count; 291 __u32 wait_all; 292 __u64 timeout_ns; 293 }; 294 struct drm_amdgpu_wait_fences_out { 295 __u32 status; 296 __u32 first_signaled; 297 }; 298 union drm_amdgpu_wait_fences { 299 struct drm_amdgpu_wait_fences_in in; 300 struct drm_amdgpu_wait_fences_out out; 301 }; 302 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 303 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 304 struct drm_amdgpu_gem_op { 305 __u32 handle; 306 __u32 op; 307 __u64 value; 308 }; 309 #define AMDGPU_VA_OP_MAP 1 310 #define AMDGPU_VA_OP_UNMAP 2 311 #define AMDGPU_VA_OP_CLEAR 3 312 #define AMDGPU_VA_OP_REPLACE 4 313 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 314 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 315 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 316 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 317 #define AMDGPU_VM_PAGE_PRT (1 << 4) 318 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 319 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 320 #define AMDGPU_VM_MTYPE_NC (1 << 5) 321 #define AMDGPU_VM_MTYPE_WC (2 << 5) 322 #define AMDGPU_VM_MTYPE_CC (3 << 5) 323 #define AMDGPU_VM_MTYPE_UC (4 << 5) 324 #define AMDGPU_VM_MTYPE_RW (5 << 5) 325 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 326 struct drm_amdgpu_gem_va { 327 __u32 handle; 328 __u32 _pad; 329 __u32 operation; 330 __u32 flags; 331 __u64 va_address; 332 __u64 offset_in_bo; 333 __u64 map_size; 334 }; 335 #define AMDGPU_HW_IP_GFX 0 336 #define AMDGPU_HW_IP_COMPUTE 1 337 #define AMDGPU_HW_IP_DMA 2 338 #define AMDGPU_HW_IP_UVD 3 339 #define AMDGPU_HW_IP_VCE 4 340 #define AMDGPU_HW_IP_UVD_ENC 5 341 #define AMDGPU_HW_IP_VCN_DEC 6 342 #define AMDGPU_HW_IP_VCN_ENC 7 343 #define AMDGPU_HW_IP_VCN_JPEG 8 344 #define AMDGPU_HW_IP_NUM 9 345 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 346 #define AMDGPU_CHUNK_ID_IB 0x01 347 #define AMDGPU_CHUNK_ID_FENCE 0x02 348 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 349 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 350 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 351 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 352 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 353 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 354 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 355 struct drm_amdgpu_cs_chunk { 356 __u32 chunk_id; 357 __u32 length_dw; 358 __u64 chunk_data; 359 }; 360 struct drm_amdgpu_cs_in { 361 __u32 ctx_id; 362 __u32 bo_list_handle; 363 __u32 num_chunks; 364 __u32 flags; 365 __u64 chunks; 366 }; 367 struct drm_amdgpu_cs_out { 368 __u64 handle; 369 }; 370 union drm_amdgpu_cs { 371 struct drm_amdgpu_cs_in in; 372 struct drm_amdgpu_cs_out out; 373 }; 374 #define AMDGPU_IB_FLAG_CE (1 << 0) 375 #define AMDGPU_IB_FLAG_PREAMBLE (1 << 1) 376 #define AMDGPU_IB_FLAG_PREEMPT (1 << 2) 377 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 378 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 379 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 380 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 381 struct drm_amdgpu_cs_chunk_ib { 382 __u32 _pad; 383 __u32 flags; 384 __u64 va_start; 385 __u32 ib_bytes; 386 __u32 ip_type; 387 __u32 ip_instance; 388 __u32 ring; 389 }; 390 struct drm_amdgpu_cs_chunk_dep { 391 __u32 ip_type; 392 __u32 ip_instance; 393 __u32 ring; 394 __u32 ctx_id; 395 __u64 handle; 396 }; 397 struct drm_amdgpu_cs_chunk_fence { 398 __u32 handle; 399 __u32 offset; 400 }; 401 struct drm_amdgpu_cs_chunk_sem { 402 __u32 handle; 403 }; 404 struct drm_amdgpu_cs_chunk_syncobj { 405 __u32 handle; 406 __u32 flags; 407 __u64 point; 408 }; 409 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 410 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 411 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 412 union drm_amdgpu_fence_to_handle { 413 struct { 414 struct drm_amdgpu_fence fence; 415 __u32 what; 416 __u32 pad; 417 } in; 418 struct { 419 __u32 handle; 420 } out; 421 }; 422 struct drm_amdgpu_cs_chunk_data { 423 union { 424 struct drm_amdgpu_cs_chunk_ib ib_data; 425 struct drm_amdgpu_cs_chunk_fence fence_data; 426 }; 427 }; 428 #define AMDGPU_IDS_FLAGS_FUSION 0x1 429 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 430 #define AMDGPU_IDS_FLAGS_TMZ 0x4 431 #define AMDGPU_INFO_ACCEL_WORKING 0x00 432 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 433 #define AMDGPU_INFO_HW_IP_INFO 0x02 434 #define AMDGPU_INFO_HW_IP_COUNT 0x03 435 #define AMDGPU_INFO_TIMESTAMP 0x05 436 #define AMDGPU_INFO_FW_VERSION 0x0e 437 #define AMDGPU_INFO_FW_VCE 0x1 438 #define AMDGPU_INFO_FW_UVD 0x2 439 #define AMDGPU_INFO_FW_GMC 0x03 440 #define AMDGPU_INFO_FW_GFX_ME 0x04 441 #define AMDGPU_INFO_FW_GFX_PFP 0x05 442 #define AMDGPU_INFO_FW_GFX_CE 0x06 443 #define AMDGPU_INFO_FW_GFX_RLC 0x07 444 #define AMDGPU_INFO_FW_GFX_MEC 0x08 445 #define AMDGPU_INFO_FW_SMC 0x0a 446 #define AMDGPU_INFO_FW_SDMA 0x0b 447 #define AMDGPU_INFO_FW_SOS 0x0c 448 #define AMDGPU_INFO_FW_ASD 0x0d 449 #define AMDGPU_INFO_FW_VCN 0x0e 450 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 451 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 452 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 453 #define AMDGPU_INFO_FW_DMCU 0x12 454 #define AMDGPU_INFO_FW_TA 0x13 455 #define AMDGPU_INFO_FW_DMCUB 0x14 456 #define AMDGPU_INFO_FW_TOC 0x15 457 #define AMDGPU_INFO_FW_CAP 0x16 458 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 459 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 460 #define AMDGPU_INFO_FW_MES_KIQ 0x19 461 #define AMDGPU_INFO_FW_MES 0x1a 462 #define AMDGPU_INFO_FW_IMU 0x1b 463 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 464 #define AMDGPU_INFO_VRAM_USAGE 0x10 465 #define AMDGPU_INFO_GTT_USAGE 0x11 466 #define AMDGPU_INFO_GDS_CONFIG 0x13 467 #define AMDGPU_INFO_VRAM_GTT 0x14 468 #define AMDGPU_INFO_READ_MMR_REG 0x15 469 #define AMDGPU_INFO_DEV_INFO 0x16 470 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 471 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 472 #define AMDGPU_INFO_MEMORY 0x19 473 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 474 #define AMDGPU_INFO_VBIOS 0x1B 475 #define AMDGPU_INFO_VBIOS_SIZE 0x1 476 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 477 #define AMDGPU_INFO_VBIOS_INFO 0x3 478 #define AMDGPU_INFO_NUM_HANDLES 0x1C 479 #define AMDGPU_INFO_SENSOR 0x1D 480 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 481 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 482 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 483 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 484 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 485 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 486 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 487 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 488 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 489 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 490 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 491 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 492 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 493 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 494 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 495 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 496 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 497 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 498 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 499 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 500 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 501 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 502 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 503 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 504 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 505 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 506 #define AMDGPU_INFO_VIDEO_CAPS 0x21 507 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 508 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 509 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 510 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 511 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 512 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 513 struct drm_amdgpu_query_fw { 514 __u32 fw_type; 515 __u32 ip_instance; 516 __u32 index; 517 __u32 _pad; 518 }; 519 struct drm_amdgpu_info { 520 __u64 return_pointer; 521 __u32 return_size; 522 __u32 query; 523 union { 524 struct { 525 __u32 id; 526 __u32 _pad; 527 } mode_crtc; 528 struct { 529 __u32 type; 530 __u32 ip_instance; 531 } query_hw_ip; 532 struct { 533 __u32 dword_offset; 534 __u32 count; 535 __u32 instance; 536 __u32 flags; 537 } read_mmr_reg; 538 struct drm_amdgpu_query_fw query_fw; 539 struct { 540 __u32 type; 541 __u32 offset; 542 } vbios_info; 543 struct { 544 __u32 type; 545 } sensor_info; 546 struct { 547 __u32 type; 548 } video_cap; 549 }; 550 }; 551 struct drm_amdgpu_info_gds { 552 __u32 gds_gfx_partition_size; 553 __u32 compute_partition_size; 554 __u32 gds_total_size; 555 __u32 gws_per_gfx_partition; 556 __u32 gws_per_compute_partition; 557 __u32 oa_per_gfx_partition; 558 __u32 oa_per_compute_partition; 559 __u32 _pad; 560 }; 561 struct drm_amdgpu_info_vram_gtt { 562 __u64 vram_size; 563 __u64 vram_cpu_accessible_size; 564 __u64 gtt_size; 565 }; 566 struct drm_amdgpu_heap_info { 567 __u64 total_heap_size; 568 __u64 usable_heap_size; 569 __u64 heap_usage; 570 __u64 max_allocation; 571 }; 572 struct drm_amdgpu_memory_info { 573 struct drm_amdgpu_heap_info vram; 574 struct drm_amdgpu_heap_info cpu_accessible_vram; 575 struct drm_amdgpu_heap_info gtt; 576 }; 577 struct drm_amdgpu_info_firmware { 578 __u32 ver; 579 __u32 feature; 580 }; 581 struct drm_amdgpu_info_vbios { 582 __u8 name[64]; 583 __u8 vbios_pn[64]; 584 __u32 version; 585 __u32 pad; 586 __u8 vbios_ver_str[32]; 587 __u8 date[32]; 588 }; 589 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 590 #define AMDGPU_VRAM_TYPE_GDDR1 1 591 #define AMDGPU_VRAM_TYPE_DDR2 2 592 #define AMDGPU_VRAM_TYPE_GDDR3 3 593 #define AMDGPU_VRAM_TYPE_GDDR4 4 594 #define AMDGPU_VRAM_TYPE_GDDR5 5 595 #define AMDGPU_VRAM_TYPE_HBM 6 596 #define AMDGPU_VRAM_TYPE_DDR3 7 597 #define AMDGPU_VRAM_TYPE_DDR4 8 598 #define AMDGPU_VRAM_TYPE_GDDR6 9 599 #define AMDGPU_VRAM_TYPE_DDR5 10 600 #define AMDGPU_VRAM_TYPE_LPDDR4 11 601 #define AMDGPU_VRAM_TYPE_LPDDR5 12 602 struct drm_amdgpu_info_device { 603 __u32 device_id; 604 __u32 chip_rev; 605 __u32 external_rev; 606 __u32 pci_rev; 607 __u32 family; 608 __u32 num_shader_engines; 609 __u32 num_shader_arrays_per_engine; 610 __u32 gpu_counter_freq; 611 __u64 max_engine_clock; 612 __u64 max_memory_clock; 613 __u32 cu_active_number; 614 __u32 cu_ao_mask; 615 __u32 cu_bitmap[4][4]; 616 __u32 enabled_rb_pipes_mask; 617 __u32 num_rb_pipes; 618 __u32 num_hw_gfx_contexts; 619 __u32 _pad; 620 __u64 ids_flags; 621 __u64 virtual_address_offset; 622 __u64 virtual_address_max; 623 __u32 virtual_address_alignment; 624 __u32 pte_fragment_size; 625 __u32 gart_page_size; 626 __u32 ce_ram_size; 627 __u32 vram_type; 628 __u32 vram_bit_width; 629 __u32 vce_harvest_config; 630 __u32 gc_double_offchip_lds_buf; 631 __u64 prim_buf_gpu_addr; 632 __u64 pos_buf_gpu_addr; 633 __u64 cntl_sb_buf_gpu_addr; 634 __u64 param_buf_gpu_addr; 635 __u32 prim_buf_size; 636 __u32 pos_buf_size; 637 __u32 cntl_sb_buf_size; 638 __u32 param_buf_size; 639 __u32 wave_front_size; 640 __u32 num_shader_visible_vgprs; 641 __u32 num_cu_per_sh; 642 __u32 num_tcc_blocks; 643 __u32 gs_vgt_table_depth; 644 __u32 gs_prim_buffer_depth; 645 __u32 max_gs_waves_per_vgt; 646 __u32 _pad1; 647 __u32 cu_ao_bitmap[4][4]; 648 __u64 high_va_offset; 649 __u64 high_va_max; 650 __u32 pa_sc_tile_steering_override; 651 __u64 tcc_disabled_mask; 652 }; 653 struct drm_amdgpu_info_hw_ip { 654 __u32 hw_ip_version_major; 655 __u32 hw_ip_version_minor; 656 __u64 capabilities_flags; 657 __u32 ib_start_alignment; 658 __u32 ib_size_alignment; 659 __u32 available_rings; 660 __u32 ip_discovery_version; 661 }; 662 struct drm_amdgpu_info_num_handles { 663 __u32 uvd_max_handles; 664 __u32 uvd_used_handles; 665 }; 666 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 667 struct drm_amdgpu_info_vce_clock_table_entry { 668 __u32 sclk; 669 __u32 mclk; 670 __u32 eclk; 671 __u32 pad; 672 }; 673 struct drm_amdgpu_info_vce_clock_table { 674 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 675 __u32 num_valid_entries; 676 __u32 pad; 677 }; 678 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 679 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 680 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 681 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 682 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 683 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 684 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 685 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 686 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 687 struct drm_amdgpu_info_video_codec_info { 688 __u32 valid; 689 __u32 max_width; 690 __u32 max_height; 691 __u32 max_pixels_per_frame; 692 __u32 max_level; 693 __u32 pad; 694 }; 695 struct drm_amdgpu_info_video_caps { 696 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 697 }; 698 #define AMDGPU_FAMILY_UNKNOWN 0 699 #define AMDGPU_FAMILY_SI 110 700 #define AMDGPU_FAMILY_CI 120 701 #define AMDGPU_FAMILY_KV 125 702 #define AMDGPU_FAMILY_VI 130 703 #define AMDGPU_FAMILY_CZ 135 704 #define AMDGPU_FAMILY_AI 141 705 #define AMDGPU_FAMILY_RV 142 706 #define AMDGPU_FAMILY_NV 143 707 #define AMDGPU_FAMILY_VGH 144 708 #define AMDGPU_FAMILY_GC_11_0_0 145 709 #define AMDGPU_FAMILY_YC 146 710 #define AMDGPU_FAMILY_GC_11_0_1 148 711 #define AMDGPU_FAMILY_GC_10_3_6 149 712 #define AMDGPU_FAMILY_GC_10_3_7 151 713 #ifdef __cplusplus 714 } 715 #endif 716 #endif 717