1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __SAMSUNG_DRM_H__ 20 #define __SAMSUNG_DRM_H__ 21 #ifdef __linux__ 22 #include <linux/types.h> 23 #endif 24 #include <drm/drm.h> 25 #include <drm/drm_fourcc_gs101.h> 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 #define DRM_SAMSUNG_HDR_EOTF_LUT_LEN 129 30 #define DRM_SAMSUNG_HDR_EOTF_V2P2_LUT_LEN 20 31 struct hdr_eotf_lut { 32 __u16 posx[DRM_SAMSUNG_HDR_EOTF_LUT_LEN]; 33 __u32 posy[DRM_SAMSUNG_HDR_EOTF_LUT_LEN]; 34 }; 35 struct hdr_v2p2_element { 36 __u16 even; 37 __u16 odd; 38 }; 39 struct hdr_eotf_lut_v2p2 { 40 struct hdr_v2p2_element ts[DRM_SAMSUNG_HDR_EOTF_V2P2_LUT_LEN]; 41 struct hdr_v2p2_element vs[DRM_SAMSUNG_HDR_EOTF_V2P2_LUT_LEN]; 42 __u16 scaler; 43 bool lut_en; 44 }; 45 #define DRM_SAMSUNG_HDR_OETF_LUT_LEN 33 46 #define DRM_SAMSUNG_HDR_OETF_V2P2_LUT_LEN 24 47 struct hdr_oetf_lut { 48 __u16 posx[DRM_SAMSUNG_HDR_OETF_LUT_LEN]; 49 __u16 posy[DRM_SAMSUNG_HDR_OETF_LUT_LEN]; 50 }; 51 struct hdr_oetf_lut_v2p2 { 52 struct hdr_v2p2_element ts[DRM_SAMSUNG_HDR_OETF_V2P2_LUT_LEN]; 53 struct hdr_v2p2_element vs[DRM_SAMSUNG_HDR_OETF_V2P2_LUT_LEN]; 54 }; 55 #define DRM_SAMSUNG_HDR_GM_DIMENS 3 56 struct hdr_gm_data { 57 __u32 coeffs[DRM_SAMSUNG_HDR_GM_DIMENS * DRM_SAMSUNG_HDR_GM_DIMENS]; 58 __u32 offsets[DRM_SAMSUNG_HDR_GM_DIMENS]; 59 }; 60 #define DRM_SAMSUNG_HDR_TM_LUT_LEN 33 61 #define DRM_SAMSUNG_HDR_TM_V2P2_LUT_LEN 24 62 struct hdr_tm_data { 63 __u16 coeff_r; 64 __u16 coeff_g; 65 __u16 coeff_b; 66 __u16 rng_x_min; 67 __u16 rng_x_max; 68 __u16 rng_y_min; 69 __u16 rng_y_max; 70 __u16 posx[DRM_SAMSUNG_HDR_TM_LUT_LEN]; 71 __u32 posy[DRM_SAMSUNG_HDR_TM_LUT_LEN]; 72 }; 73 struct hdr_tm_data_v2p2 { 74 __u16 coeff_00; 75 __u16 coeff_01; 76 __u16 coeff_02; 77 __u16 ymix_tf; 78 __u16 ymix_vf; 79 __u16 ymix_slope; 80 __u16 ymix_dv; 81 struct hdr_v2p2_element ts[DRM_SAMSUNG_HDR_TM_V2P2_LUT_LEN]; 82 struct hdr_v2p2_element vs[DRM_SAMSUNG_HDR_TM_V2P2_LUT_LEN]; 83 }; 84 #define DRM_SAMSUNG_CGC_LUT_REG_CNT 2457 85 struct cgc_lut { 86 __u32 r_values[DRM_SAMSUNG_CGC_LUT_REG_CNT]; 87 __u32 g_values[DRM_SAMSUNG_CGC_LUT_REG_CNT]; 88 __u32 b_values[DRM_SAMSUNG_CGC_LUT_REG_CNT]; 89 }; 90 #define DRM_SAMSUNG_CGC_DMA_LUT_ENTRY_CNT 4913 91 struct cgc_dma_lut { 92 __u16 r_value; 93 __u16 g_value; 94 __u16 b_value; 95 }; 96 #define DRM_SAMSUNG_MATRIX_DIMENS 3 97 struct exynos_matrix { 98 __u16 coeffs[DRM_SAMSUNG_MATRIX_DIMENS * DRM_SAMSUNG_MATRIX_DIMENS]; 99 __u16 offsets[DRM_SAMSUNG_MATRIX_DIMENS]; 100 }; 101 struct dpp_size_range { 102 __u32 min; 103 __u32 max; 104 __u32 align; 105 }; 106 struct dpp_restriction { 107 struct dpp_size_range src_f_w; 108 struct dpp_size_range src_f_h; 109 struct dpp_size_range src_w; 110 struct dpp_size_range src_h; 111 __u32 src_x_align; 112 __u32 src_y_align; 113 struct dpp_size_range dst_f_w; 114 struct dpp_size_range dst_f_h; 115 struct dpp_size_range dst_w; 116 struct dpp_size_range dst_h; 117 __u32 dst_x_align; 118 __u32 dst_y_align; 119 struct dpp_size_range blk_w; 120 struct dpp_size_range blk_h; 121 __u32 blk_x_align; 122 __u32 blk_y_align; 123 __u32 src_h_rot_max; 124 __u32 scale_down; 125 __u32 scale_up; 126 }; 127 struct dpp_ch_restriction { 128 __s32 id; 129 __u64 attr; 130 struct dpp_restriction restriction; 131 }; 132 struct dither_config { 133 __u8 en : 1; 134 __u8 mode : 1; 135 __u8 frame_con : 1; 136 __u8 frame_offset : 2; 137 __u8 table_sel_r : 1; 138 __u8 table_sel_g : 1; 139 __u8 table_sel_b : 1; 140 __u32 reserved : 24; 141 }; 142 struct attribute_range { 143 __u32 min; 144 __u32 max; 145 }; 146 struct brightness_attribute { 147 struct attribute_range nits; 148 struct attribute_range level; 149 struct attribute_range percentage; 150 }; 151 struct brightness_capability { 152 struct brightness_attribute normal; 153 struct brightness_attribute hbm; 154 }; 155 struct tui_hw_buffer { 156 __u64 fb_physical; 157 __u64 fb_size; 158 } __attribute__((packed)); 159 #define EXYNOS_START_TUI 0x10 160 #define EXYNOS_FINISH_TUI 0x11 161 #define EXYNOS_TUI_REQUEST_BUFFER 0x20 162 #define EXYNOS_TUI_RELEASE_BUFFER 0x21 163 struct histogram_roi { 164 __u16 start_x; 165 __u16 start_y; 166 __u16 hsize; 167 __u16 vsize; 168 }; 169 struct histogram_weights { 170 __u16 weight_r; 171 __u16 weight_g; 172 __u16 weight_b; 173 }; 174 #define HISTOGRAM_BIN_COUNT 256 175 struct histogram_bins { 176 __u16 data[HISTOGRAM_BIN_COUNT]; 177 }; 178 enum histogram_prog_pos { 179 POST_DQE, 180 PRE_DQE, 181 }; 182 enum histogram_flags { 183 HISTOGRAM_FLAGS_BLOCKED_ROI = 0x20, 184 }; 185 struct histogram_channel_config { 186 struct histogram_roi roi; 187 struct histogram_weights weights; 188 enum histogram_prog_pos pos; 189 __u32 threshold; 190 struct histogram_roi blocked_roi; 191 __u32 flags; 192 }; 193 #define EXYNOS_DRM_HISTOGRAM_EVENT 0x80000000 194 #define EXYNOS_DRM_HISTOGRAM_CHANNEL_EVENT 0x80000001 195 struct exynos_drm_histogram_event { 196 struct drm_event base; 197 struct histogram_bins bins; 198 __u32 crtc_id; 199 }; 200 struct exynos_drm_histogram_channel_event { 201 struct drm_event base; 202 struct histogram_bins bins; 203 __u16 crtc_id; 204 __u16 hist_id; 205 }; 206 #define EXYNOS_HISTOGRAM_REQUEST 0x0 207 #define EXYNOS_HISTOGRAM_CANCEL 0x1 208 #define EXYNOS_HISTOGRAM_CHANNEL_REQUEST 0x20 209 #define EXYNOS_HISTOGRAM_CHANNEL_CANCEL 0x21 210 #define EXYNOS_HISTOGRAM_CHANNEL_DATA_REQUEST 0x30 211 struct exynos_drm_histogram_channel_request { 212 __u32 crtc_id; 213 __u32 hist_id; 214 }; 215 struct exynos_drm_histogram_channel_data_request { 216 __u16 crtc_id; 217 __u16 hist_id; 218 struct histogram_bins * bins; 219 }; 220 #define DRM_IOCTL_EXYNOS_HISTOGRAM_REQUEST DRM_IOW(DRM_COMMAND_BASE + EXYNOS_HISTOGRAM_REQUEST, __u32) 221 #define DRM_IOCTL_EXYNOS_HISTOGRAM_CANCEL DRM_IOW(DRM_COMMAND_BASE + EXYNOS_HISTOGRAM_CANCEL, __u32) 222 #define DRM_IOCTL_EXYNOS_HISTOGRAM_CHANNEL_REQUEST DRM_IOW(DRM_COMMAND_BASE + EXYNOS_HISTOGRAM_CHANNEL_REQUEST, struct exynos_drm_histogram_channel_request) 223 #define DRM_IOCTL_EXYNOS_HISTOGRAM_CHANNEL_CANCEL DRM_IOW(DRM_COMMAND_BASE + EXYNOS_HISTOGRAM_CHANNEL_CANCEL, struct exynos_drm_histogram_channel_request) 224 #define DRM_IOCTL_EXYNOS_HISTOGRAM_CHANNEL_DATA_REQUEST DRM_IOW(DRM_COMMAND_BASE + EXYNOS_HISTOGRAM_CHANNEL_DATA_REQUEST, struct exynos_drm_histogram_channel_data_request) 225 #ifdef __cplusplus 226 } 227 #endif 228 #endif 229