1 /* 2 * Copyright (c) 2020-2021 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #ifndef ARM_COMPUTE_NEGEMMCONV2D_H 25 #define ARM_COMPUTE_NEGEMMCONV2D_H 26 27 #include "arm_compute/runtime/FunctionDescriptors.h" 28 #include "arm_compute/runtime/IFunction.h" 29 #include "arm_compute/runtime/IMemoryManager.h" 30 31 #include <memory> 32 33 namespace arm_compute 34 { 35 // Forward declarations 36 class ITensor; 37 class ITensorInfo; 38 39 /** Basic function to compute the convolution layer. This function calls the following kernels/functions: 40 * 41 * Supports only NHWC data layout 42 * 43 * -# @ref cpu::CpuGemmAssemblyDispatch 44 * -# @ref NEActivationLayer, in case activation cannot be fused in the assembly dispatch 45 * 46 * Weights are transformed from OHWI to HWIO format using the following kernels: 47 * -# @ref NEPermute 48 */ 49 class NEGEMMConv2d : public IFunction 50 { 51 public: 52 /** Constructor */ 53 NEGEMMConv2d(const std::shared_ptr<IMemoryManager> &memory_manager = nullptr); 54 /** Prevent instances of this class from being copied (As this class contains pointers) */ 55 NEGEMMConv2d(const NEGEMMConv2d &) = delete; 56 /** Default move constructor */ 57 NEGEMMConv2d(NEGEMMConv2d &&) = default; 58 /** Prevent instances of this class from being copied (As this class contains pointers) */ 59 NEGEMMConv2d &operator=(const NEGEMMConv2d &) = delete; 60 /** Default move assignment operator */ 61 NEGEMMConv2d &operator=(NEGEMMConv2d &&) = default; 62 /** Destructor */ 63 ~NEGEMMConv2d(); 64 /** Set the input and output tensors. 65 * 66 * Valid data layouts: 67 * - All 68 * 69 * Valid data type configurations: 70 * |src0 |src1 |src2 |dst | 71 * |:--------------|:--------------|:--------------|:--------------| 72 * |QASYMM8 |QASYMM8 |S32 |QASYMM8 | 73 * |QASYMM8_SIGNED |QASYMM8_SIGNED |S32 |QASYMM8_SIGNED | 74 * |F16 |F16 |F16 |F16 | 75 * |F32 |F32 |F32 |F32 | 76 * |BFLOAT16 |BFLOAT16 |BFLOAT16 |BFLOAT16 | 77 * 78 * @param[in] input Source tensor. 3 lower dimensions represent a single input [width, height, IFM], 79 * while every optional dimension from 4 and above represent a batch of inputs. 80 * Data types supported: QASYMM8/QASYMM8_SIGNED/BFLOAT16/F16/F32. 81 * @param[in] weights Weights tensor. Weights are 4D tensor with dimensions [kernel_x, kernel_y, IFM, OFM]. 82 * Data type supported: QASYMM8/QASYMM8_SIGNED/QSYMM8_PER_CHANNEL/BFLOAT16/F16/F32. 83 * @param[in] biases Biases tensor. Shared biases supported. Biases are 1D tensor with dimensions [OFM]. 84 * Data type supported: Should match @p input data type, except for input of QASYMM8/QASYMM8_SIGNED type where biases should be of S32 type. 85 * @param[out] output Destination tensor. 3 lower dimensions represent a single output [width, height, OFM], while the rest represent batch of outputs. 86 * Data types supported: Same as @p input. 87 * @param[in] info Convolution layer descriptor 88 */ 89 void configure(ITensor *input, const ITensor *weights, const ITensor *biases, ITensor *output, const Conv2dInfo &info); 90 /** Static function to check if given info will lead to a valid configuration of @ref NEGEMMConv2d 91 * 92 * @param[in] input Source tensor info. 3 lower dimensions represent a single input [width, height, IFM], 93 * while every optional dimension from 4 and above represent a batch of inputs. 94 * Data types supported: QASYMM8/QASYMM8_SIGNED/BFLOAT16/F16/F32. 95 * @param[in] weights Weights tensor info. Weights are 4D tensor with dimensions [kernel_x, kernel_y, IFM, OFM]. 96 * Data type supported: QASYMM8/QASYMM8_SIGNED/QSYMM8_PER_CHANNEL/BFLOAT16/F16/F32. 97 * @param[in] biases Biases tensor info. Shared biases supported. Biases are 1D tensor with dimensions [OFM]. 98 * Data type supported: Should match @p input data type, except for input of QASYMM8/QASYMM8_SIGNED type where biases should be of S32 type. 99 * @param[in] output Destination tensor info. 3 lower dimensions represent a single output [width, height, OFM], while the rest represent batch of outputs. 100 * Data types supported: Same as @p input. 101 * @param[in] info Contains padding and stride information described in @ref PadStrideInfo. 102 * 103 * @return a status 104 */ 105 static Status validate(const ITensorInfo *input, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *output, const Conv2dInfo &info); 106 107 // Inherited methods overridden: 108 void run() override; 109 void prepare() override; 110 111 private: 112 struct Impl; 113 std::unique_ptr<Impl> _impl; 114 }; 115 } // namespace arm_compute 116 #endif /* ARM_COMPUTE_NEGEMMCONV2D_H */ 117