1 /* 2 * Copyright (c) 2017-2022 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #ifndef ARM_COMPUTE_CPU_IM2COL_KERNEL_H 25 #define ARM_COMPUTE_CPU_IM2COL_KERNEL_H 26 27 #include "arm_compute/core/Size2D.h" 28 #include "src/core/common/Macros.h" 29 #include "src/cpu/ICpuKernel.h" 30 31 namespace arm_compute 32 { 33 class ITensor; 34 namespace cpu 35 { 36 namespace kernels 37 { 38 /** Interface for the im2col reshape kernel. 39 * 40 * Rearranges image blocks into columns. It is used to strip out each convolution block to a single column. 41 * It is used to transform a convolution to a plain matrix multiplication. 42 * 43 * For example taking into account the image below and assuming 3x3 image blocks with stride of 1 we have: 44 * 45 * @f[ 46 * \left( \begin{array}{cccc} 47 * a00 & a01 & a02 & a03 \\ 48 * a10 & a11 & a12 & a13 \\ 49 * a20 & a21 & a22 & a23 \\ 50 * a30 & a31 & a32 & a33 \\ 51 * \end{array} \right) 52 * \rightarrow 53 * \left( \begin{array}{ccccccccc} 54 * a00 & a01 & a02 & a10 & a11 & a12 & a20 & a21 & a22 \\ 55 * a01 & a02 & a03 & a11 & a12 & a13 & a21 & a22 & a23 \\ 56 * a10 & a11 & a12 & a20 & a21 & a22 & a30 & a31 & a32 \\ 57 * a11 & a12 & a13 & a21 & a22 & a23 & a31 & a32 & a33 \\ 58 * \end{array} \right) 59 * @f] 60 */ 61 class CpuIm2ColKernel : public ICpuKernel<CpuIm2ColKernel> 62 { 63 public: 64 /** Default constructor */ 65 CpuIm2ColKernel() = default; 66 ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(CpuIm2ColKernel); 67 /** Set the input and output of the kernel. 68 * 69 * @param[in] src The input tensor info to convert. 3 lower dimensions represent a single input [width, height, IFM], 70 * while every optional dimension from 4 and above represent a batch of inputs. 71 * Data types supported: QASYMM8/QASYMM8_SIGNED/BFLOAT16/F16/F32 72 * Note: QASYMM8/QASYMM8_SIGNED works only for has_bias = false 73 * @param[out] dst The output tensor info. Data types supported: Same as @p input 74 * @param[in] kernel_dims The kernel dimensions (width and height). 75 * @param[in] conv_info Contains padding and stride information described in @ref PadStrideInfo. 76 * @param[in] has_bias In case biases are provided expands the matrix with 1. 77 * @param[in] dilation (Optional) Dilation, in elements, across x and y. Defaults to (1, 1). 78 * @param[in] num_groups (Optional) Number of groups when performing a grouped convolution. num_groups != 1 is not supported 79 */ 80 void configure(const ITensorInfo *src, ITensorInfo *dst, const Size2D &kernel_dims, const PadStrideInfo &conv_info, 81 bool has_bias, const Size2D &dilation = Size2D(1U, 1U), unsigned int num_groups = 1); 82 /** Static function to check if given info will lead to a valid configuration 83 * 84 * Similar to CpuIm2ColKernel::configure() 85 * 86 * @return a status 87 */ 88 static Status validate(const ITensorInfo *src, const ITensorInfo *dst, const Size2D &kernel_dims, const PadStrideInfo &conv_info, 89 bool has_bias, const Size2D &dilation = Size2D(1U, 1U), unsigned int num_groups = 1); 90 91 // Inherited methods overridden: 92 void run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) override; 93 const char *name() const override; 94 /** Return minimum workload size of the relevant kernel 95 * 96 * @param[in] platform The CPU platform used to create the context. 97 * @param[in] thread_count Number of threads in the execution. 98 * 99 * @return[out] small_network_mws Minimum workload size for requsted configuration. 100 */ 101 size_t get_mws(const CPUInfo &platform, size_t thread_count) const override; 102 103 private: 104 /** Template function to run im2col 105 * 106 * @param[in] src The input tensor info 107 * @param[out] dst The output tensor info 108 * @param[in] window Region on which to execute the kernel. (Must be a valid region of the window returned by window()). 109 */ 110 template <typename T, bool has_pads, bool is_nchw> 111 void run_im2col(const ITensor *src, ITensor *dst, const Window &window); 112 113 /** Common signature for all the specialised im2col functions 114 * 115 * @param[in] window Region on which to execute the kernel. 116 */ 117 using Im2ColFunctionPtr = void (CpuIm2ColKernel::*)(const ITensor *src, ITensor *dst, const Window &window); 118 119 Im2ColFunctionPtr _func{ nullptr }; 120 std::pair<unsigned int, unsigned int> _convolved_dims{}; 121 PadStrideInfo _conv_info{}; 122 unsigned int _kernel_width{ 0 }; 123 unsigned int _kernel_height{ 0 }; 124 bool _has_bias{ false }; 125 Size2D _dilation{ 1U, 1U }; 126 DataLayout _data_layout{ DataLayout::UNKNOWN }; 127 }; 128 } // namespace kernels 129 } // namespace cpu 130 } // namespace arm_compute 131 #endif /*ARM_COMPUTE_CPU_IM2COL_KERNEL_H */ 132