1 /* 2 * Copyright (c) 2017-2022 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #ifndef ARM_COMPUTE_CPU_POOL2D_KERNEL_H 25 #define ARM_COMPUTE_CPU_POOL2D_KERNEL_H 26 27 #include "arm_compute/core/Types.h" 28 #include "src/core/common/Macros.h" 29 #include "src/cpu/ICpuKernel.h" 30 31 namespace arm_compute 32 { 33 namespace cpu 34 { 35 namespace kernels 36 { 37 /** Interface for the pooling layer kernel */ 38 class CpuPool2dKernel : public ICpuKernel<CpuPool2dKernel> 39 { 40 private: 41 using PoolingKernelPtr = std::add_pointer<void(const ITensor *, ITensor *, ITensor *, PoolingLayerInfo &, const Window &, const Window &)>::type; 42 43 public: 44 CpuPool2dKernel() = default; 45 ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(CpuPool2dKernel); 46 /** Configure kernel for a given list of arguments 47 * 48 * @note F16 are supported for pool sizes 2 and 3 only 49 * 50 * @param[in] src Source tensor info. Data types supported: QASYMM8/QASYMM8_SIGNED/F16/F32. 51 * @param[out] dst Destination tensor info. Data types supported: Same as @p src. 52 * @param[in] pool_info Contains pooling operation information described in @ref PoolingLayerInfo. 53 * @param[out] indices (optional) The indices of the maximal values. Data type supported: U32. 54 */ 55 void configure(ITensorInfo *src, ITensorInfo *dst, const PoolingLayerInfo &pool_info, ITensorInfo *indices = nullptr); 56 /** Static function to check if given info will lead to a valid configuration 57 * 58 * Similar to CpuPool2dKernel::configure() 59 * 60 * @return a status 61 */ 62 static Status validate(const ITensorInfo *src, const ITensorInfo *dst, const PoolingLayerInfo &pool_info, const ITensorInfo *indices = nullptr); 63 64 // Inherited methods overridden: 65 void run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) override; 66 const char *name() const override; 67 68 struct PoolingKernel 69 { 70 const char *name; 71 const PoolDataTypeISASelectorPtr is_selected; 72 PoolingKernelPtr ukernel; 73 }; 74 75 static const std::vector<PoolingKernel> &get_available_kernels(); 76 77 private: 78 PoolingLayerInfo _pool_info{}; 79 DataLayout _data_layout{ DataLayout::UNKNOWN }; 80 unsigned int _num_elems_processed_per_iteration{ 0 }; 81 Size2D _pool_size{}; 82 int _pool_stride_x{}; 83 PoolingKernelPtr _run_method{ nullptr }; 84 std::string _name{}; 85 }; 86 } // namespace kernels 87 } // namespace cpu 88 } // namespace arm_compute 89 #endif /* ARM_COMPUTE_CPU_POOL2D_KERNEL_H */ 90