1 /*
2 * Copyright (c) 2021-2022 Arm Limited.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24 #include "src/cpu/kernels/CpuSubKernel.h"
25
26 #include "arm_compute/core/TensorInfo.h"
27 #include "arm_compute/core/Validate.h"
28 #include "src/core/CPP/Validate.h"
29 #include "src/core/common/Registrars.h"
30 #include "src/core/helpers/AutoConfiguration.h"
31 #include "src/core/helpers/WindowHelpers.h"
32 #include "src/cpu/kernels/add/generic/neon/impl.h"
33 #include "src/cpu/kernels/sub/neon/list.h"
34
35 #if defined(ENABLE_FP32_KERNELS)
36 namespace
37 {
38 static constexpr size_t default_mws_N1_fp32_neon = 24385;
39 static constexpr size_t default_mws_V1_fp32_neon = 40520;
40 } // namespace
41 #endif /* ENABLE_FP32_KERNELS */
42
43 namespace arm_compute
44 {
45 namespace cpu
46 {
47 namespace kernels
48 {
49 namespace
50 {
51 using CpuSubKernelDataTypeISASelectorData = CpuAddKernelDataTypeISASelectorData;
52 using CpuSubKernelDataTypeISASelectorDataPtr = CpuAddKernelDataTypeISASelectorDataPtr;
53
54 static const std::vector<CpuSubKernel::SubKernel> available_kernels =
55 {
56 {
57 "neon_fp32_sub",
__anonc166f72c0302() 58 [](const CpuSubKernelDataTypeISASelectorData & data) { return (data.dt == DataType::F32); },
59 REGISTER_FP32_NEON(arm_compute::cpu::sub_same_neon<float>)
60 },
61 {
62 "neon_fp16_sub",
__anonc166f72c0402() 63 [](const CpuSubKernelDataTypeISASelectorData & data) { return (data.dt == DataType::F16) && data.isa.fp16; },
64 REGISTER_FP16_NEON(arm_compute::cpu::sub_same_neon<float16_t>)
65 },
66 {
67 "neon_u8_sub",
__anonc166f72c0502() 68 [](const CpuSubKernelDataTypeISASelectorData & data) { return (data.dt == DataType::U8); },
69 REGISTER_INTEGER_NEON(arm_compute::cpu::sub_same_neon<uint8_t>)
70 },
71 {
72 "neon_s16_sub",
__anonc166f72c0602() 73 [](const CpuSubKernelDataTypeISASelectorData & data) { return (data.dt == DataType::S16); },
74 REGISTER_INTEGER_NEON(arm_compute::cpu::sub_same_neon<int16_t>)
75 },
76 {
77 "neon_s32_sub",
__anonc166f72c0702() 78 [](const CpuSubKernelDataTypeISASelectorData & data) { return (data.dt == DataType::S32); },
79 REGISTER_INTEGER_NEON(arm_compute::cpu::sub_same_neon<int32_t>)
80 },
81 {
82 "neon_qu8_sub_fixedpoint",
__anonc166f72c0802() 83 [](const CpuSubKernelDataTypeISASelectorData & data) { return ((data.dt == DataType::QASYMM8) && data.can_use_fixedpoint); },
84 REGISTER_QASYMM8_NEON(arm_compute::cpu::sub_qasymm8_neon_fixedpoint)
85 },
86 {
87 "neon_qs8_sub_fixedpoint",
__anonc166f72c0902() 88 [](const CpuSubKernelDataTypeISASelectorData & data) { return ((data.dt == DataType::QASYMM8_SIGNED) && data.can_use_fixedpoint); },
89 REGISTER_QASYMM8_SIGNED_NEON(arm_compute::cpu::sub_qasymm8_signed_neon_fixedpoint)
90 },
91 {
92 "neon_qu8_sub",
__anonc166f72c0a02() 93 [](const CpuSubKernelDataTypeISASelectorData & data) { return (data.dt == DataType::QASYMM8); },
94 REGISTER_QASYMM8_NEON(arm_compute::cpu::sub_qasymm8_neon)
95 },
96 {
97 "neon_qs8_sub",
__anonc166f72c0b02() 98 [](const CpuSubKernelDataTypeISASelectorData & data) { return (data.dt == DataType::QASYMM8_SIGNED); },
99 REGISTER_QASYMM8_SIGNED_NEON(arm_compute::cpu::sub_qasymm8_signed_neon)
100 },
101 {
102 "neon_qs16_sub",
__anonc166f72c0c02() 103 [](const CpuSubKernelDataTypeISASelectorData & data) { return (data.dt == DataType::QSYMM16); },
104 REGISTER_QSYMM16_NEON(arm_compute::cpu::sub_qsymm16_neon)
105 },
106 };
107
validate_arguments(const ITensorInfo & src0,const ITensorInfo & src1,const ITensorInfo & dst,ConvertPolicy policy)108 inline Status validate_arguments(const ITensorInfo &src0, const ITensorInfo &src1, const ITensorInfo &dst, ConvertPolicy policy)
109 {
110 ARM_COMPUTE_UNUSED(policy);
111 ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(&src0);
112 ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(&src0, 1, DataType::U8, DataType::QASYMM8, DataType::QASYMM8_SIGNED, DataType::QSYMM16, DataType::S16, DataType::S32, DataType::F16,
113 DataType::F32);
114 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(&src0, &src1);
115
116 const auto can_use_fixedpoint = sub_q8_neon_fixedpoint_possible(&src0, &src1, &dst);
117 const auto uk = CpuSubKernel::get_implementation<CpuSubKernelDataTypeISASelectorData>(CpuSubKernelDataTypeISASelectorData{ src0.data_type(), CPUInfo::get().get_isa(), can_use_fixedpoint });
118
119 ARM_COMPUTE_RETURN_ERROR_ON(uk == nullptr || uk->ukernel == nullptr);
120
121 const TensorShape out_shape = TensorShape::broadcast_shape(src0.tensor_shape(), src1.tensor_shape());
122 ARM_COMPUTE_RETURN_ERROR_ON_MSG(out_shape.total_size() == 0, "Inputs are not broadcast compatible");
123
124 ARM_COMPUTE_RETURN_ERROR_ON_MSG(is_data_type_quantized(src0.data_type()) && (policy == ConvertPolicy::WRAP),
125 "Convert policy cannot be WRAP if datatype is quantized");
126
127 // Validate in case of configured dst
128 if(dst.total_size() > 0)
129 {
130 ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(&src0, &dst);
131 ARM_COMPUTE_RETURN_ERROR_ON_MSG(detail::have_different_dimensions(out_shape, dst.tensor_shape(), 0),
132 "Wrong shape for dst");
133 }
134 return Status{};
135 }
136 } // namespace
137
configure(const ITensorInfo * src0,const ITensorInfo * src1,ITensorInfo * dst,ConvertPolicy policy)138 void CpuSubKernel::configure(const ITensorInfo *src0, const ITensorInfo *src1, ITensorInfo *dst, ConvertPolicy policy)
139 {
140 ARM_COMPUTE_ERROR_ON_NULLPTR(src0, src1, dst);
141 ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(*src0, *src1, *dst, policy));
142
143 const TensorShape &out_shape = TensorShape::broadcast_shape(src0->tensor_shape(), src1->tensor_shape());
144
145 // Auto initialize dst if not initialized
146 set_shape_if_empty(*dst, out_shape);
147 set_data_type_if_unknown(*dst, src0->data_type());
148
149 const auto can_use_fixedpoint = sub_q8_neon_fixedpoint_possible(src0, src1, dst);
150 const auto uk = CpuSubKernel::get_implementation<CpuSubKernelDataTypeISASelectorData>(CpuSubKernelDataTypeISASelectorData{ src0->data_type(), CPUInfo::get().get_isa(), can_use_fixedpoint });
151
152 ARM_COMPUTE_ERROR_ON_NULLPTR(uk);
153
154 _policy = policy;
155 _run_method = uk->ukernel;
156 _name = std::string("CpuSubKernel").append("/").append(uk->name);
157
158 // CpuSubKernel doesn't need padding so update_window_and_padding() can be skipped
159 Window win;
160 std::tie(win, _split_dimension) = calculate_squashed_or_max_window(*src0, *src1);
161
162 ICpuKernel::configure(win);
163 }
164
get_mws(const CPUInfo & platform,size_t thread_count) const165 size_t CpuSubKernel::get_mws(const CPUInfo &platform, size_t thread_count) const
166 {
167 ARM_COMPUTE_UNUSED(thread_count);
168
169 #if defined(ENABLE_FP32_KERNELS)
170 if(this->_run_method == &sub_same_neon<float>)
171 {
172 size_t mws = ICPPKernel::default_mws;
173 if(platform.get_cpu_model() == CPUModel::N1)
174 {
175 mws = default_mws_N1_fp32_neon;
176 }
177 else if(platform.get_cpu_model() == CPUModel::V1)
178 {
179 mws = default_mws_V1_fp32_neon;
180 }
181 else
182 {
183 return ICPPKernel::default_mws;
184 }
185
186 // tensor is 1D or was re-interpreted as 1D
187 if(this->window().shape().num_dimensions() == 1)
188 {
189 return mws;
190 }
191 else
192 {
193 // scale mws down by the number of elements along all the dimensions (x, z, w, etc) except the one
194 // that we parallelize along (the y dimension). This allows for parallelization when the Y_SIZE is small
195 // but the other sizes are large, which boosts performance.
196 mws = static_cast<size_t>(mws / (this->window().num_iterations_total() / this->window().num_iterations(1)));
197 return std::max(static_cast<size_t>(1), mws);
198 }
199 }
200 #else /* ENABLE_FP32_KERNELS */
201 ARM_COMPUTE_UNUSED(platform);
202 #endif /* ENABLE_FP32_KERNELS */
203 return ICPPKernel::default_mws;
204 }
205
validate(const ITensorInfo * src0,const ITensorInfo * src1,const ITensorInfo * dst,ConvertPolicy policy)206 Status CpuSubKernel::validate(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *dst, ConvertPolicy policy)
207 {
208 ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src0, src1, dst);
209 ARM_COMPUTE_RETURN_ON_ERROR(validate_arguments(*src0, *src1, *dst, policy));
210
211 return Status{};
212 }
213
run_op(ITensorPack & tensors,const Window & window,const ThreadInfo & info)214 void CpuSubKernel::run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info)
215 {
216 ARM_COMPUTE_UNUSED(info);
217 ARM_COMPUTE_ERROR_ON_UNCONFIGURED_KERNEL(this);
218 ARM_COMPUTE_ERROR_ON_INVALID_SUBWINDOW(ICpuKernel::window(), window);
219 ARM_COMPUTE_ERROR_ON(_run_method == nullptr);
220
221 const ITensor *src0 = tensors.get_const_tensor(TensorType::ACL_SRC_0);
222 const ITensor *src1 = tensors.get_const_tensor(TensorType::ACL_SRC_1);
223 ITensor *dst = tensors.get_tensor(TensorType::ACL_DST);
224
225 _run_method(src0, src1, dst, _policy, window);
226 }
227
name() const228 const char *CpuSubKernel::name() const
229 {
230 return _name.c_str();
231 }
232
get_available_kernels()233 const std::vector<CpuSubKernel::SubKernel> &CpuSubKernel::get_available_kernels()
234 {
235 return available_kernels;
236 }
237
238 } // namespace kernels
239 } // namespace cpu
240 } // namespace arm_compute
241