1 /* 2 * Copyright (c) 2021 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #ifndef ARM_COMPUTE_CL_DIRECT_CONV3D_H 25 #define ARM_COMPUTE_CL_DIRECT_CONV3D_H 26 27 #include "src/gpu/cl/IClKernel.h" 28 #include "src/gpu/cl/IClOperator.h" 29 30 #include <memory> 31 32 namespace arm_compute 33 { 34 class CLCompileContext; 35 struct Conv3dInfo; 36 class IClKernel; 37 38 namespace opencl 39 { 40 /** Basic function to simulate a directly convolution layer with 3 spatial dimensions. This function calls the following OpenCL kernels: 41 * 42 * -# @ref opencl::ClDirectConv3d 43 */ 44 class ClDirectConv3d : public IClOperator 45 { 46 public: 47 ClDirectConv3d() = default; 48 /** Set the src and dst tensors. 49 * 50 * Valid data layouts: 51 * - NDHWC 52 * 53 * Valid data type configurations: 54 * |src0 |src1 |src2 |dst | 55 * |:--------------|:--------------|:------|:--------------| 56 * |F16 |F16 |F16 |F16 | 57 * |F32 |F32 |F32 |F32 | 58 * |QASYMM8 |QASYMM8 |S32 |QASYMM8 | 59 * |QASYMM8_SIGNED |QASYMM8_SIGNED |S32 |QASYMM8_SIGNED | 60 * 61 * @param[in] compile_context The compile context to be used. 62 * @param[in] src0 Source tensor. 4 lower dimensions represent a single src [IFM, width, height, depth], 63 * while every optional dimension from 5 and above represent a batch of srcs. 64 * @param[in] src1 Weights tensor. Weights are 5D tensor with dimensions [OFM, IFM, kernel_w, kernel_h, kernel_d]. 65 * @param[in] src2 Biases tensor. Shared biases supported. Biases are 1D tensor with dimensions [OFM]. 66 * @param[out] dst Destination tensor. 4 lower dimensions represent a single dst [OFM, width, height, depth], while the rest represent batch of dsts. 67 * @param[in] conv3d_info Contains strides, padding, rounding, activation, dilation and fast math information. Activation and fast math are currently unused. 68 * 69 */ 70 void configure(const CLCompileContext &compile_context, const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, ITensorInfo *dst, const Conv3dInfo &conv3d_info); 71 72 /** Static function to check if given info will lead to a valid configuration 73 * 74 * Similar to ClDirectConv3d::configure() 75 * 76 * @return a status 77 */ 78 static Status validate(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *src2, const ITensorInfo *dst, const Conv3dInfo &conv3d_info); 79 80 // Inherited method overridden 81 void run(ITensorPack &tensors) override; 82 83 private: 84 std::unique_ptr<IClKernel> _direct_conv3d_kernel{ nullptr }; 85 }; 86 } // namespace opencl 87 } // namespace arm_compute 88 #endif /* ARM_COMPUTE_CL_DIRECT_CONV3D_H */