1 // Auto-generated file. Do not edit!
2 // Template: src/f16-raddstoreexpminusmax/avx2-rr1-p2.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2022 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <immintrin.h>
13
14 #include <xnnpack/intrinsics-polyfill.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16
17
xnn_f16_raddstoreexpminusmax_ukernel__avx2_rr1_p2_x48_acc2(size_t batch,const void * input,const void * max,void * output,void * sum,const union xnn_f16_expminus_params params[restrict XNN_MIN_ELEMENTS (1)])18 void xnn_f16_raddstoreexpminusmax_ukernel__avx2_rr1_p2_x48_acc2(
19 size_t batch,
20 const void* input,
21 const void* max,
22 void* output,
23 void* sum,
24 const union xnn_f16_expminus_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
25 {
26 assert(batch % sizeof(uint16_t) == 0);
27
28 const __m256 vi_max = _mm256_cvtph_ps(_mm_set1_epi16((short) *((const uint16_t*) max)));
29 const __m256 vlog2e = _mm256_load_ps(params->avx2_rr1_p2.log2e);
30 const __m256 vmagic_bias = _mm256_load_ps(params->avx2_rr1_p2.magic_bias);
31 const __m256 vminus_ln2 = _mm256_load_ps(params->avx2_rr1_p2.minus_ln2);
32 const __m256 vc2 = _mm256_load_ps(params->avx2_rr1_p2.c2);
33 const __m256 vc1 = _mm256_load_ps(params->avx2_rr1_p2.c1);
34 const __m256 vdenorm_cutoff = _mm256_load_ps(params->avx2_rr1_p2.denorm_cutoff);
35
36 const uint16_t* i = (const uint16_t*) input;
37 uint16_t* o = (uint16_t*) output;
38 __m256 vacc0 = _mm256_setzero_ps();
39 __m256 vacc1 = _mm256_setzero_ps();
40 for (; batch >= 48 * sizeof(uint16_t); batch -= 48 * sizeof(uint16_t)) {
41 const __m256 vi0 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) i));
42 const __m256 vi1 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 8)));
43 const __m256 vi2 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 16)));
44 const __m256 vi3 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 24)));
45 const __m256 vi4 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 32)));
46 const __m256 vi5 = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) (i + 40)));
47 i += 48;
48
49 const __m256 vx0 = _mm256_sub_ps(vi0, vi_max);
50 const __m256 vx1 = _mm256_sub_ps(vi1, vi_max);
51 const __m256 vx2 = _mm256_sub_ps(vi2, vi_max);
52 const __m256 vx3 = _mm256_sub_ps(vi3, vi_max);
53 const __m256 vx4 = _mm256_sub_ps(vi4, vi_max);
54 const __m256 vx5 = _mm256_sub_ps(vi5, vi_max);
55
56 __m256 vn0 = _mm256_fmadd_ps(vx0, vlog2e, vmagic_bias);
57 __m256 vn1 = _mm256_fmadd_ps(vx1, vlog2e, vmagic_bias);
58 __m256 vn2 = _mm256_fmadd_ps(vx2, vlog2e, vmagic_bias);
59 __m256 vn3 = _mm256_fmadd_ps(vx3, vlog2e, vmagic_bias);
60 __m256 vn4 = _mm256_fmadd_ps(vx4, vlog2e, vmagic_bias);
61 __m256 vn5 = _mm256_fmadd_ps(vx5, vlog2e, vmagic_bias);
62
63 const __m256 vs0 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn0), 23));
64 const __m256 vs1 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn1), 23));
65 const __m256 vs2 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn2), 23));
66 const __m256 vs3 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn3), 23));
67 const __m256 vs4 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn4), 23));
68 const __m256 vs5 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn5), 23));
69
70 vn0 = _mm256_sub_ps(vn0, vmagic_bias);
71 vn1 = _mm256_sub_ps(vn1, vmagic_bias);
72 vn2 = _mm256_sub_ps(vn2, vmagic_bias);
73 vn3 = _mm256_sub_ps(vn3, vmagic_bias);
74 vn4 = _mm256_sub_ps(vn4, vmagic_bias);
75 vn5 = _mm256_sub_ps(vn5, vmagic_bias);
76
77 __m256 vt0 = _mm256_fmadd_ps(vn0, vminus_ln2, vx0);
78 __m256 vt1 = _mm256_fmadd_ps(vn1, vminus_ln2, vx1);
79 __m256 vt2 = _mm256_fmadd_ps(vn2, vminus_ln2, vx2);
80 __m256 vt3 = _mm256_fmadd_ps(vn3, vminus_ln2, vx3);
81 __m256 vt4 = _mm256_fmadd_ps(vn4, vminus_ln2, vx4);
82 __m256 vt5 = _mm256_fmadd_ps(vn5, vminus_ln2, vx5);
83
84 const __m256 vp0 = _mm256_fmadd_ps(vc2, vt0, vc1);
85 const __m256 vp1 = _mm256_fmadd_ps(vc2, vt1, vc1);
86 const __m256 vp2 = _mm256_fmadd_ps(vc2, vt2, vc1);
87 const __m256 vp3 = _mm256_fmadd_ps(vc2, vt3, vc1);
88 const __m256 vp4 = _mm256_fmadd_ps(vc2, vt4, vc1);
89 const __m256 vp5 = _mm256_fmadd_ps(vc2, vt5, vc1);
90
91 vt0 = _mm256_mul_ps(vt0, vs0);
92 vt1 = _mm256_mul_ps(vt1, vs1);
93 vt2 = _mm256_mul_ps(vt2, vs2);
94 vt3 = _mm256_mul_ps(vt3, vs3);
95 vt4 = _mm256_mul_ps(vt4, vs4);
96 vt5 = _mm256_mul_ps(vt5, vs5);
97
98 __m256 vf0 = _mm256_fmadd_ps(vt0, vp0, vs0);
99 __m256 vf1 = _mm256_fmadd_ps(vt1, vp1, vs1);
100 __m256 vf2 = _mm256_fmadd_ps(vt2, vp2, vs2);
101 __m256 vf3 = _mm256_fmadd_ps(vt3, vp3, vs3);
102 __m256 vf4 = _mm256_fmadd_ps(vt4, vp4, vs4);
103 __m256 vf5 = _mm256_fmadd_ps(vt5, vp5, vs5);
104
105 vf0 = _mm256_andnot_ps(_mm256_cmp_ps(vx0, vdenorm_cutoff, _CMP_LT_OS), vf0);
106 vf1 = _mm256_andnot_ps(_mm256_cmp_ps(vx1, vdenorm_cutoff, _CMP_LT_OS), vf1);
107 vf2 = _mm256_andnot_ps(_mm256_cmp_ps(vx2, vdenorm_cutoff, _CMP_LT_OS), vf2);
108 vf3 = _mm256_andnot_ps(_mm256_cmp_ps(vx3, vdenorm_cutoff, _CMP_LT_OS), vf3);
109 vf4 = _mm256_andnot_ps(_mm256_cmp_ps(vx4, vdenorm_cutoff, _CMP_LT_OS), vf4);
110 vf5 = _mm256_andnot_ps(_mm256_cmp_ps(vx5, vdenorm_cutoff, _CMP_LT_OS), vf5);
111
112 _mm_storeu_si128((__m128i*) o, _mm256_cvtps_ph(vf0, _MM_FROUND_NO_EXC));
113 _mm_storeu_si128((__m128i*) (o + 8), _mm256_cvtps_ph(vf1, _MM_FROUND_NO_EXC));
114 _mm_storeu_si128((__m128i*) (o + 16), _mm256_cvtps_ph(vf2, _MM_FROUND_NO_EXC));
115 _mm_storeu_si128((__m128i*) (o + 24), _mm256_cvtps_ph(vf3, _MM_FROUND_NO_EXC));
116 _mm_storeu_si128((__m128i*) (o + 32), _mm256_cvtps_ph(vf4, _MM_FROUND_NO_EXC));
117 _mm_storeu_si128((__m128i*) (o + 40), _mm256_cvtps_ph(vf5, _MM_FROUND_NO_EXC));
118 o += 48;
119
120 vacc0 = _mm256_add_ps(vacc0, vf0);
121 vacc1 = _mm256_add_ps(vacc1, vf1);
122 vacc0 = _mm256_add_ps(vacc0, vf2);
123 vacc1 = _mm256_add_ps(vacc1, vf3);
124 vacc0 = _mm256_add_ps(vacc0, vf4);
125 vacc1 = _mm256_add_ps(vacc1, vf5);
126 }
127 vacc0 = _mm256_add_ps(vacc0, vacc1);
128
129 __m256 vacc = vacc0;
130 for (; batch >= 8 * sizeof(uint16_t); batch -= 8 * sizeof(uint16_t)) {
131 const __m256 vi = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) i));
132 i += 8;
133
134 const __m256 vx = _mm256_sub_ps(vi, vi_max);
135
136 __m256 vn = _mm256_fmadd_ps(vx, vlog2e, vmagic_bias);
137
138 const __m256 vs = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn), 23));
139
140 vn = _mm256_sub_ps(vn, vmagic_bias);
141
142 __m256 vt = _mm256_fmadd_ps(vn, vminus_ln2, vx);
143
144 const __m256 vp = _mm256_fmadd_ps(vc2, vt, vc1);
145 vt = _mm256_mul_ps(vt, vs);
146 __m256 vf = _mm256_fmadd_ps(vt, vp, vs);
147 vf = _mm256_andnot_ps(_mm256_cmp_ps(vx, vdenorm_cutoff, _CMP_LT_OS), vf);
148
149 _mm_storeu_si128((__m128i*) o, _mm256_cvtps_ph(vf, _MM_FROUND_NO_EXC));
150 o += 8;
151
152 vacc = _mm256_add_ps(vacc, vf);
153 }
154 __m128 vacc_lo = _mm_add_ps(_mm256_castps256_ps128(vacc), _mm256_extractf128_ps(vacc, 1));
155 if (batch != 0) {
156 assert(batch >= 1 * sizeof(uint16_t));
157 assert(batch <= 7 * sizeof(uint16_t));
158
159 const __m256 vi = _mm256_cvtph_ps(_mm_loadu_si128((const __m128i*) i));
160
161 const __m256 vx = _mm256_sub_ps(vi, vi_max);
162
163 __m256 vn = _mm256_fmadd_ps(vx, vlog2e, vmagic_bias);
164
165 const __m256 vs = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn), 23));
166
167 vn = _mm256_sub_ps(vn, vmagic_bias);
168
169 __m256 vt = _mm256_fmadd_ps(vn, vminus_ln2, vx);
170
171 const __m256 vp = _mm256_fmadd_ps(vc2, vt, vc1);
172 vt = _mm256_mul_ps(vt, vs);
173 __m256 vf = _mm256_fmadd_ps(vt, vp, vs);
174 vf = _mm256_andnot_ps(_mm256_cmp_ps(vx, vdenorm_cutoff, _CMP_LT_OS), vf);
175
176 __m128i vh = _mm256_cvtps_ph(vf, _MM_FROUND_NO_EXC);
177 __m128 vf_lo = _mm256_castps256_ps128(vf);
178 if (batch & (4 * sizeof(uint16_t))) {
179 _mm_storel_epi64((__m128i*) o, vh);
180 vh = _mm_unpackhi_epi64(vh, vh);
181 vacc_lo = _mm_add_ps(vacc_lo, vf_lo);
182 vf_lo = _mm256_extractf128_ps(vf, 1);
183 o += 4;
184 }
185 if (batch & (2 * sizeof(uint16_t))) {
186 _mm_storeu_si32(o, vh);
187 vh = _mm_srli_epi64(vh, 32);
188 vacc_lo = _mm_blend_ps(_mm_add_ps(vacc_lo, vf_lo), vacc_lo, 0xC);
189 vf_lo = _mm_movehl_ps(vf_lo, vf_lo);
190 o += 2;
191 }
192 if (batch & (1 * sizeof(uint16_t))) {
193 *o = (uint16_t) _mm_extract_epi16(vh, 0);
194 vacc_lo = _mm_add_ss(vacc_lo, vf_lo);
195 }
196 }
197 vacc_lo = _mm_add_ps(vacc_lo, _mm_movehl_ps(vacc_lo, vacc_lo));
198 vacc_lo = _mm_add_ss(vacc_lo, _mm_movehdup_ps(vacc_lo));
199 *((uint16_t*) sum) = (uint16_t) _mm_extract_epi16(_mm_cvtps_ph(vacc_lo, _MM_FROUND_NO_EXC), 0);
200 _mm256_zeroupper();
201 }
202