1// Copyright 2022 Google LLC 2// 3// This source code is licensed under the BSD-style license found in the 4// LICENSE file in the root directory of this source tree. 5 6$assert BATCH_TILE % 8 == 0 7$assert BATCH_TILE >= 8 8$SIMD_TILE = BATCH_TILE // 8 9$ABC = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ" 10#include <assert.h> 11 12#include <arm_neon.h> 13 14#include <xnnpack/common.h> 15#include <xnnpack/raddstoreexpminusmax.h> 16 17 18void xnn_f16_raddstoreexpminusmax_ukernel__neonfp16arith_rr2_p2_x${BATCH_TILE}${"" if ACCUMULATORS == 1 else "_acc%d" % ACCUMULATORS}( 19 size_t batch, 20 const void* input, 21 const void* max, 22 void* output, 23 void* sum, 24 const union xnn_f16_expminus_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS 25{ 26 assert(batch % sizeof(__fp16) == 0); 27 28 const float16x8_t vi_max = vld1q_dup_f16(max); 29 const float16x8_t vlog2e = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->neonfp16arith_rr2_p2.log2e)); 30 const float16x8_t vmagic_bias = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->neonfp16arith_rr2_p2.magic_bias)); 31 const float16x8_t vminus_ln2_hi = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->neonfp16arith_rr2_p2.minus_ln2_hi)); 32 const float16x8_t vminus_ln2_lo = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->neonfp16arith_rr2_p2.minus_ln2_lo)); 33 const float16x8_t vc2 = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->neonfp16arith_rr2_p2.c2)); 34 const float16x8_t vc1 = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->neonfp16arith_rr2_p2.c1)); 35 const float16x8_t vdenorm_cutoff = vreinterpretq_f16_u16(vld1q_dup_u16(¶ms->neonfp16arith_rr2_p2.denorm_cutoff)); 36 37 const __fp16* i = (const __fp16*) input; 38 __fp16* o = (__fp16*) output; 39 $if BATCH_TILE > 8: 40 $for K in range(ACCUMULATORS): 41 float16x8_t vacc${K} = vmovq_n_f16(0.0f); 42 for (; batch >= ${BATCH_TILE} * sizeof(__fp16); batch -= ${BATCH_TILE} * sizeof(__fp16)) { 43 $for N in range(SIMD_TILE): 44 const float16x8_t vi${ABC[N]} = vld1q_f16(i); i += 8; 45 46 $for N in range(SIMD_TILE): 47 const float16x8_t vx${ABC[N]} = vsubq_f16(vi${ABC[N]}, vi_max); 48 49 $for N in range(SIMD_TILE): 50 float16x8_t vn${ABC[N]} = vfmaq_f16(vmagic_bias, vx${ABC[N]}, vlog2e); 51 52 $for N in range(SIMD_TILE): 53 const float16x8_t vs${ABC[N]} = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn${ABC[N]}), 10)); 54 55 $for N in range(SIMD_TILE): 56 vn${ABC[N]} = vsubq_f16(vn${ABC[N]}, vmagic_bias); 57 58 $for N in range(SIMD_TILE): 59 float16x8_t vt${ABC[N]} = vfmaq_f16(vx${ABC[N]}, vn${ABC[N]}, vminus_ln2_hi); 60 61 $for N in range(SIMD_TILE): 62 vt${ABC[N]} = vfmaq_f16(vt${ABC[N]}, vn${ABC[N]}, vminus_ln2_lo); 63 64 $for N in range(SIMD_TILE): 65 const float16x8_t vp${ABC[N]} = vfmaq_f16(vc1, vc2, vt${ABC[N]}); 66 67 $for N in range(SIMD_TILE): 68 vt${ABC[N]} = vmulq_f16(vt${ABC[N]}, vs${ABC[N]}); 69 70 $for N in range(SIMD_TILE): 71 float16x8_t vf${ABC[N]} = vfmaq_f16(vs${ABC[N]}, vp${ABC[N]}, vt${ABC[N]}); 72 const uint16x8_t vm${ABC[N]} = vcltq_f16(vx${ABC[N]}, vdenorm_cutoff); 73 74 $for N in range(SIMD_TILE): 75 vf${ABC[N]} = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf${ABC[N]}), vm${ABC[N]})); 76 77 $for N in range(SIMD_TILE): 78 vst1q_f16(o, vf${ABC[N]}); o += 8; 79 80 $for N in range(SIMD_TILE): 81 vacc${N % ACCUMULATORS} = vaddq_f16(vacc${N % ACCUMULATORS}, vf${ABC[N]}); 82 } 83 $if ACCUMULATORS > 1: 84 $ACC_SLICE = 1 85 $while ACC_SLICE < ACCUMULATORS: 86 $for A in range(0, ACCUMULATORS, ACC_SLICE * 2): 87 $if A + ACC_SLICE < ACCUMULATORS: 88 vacc${A} = vaddq_f16(vacc${A}, vacc${A + ACC_SLICE}); 89 $ACC_SLICE *= 2 90 91 float16x8_t vacc = vacc0; 92 $else: 93 float16x8_t vacc = vmovq_n_f16(0.0f); 94 for (; batch >= 8 * sizeof(__fp16); batch -= 8 * sizeof(__fp16)) { 95 const float16x8_t vi = vld1q_f16(i); i += 8; 96 97 const float16x8_t vx = vsubq_f16(vi, vi_max); 98 99 float16x8_t vn = vfmaq_f16(vmagic_bias, vx, vlog2e); 100 const float16x8_t vs = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn), 10)); 101 vn = vsubq_f16(vn, vmagic_bias); 102 103 float16x8_t vt = vfmaq_f16(vx, vn, vminus_ln2_hi); 104 vt = vfmaq_f16(vt, vn, vminus_ln2_lo); 105 106 const float16x8_t vp = vfmaq_f16(vc1, vc2, vt); 107 vt = vmulq_f16(vt, vs); 108 109 float16x8_t vf = vfmaq_f16(vs, vp, vt); 110 const uint16x8_t vm = vcltq_f16(vx, vdenorm_cutoff); 111 vf = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf), vm)); 112 113 vst1q_f16(o, vf); o += 8; 114 115 vacc = vaddq_f16(vacc, vf); 116 } 117 float16x4_t vacc_lo = vadd_f16(vget_low_f16(vacc), vget_high_f16(vacc)); 118 if (batch != 0) { 119 assert(batch >= 1 * sizeof(__fp16)); 120 assert(batch <= 7 * sizeof(__fp16)); 121 const float16x8_t vi = vld1q_f16(i); 122 123 const float16x8_t vx = vsubq_f16(vi, vi_max); 124 125 float16x8_t vn = vfmaq_f16(vmagic_bias, vx, vlog2e); 126 const float16x8_t vs = vreinterpretq_f16_s16(vshlq_n_s16(vreinterpretq_s16_f16(vn), 10)); 127 vn = vsubq_f16(vn, vmagic_bias); 128 129 float16x8_t vt = vfmaq_f16(vx, vn, vminus_ln2_hi); 130 vt = vfmaq_f16(vt, vn, vminus_ln2_lo); 131 132 const float16x8_t vp = vfmaq_f16(vc1, vc2, vt); 133 vt = vmulq_f16(vt, vs); 134 135 float16x8_t vf = vfmaq_f16(vs, vp, vt); 136 const uint16x8_t vm = vcltq_f16(vx, vdenorm_cutoff); 137 vf = vreinterpretq_f16_u16(vbicq_u16(vreinterpretq_u16_f16(vf), vm)); 138 139 float16x4_t vf_lo = vget_low_f16(vf); 140 if (batch & (4 * sizeof(__fp16))) { 141 vst1_f16(o, vf_lo); o += 4; 142 vacc_lo = vadd_f16(vacc_lo, vf_lo); 143 vf_lo = vget_high_f16(vf); 144 } 145 if (batch & (2 * sizeof(__fp16))) { 146 vst1_lane_u32((void*) o, vreinterpret_u32_f16(vf_lo), 0); o += 2; 147 vacc_lo = vadd_f16(vacc_lo, vreinterpret_f16_u64(vshl_n_u64(vreinterpret_u64_f16(vf_lo), 32))); 148 vf_lo = vext_f16(vf_lo, vf_lo, 2); 149 } 150 if (batch & (1 * sizeof(__fp16))) { 151 vst1_lane_f16(o, vf_lo, 0); 152 vacc_lo = vadd_f16(vacc_lo, vreinterpret_f16_u64(vshl_n_u64(vreinterpret_u64_f16(vf_lo), 48))); 153 } 154 } 155 vacc_lo = vpadd_f16(vacc_lo, vacc_lo); 156 *((__fp16*) sum) = vget_lane_f16(vacc_lo, 0) + vget_lane_f16(vacc_lo, 1); 157} 158