1 // Auto-generated file. Do not edit!
2 // Template: src/f32-velu/avx2-rr1-p6.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2020 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <immintrin.h>
13
14 #include <xnnpack/common.h>
15 #include <xnnpack/vunary.h>
16
17
xnn_f32_velu_ukernel__avx2_rr1_p6_x72(size_t n,const float * x,float * y,const union xnn_f32_elu_params params[restrict XNN_MIN_ELEMENTS (1)])18 void xnn_f32_velu_ukernel__avx2_rr1_p6_x72(
19 size_t n,
20 const float* x,
21 float* y,
22 const union xnn_f32_elu_params params[restrict XNN_MIN_ELEMENTS(1)])
23 {
24 assert(n % sizeof(float) == 0);
25
26 const __m256 vprescale = _mm256_load_ps(params->avx2_rr1_p6.prescale);
27 const __m256 valpha = _mm256_load_ps(params->avx2_rr1_p6.alpha);
28 const __m256 vbeta = _mm256_load_ps(params->avx2_rr1_p6.beta);
29 const __m256 vsat_cutoff = _mm256_load_ps(params->avx2_rr1_p6.sat_cutoff);
30 const __m256 vmagic_bias = _mm256_load_ps(params->avx2_rr1_p6.magic_bias);
31 const __m256 vlog2e = _mm256_load_ps(params->avx2_rr1_p6.log2e);
32 const __m256 vminus_ln2 = _mm256_load_ps(params->avx2_rr1_p6.minus_ln2);
33 const __m256 vc6 = _mm256_load_ps(params->avx2_rr1_p6.c6);
34 const __m256 vc5 = _mm256_load_ps(params->avx2_rr1_p6.c5);
35 const __m256 vc4 = _mm256_load_ps(params->avx2_rr1_p6.c4);
36 const __m256 vc3 = _mm256_load_ps(params->avx2_rr1_p6.c3);
37 const __m256 vc2 = _mm256_load_ps(params->avx2_rr1_p6.c2);
38
39 for (; n >= 72 * sizeof(float); n -= 72 * sizeof(float)) {
40 __m256 vx0 = _mm256_loadu_ps(x);
41 __m256 vx1 = _mm256_loadu_ps(x + 8);
42 __m256 vx2 = _mm256_loadu_ps(x + 16);
43 __m256 vx3 = _mm256_loadu_ps(x + 24);
44 __m256 vx4 = _mm256_loadu_ps(x + 32);
45 __m256 vx5 = _mm256_loadu_ps(x + 40);
46 __m256 vx6 = _mm256_loadu_ps(x + 48);
47 __m256 vx7 = _mm256_loadu_ps(x + 56);
48 __m256 vx8 = _mm256_loadu_ps(x + 64);
49 x += 72;
50
51 const __m256 vz0 = _mm256_max_ps(vsat_cutoff, _mm256_mul_ps(vx0, vprescale));
52 const __m256 vz1 = _mm256_max_ps(vsat_cutoff, _mm256_mul_ps(vx1, vprescale));
53 const __m256 vz2 = _mm256_max_ps(vsat_cutoff, _mm256_mul_ps(vx2, vprescale));
54 const __m256 vz3 = _mm256_max_ps(vsat_cutoff, _mm256_mul_ps(vx3, vprescale));
55 const __m256 vz4 = _mm256_max_ps(vsat_cutoff, _mm256_mul_ps(vx4, vprescale));
56 const __m256 vz5 = _mm256_max_ps(vsat_cutoff, _mm256_mul_ps(vx5, vprescale));
57 const __m256 vz6 = _mm256_max_ps(vsat_cutoff, _mm256_mul_ps(vx6, vprescale));
58 const __m256 vz7 = _mm256_max_ps(vsat_cutoff, _mm256_mul_ps(vx7, vprescale));
59 const __m256 vz8 = _mm256_max_ps(vsat_cutoff, _mm256_mul_ps(vx8, vprescale));
60
61 __m256 vn0 = _mm256_fmadd_ps(vz0, vlog2e, vmagic_bias);
62 __m256 vn1 = _mm256_fmadd_ps(vz1, vlog2e, vmagic_bias);
63 __m256 vn2 = _mm256_fmadd_ps(vz2, vlog2e, vmagic_bias);
64 __m256 vn3 = _mm256_fmadd_ps(vz3, vlog2e, vmagic_bias);
65 __m256 vn4 = _mm256_fmadd_ps(vz4, vlog2e, vmagic_bias);
66 __m256 vn5 = _mm256_fmadd_ps(vz5, vlog2e, vmagic_bias);
67 __m256 vn6 = _mm256_fmadd_ps(vz6, vlog2e, vmagic_bias);
68 __m256 vn7 = _mm256_fmadd_ps(vz7, vlog2e, vmagic_bias);
69 __m256 vn8 = _mm256_fmadd_ps(vz8, vlog2e, vmagic_bias);
70
71 __m256 vs0 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn0), 23));
72 vn0 = _mm256_sub_ps(vn0, vmagic_bias);
73 __m256 vs1 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn1), 23));
74 vn1 = _mm256_sub_ps(vn1, vmagic_bias);
75 __m256 vs2 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn2), 23));
76 vn2 = _mm256_sub_ps(vn2, vmagic_bias);
77 __m256 vs3 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn3), 23));
78 vn3 = _mm256_sub_ps(vn3, vmagic_bias);
79 __m256 vs4 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn4), 23));
80 vn4 = _mm256_sub_ps(vn4, vmagic_bias);
81 __m256 vs5 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn5), 23));
82 vn5 = _mm256_sub_ps(vn5, vmagic_bias);
83 __m256 vs6 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn6), 23));
84 vn6 = _mm256_sub_ps(vn6, vmagic_bias);
85 __m256 vs7 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn7), 23));
86 vn7 = _mm256_sub_ps(vn7, vmagic_bias);
87 __m256 vs8 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn8), 23));
88 vn8 = _mm256_sub_ps(vn8, vmagic_bias);
89
90 __m256 vt0 = _mm256_fmadd_ps(vn0, vminus_ln2, vz0);
91 __m256 vt1 = _mm256_fmadd_ps(vn1, vminus_ln2, vz1);
92 __m256 vt2 = _mm256_fmadd_ps(vn2, vminus_ln2, vz2);
93 __m256 vt3 = _mm256_fmadd_ps(vn3, vminus_ln2, vz3);
94 __m256 vt4 = _mm256_fmadd_ps(vn4, vminus_ln2, vz4);
95 __m256 vt5 = _mm256_fmadd_ps(vn5, vminus_ln2, vz5);
96 __m256 vt6 = _mm256_fmadd_ps(vn6, vminus_ln2, vz6);
97 __m256 vt7 = _mm256_fmadd_ps(vn7, vminus_ln2, vz7);
98 __m256 vt8 = _mm256_fmadd_ps(vn8, vminus_ln2, vz8);
99
100 __m256 vp0 = _mm256_fmadd_ps(vc6, vt0, vc5);
101 __m256 vp1 = _mm256_fmadd_ps(vc6, vt1, vc5);
102 __m256 vp2 = _mm256_fmadd_ps(vc6, vt2, vc5);
103 __m256 vp3 = _mm256_fmadd_ps(vc6, vt3, vc5);
104 __m256 vp4 = _mm256_fmadd_ps(vc6, vt4, vc5);
105 __m256 vp5 = _mm256_fmadd_ps(vc6, vt5, vc5);
106 __m256 vp6 = _mm256_fmadd_ps(vc6, vt6, vc5);
107 __m256 vp7 = _mm256_fmadd_ps(vc6, vt7, vc5);
108 __m256 vp8 = _mm256_fmadd_ps(vc6, vt8, vc5);
109
110 vp0 = _mm256_fmadd_ps(vp0, vt0, vc4);
111 vp1 = _mm256_fmadd_ps(vp1, vt1, vc4);
112 vp2 = _mm256_fmadd_ps(vp2, vt2, vc4);
113 vp3 = _mm256_fmadd_ps(vp3, vt3, vc4);
114 vp4 = _mm256_fmadd_ps(vp4, vt4, vc4);
115 vp5 = _mm256_fmadd_ps(vp5, vt5, vc4);
116 vp6 = _mm256_fmadd_ps(vp6, vt6, vc4);
117 vp7 = _mm256_fmadd_ps(vp7, vt7, vc4);
118 vp8 = _mm256_fmadd_ps(vp8, vt8, vc4);
119
120 vp0 = _mm256_fmadd_ps(vp0, vt0, vc3);
121 vp1 = _mm256_fmadd_ps(vp1, vt1, vc3);
122 vp2 = _mm256_fmadd_ps(vp2, vt2, vc3);
123 vp3 = _mm256_fmadd_ps(vp3, vt3, vc3);
124 vp4 = _mm256_fmadd_ps(vp4, vt4, vc3);
125 vp5 = _mm256_fmadd_ps(vp5, vt5, vc3);
126 vp6 = _mm256_fmadd_ps(vp6, vt6, vc3);
127 vp7 = _mm256_fmadd_ps(vp7, vt7, vc3);
128 vp8 = _mm256_fmadd_ps(vp8, vt8, vc3);
129
130 vp0 = _mm256_fmadd_ps(vp0, vt0, vc2);
131 vp1 = _mm256_fmadd_ps(vp1, vt1, vc2);
132 vp2 = _mm256_fmadd_ps(vp2, vt2, vc2);
133 vp3 = _mm256_fmadd_ps(vp3, vt3, vc2);
134 vp4 = _mm256_fmadd_ps(vp4, vt4, vc2);
135 vp5 = _mm256_fmadd_ps(vp5, vt5, vc2);
136 vp6 = _mm256_fmadd_ps(vp6, vt6, vc2);
137 vp7 = _mm256_fmadd_ps(vp7, vt7, vc2);
138 vp8 = _mm256_fmadd_ps(vp8, vt8, vc2);
139
140 vp0 = _mm256_mul_ps(vp0, vt0);
141 vt0 = _mm256_mul_ps(vt0, vs0);
142 vp1 = _mm256_mul_ps(vp1, vt1);
143 vt1 = _mm256_mul_ps(vt1, vs1);
144 vp2 = _mm256_mul_ps(vp2, vt2);
145 vt2 = _mm256_mul_ps(vt2, vs2);
146 vp3 = _mm256_mul_ps(vp3, vt3);
147 vt3 = _mm256_mul_ps(vt3, vs3);
148 vp4 = _mm256_mul_ps(vp4, vt4);
149 vt4 = _mm256_mul_ps(vt4, vs4);
150 vp5 = _mm256_mul_ps(vp5, vt5);
151 vt5 = _mm256_mul_ps(vt5, vs5);
152 vp6 = _mm256_mul_ps(vp6, vt6);
153 vt6 = _mm256_mul_ps(vt6, vs6);
154 vp7 = _mm256_mul_ps(vp7, vt7);
155 vt7 = _mm256_mul_ps(vt7, vs7);
156 vp8 = _mm256_mul_ps(vp8, vt8);
157 vt8 = _mm256_mul_ps(vt8, vs8);
158
159 vs0 = _mm256_fmsub_ps(vs0, valpha, valpha);
160 vp0 = _mm256_fmadd_ps(vp0, vt0, vt0);
161 vs1 = _mm256_fmsub_ps(vs1, valpha, valpha);
162 vp1 = _mm256_fmadd_ps(vp1, vt1, vt1);
163 vs2 = _mm256_fmsub_ps(vs2, valpha, valpha);
164 vp2 = _mm256_fmadd_ps(vp2, vt2, vt2);
165 vs3 = _mm256_fmsub_ps(vs3, valpha, valpha);
166 vp3 = _mm256_fmadd_ps(vp3, vt3, vt3);
167 vs4 = _mm256_fmsub_ps(vs4, valpha, valpha);
168 vp4 = _mm256_fmadd_ps(vp4, vt4, vt4);
169 vs5 = _mm256_fmsub_ps(vs5, valpha, valpha);
170 vp5 = _mm256_fmadd_ps(vp5, vt5, vt5);
171 vs6 = _mm256_fmsub_ps(vs6, valpha, valpha);
172 vp6 = _mm256_fmadd_ps(vp6, vt6, vt6);
173 vs7 = _mm256_fmsub_ps(vs7, valpha, valpha);
174 vp7 = _mm256_fmadd_ps(vp7, vt7, vt7);
175 vs8 = _mm256_fmsub_ps(vs8, valpha, valpha);
176 vp8 = _mm256_fmadd_ps(vp8, vt8, vt8);
177
178 const __m256 ve0 = _mm256_fmadd_ps(vp0, valpha, vs0);
179 vx0 = _mm256_mul_ps(vx0, vbeta);
180 const __m256 ve1 = _mm256_fmadd_ps(vp1, valpha, vs1);
181 vx1 = _mm256_mul_ps(vx1, vbeta);
182 const __m256 ve2 = _mm256_fmadd_ps(vp2, valpha, vs2);
183 vx2 = _mm256_mul_ps(vx2, vbeta);
184 const __m256 ve3 = _mm256_fmadd_ps(vp3, valpha, vs3);
185 vx3 = _mm256_mul_ps(vx3, vbeta);
186 const __m256 ve4 = _mm256_fmadd_ps(vp4, valpha, vs4);
187 vx4 = _mm256_mul_ps(vx4, vbeta);
188 const __m256 ve5 = _mm256_fmadd_ps(vp5, valpha, vs5);
189 vx5 = _mm256_mul_ps(vx5, vbeta);
190 const __m256 ve6 = _mm256_fmadd_ps(vp6, valpha, vs6);
191 vx6 = _mm256_mul_ps(vx6, vbeta);
192 const __m256 ve7 = _mm256_fmadd_ps(vp7, valpha, vs7);
193 vx7 = _mm256_mul_ps(vx7, vbeta);
194 const __m256 ve8 = _mm256_fmadd_ps(vp8, valpha, vs8);
195 vx8 = _mm256_mul_ps(vx8, vbeta);
196
197 const __m256 vy0 = _mm256_blendv_ps(vx0, ve0, vx0);
198 const __m256 vy1 = _mm256_blendv_ps(vx1, ve1, vx1);
199 const __m256 vy2 = _mm256_blendv_ps(vx2, ve2, vx2);
200 const __m256 vy3 = _mm256_blendv_ps(vx3, ve3, vx3);
201 const __m256 vy4 = _mm256_blendv_ps(vx4, ve4, vx4);
202 const __m256 vy5 = _mm256_blendv_ps(vx5, ve5, vx5);
203 const __m256 vy6 = _mm256_blendv_ps(vx6, ve6, vx6);
204 const __m256 vy7 = _mm256_blendv_ps(vx7, ve7, vx7);
205 const __m256 vy8 = _mm256_blendv_ps(vx8, ve8, vx8);
206
207 _mm256_storeu_ps(y, vy0);
208 _mm256_storeu_ps(y + 8, vy1);
209 _mm256_storeu_ps(y + 16, vy2);
210 _mm256_storeu_ps(y + 24, vy3);
211 _mm256_storeu_ps(y + 32, vy4);
212 _mm256_storeu_ps(y + 40, vy5);
213 _mm256_storeu_ps(y + 48, vy6);
214 _mm256_storeu_ps(y + 56, vy7);
215 _mm256_storeu_ps(y + 64, vy8);
216 y += 72;
217 }
218 for (; n >= 8 * sizeof(float); n -= 8 * sizeof(float)) {
219 __m256 vx = _mm256_loadu_ps(x);
220 x += 8;
221
222 const __m256 vz = _mm256_max_ps(vsat_cutoff, _mm256_mul_ps(vx, vprescale));
223
224 __m256 vn = _mm256_fmadd_ps(vz, vlog2e, vmagic_bias);
225 __m256 vs = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn), 23));
226 vn = _mm256_sub_ps(vn, vmagic_bias);
227
228 __m256 vt = _mm256_fmadd_ps(vn, vminus_ln2, vz);
229
230 __m256 vp = _mm256_fmadd_ps(vc6, vt, vc5);
231 vp = _mm256_fmadd_ps(vp, vt, vc4);
232 vp = _mm256_fmadd_ps(vp, vt, vc3);
233 vp = _mm256_fmadd_ps(vp, vt, vc2);
234 vp = _mm256_mul_ps(vp, vt);
235
236 vt = _mm256_mul_ps(vt, vs);
237 vs = _mm256_fmsub_ps(vs, valpha, valpha);
238 vp = _mm256_fmadd_ps(vp, vt, vt);
239 const __m256 ve = _mm256_fmadd_ps(vp, valpha, vs);
240
241 vx = _mm256_mul_ps(vx, vbeta);
242 const __m256 vy = _mm256_blendv_ps(vx, ve, vx);
243
244 _mm256_storeu_ps(y, vy);
245 y += 8;
246 }
247 if XNN_UNLIKELY(n != 0) {
248 assert(n >= 1 * sizeof(float));
249 assert(n <= 7 * sizeof(float));
250 const __m256i vmask = _mm256_loadu_si256((const __m256i*) ((uintptr_t) ¶ms->avx2_rr1_p6.mask_table[7] - n));
251
252 __m256 vx = _mm256_maskload_ps(x, vmask);
253
254 const __m256 vz = _mm256_max_ps(vsat_cutoff, _mm256_mul_ps(vx, vprescale));
255
256 __m256 vn = _mm256_fmadd_ps(vz, vlog2e, vmagic_bias);
257 __m256 vs = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn), 23));
258 vn = _mm256_sub_ps(vn, vmagic_bias);
259
260 __m256 vt = _mm256_fmadd_ps(vn, vminus_ln2, vz);
261
262 __m256 vp = _mm256_fmadd_ps(vc6, vt, vc5);
263 vp = _mm256_fmadd_ps(vp, vt, vc4);
264 vp = _mm256_fmadd_ps(vp, vt, vc3);
265 vp = _mm256_fmadd_ps(vp, vt, vc2);
266 vp = _mm256_mul_ps(vp, vt);
267
268 vt = _mm256_mul_ps(vt, vs);
269 vs = _mm256_fmsub_ps(vs, valpha, valpha);
270 vp = _mm256_fmadd_ps(vp, vt, vt);
271 const __m256 ve = _mm256_fmadd_ps(vp, valpha, vs);
272
273 vx = _mm256_mul_ps(vx, vbeta);
274 const __m256 vy = _mm256_blendv_ps(vx, ve, vx);
275
276 __m128 vy_lo = _mm256_castps256_ps128(vy);
277 if (n & (4 * sizeof(float))) {
278 _mm_storeu_ps(y, vy_lo);
279 vy_lo = _mm256_extractf128_ps(vy, 1);
280 y += 4;
281 }
282 if (n & (2 * sizeof(float))) {
283 _mm_storel_pi((__m64*) y, vy_lo);
284 vy_lo = _mm_movehl_ps(vy_lo, vy_lo);
285 y += 2;
286 }
287 if (n & (1 * sizeof(float))) {
288 _mm_store_ss(y, vy_lo);
289 }
290 }
291 }
292