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1 // Auto-generated file. Do not edit!
2 //   Template: src/qs8-gemm/c4-neon-mull-shuffle.c.in
3 //   Generator: tools/xngen
4 //
5 // Copyright 2021 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9 
10 #include <assert.h>
11 
12 #include <arm_neon.h>
13 
14 #include <xnnpack/gemm.h>
15 #include <xnnpack/math.h>
16 
17 
xnn_qs8_gemm_minmax_rndnu_ukernel_2x8c4s2__neon_mull(size_t mr,size_t nc,size_t kc,const int8_t * restrict a,size_t a_stride,const void * restrict w,int8_t * restrict c,size_t cm_stride,size_t cn_stride,const union xnn_qs8_conv_minmax_params params[restrict XNN_MIN_ELEMENTS (1)])18 void xnn_qs8_gemm_minmax_rndnu_ukernel_2x8c4s2__neon_mull(
19     size_t mr,
20     size_t nc,
21     size_t kc,
22     const int8_t* restrict a,
23     size_t a_stride,
24     const void* restrict w,
25     int8_t* restrict c,
26     size_t cm_stride,
27     size_t cn_stride,
28     const union xnn_qs8_conv_minmax_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
29 {
30   assert(mr != 0);
31   assert(mr <= 2);
32   assert(nc != 0);
33   assert(kc != 0);
34   assert(kc % sizeof(int8_t) == 0);
35   assert(a != NULL);
36   assert(w != NULL);
37   assert(c != NULL);
38 
39   const int8_t* a0 = a;
40   int8_t* c0 = c;
41   const int8_t* a1 = (const int8_t*) ((uintptr_t) a0 + a_stride);
42   int8_t* c1 = (int8_t*) ((uintptr_t) c0 + cm_stride);
43   if XNN_UNPREDICTABLE(mr != 2) {
44     a1 = a0;
45     c1 = c0;
46   }
47 
48   kc = round_up_po2(kc, 8 * sizeof(int8_t));
49   do {
50     int32x4_t vacc0x01 = vreinterpretq_s32_u64(vmovl_u32(vld1_u32(w))); w = (const int32_t*) w + 2;
51     int32x4_t vacc0x23 = vreinterpretq_s32_u64(vmovl_u32(vld1_u32(w))); w = (const int32_t*) w + 2;
52     int32x4_t vacc0x45 = vreinterpretq_s32_u64(vmovl_u32(vld1_u32(w))); w = (const int32_t*) w + 2;
53     int32x4_t vacc0x67 = vreinterpretq_s32_u64(vmovl_u32(vld1_u32(w))); w = (const int32_t*) w + 2;
54     int32x4_t vacc1x01 = vacc0x01;
55     int32x4_t vacc1x23 = vacc0x23;
56     int32x4_t vacc1x45 = vacc0x45;
57     int32x4_t vacc1x67 = vacc0x67;
58 
59     size_t k = kc;
60     do {
61       int8x8_t va0x0 = vld1_s8(a0); a0 += 8;
62       int8x8_t va1x0 = vld1_s8(a1); a1 += 8;
63 
64       const int8x8_t vb01c0x0 = vld1_s8(w); w = (const int8_t*) w + 8;
65       const int8x8_t vb23c0x0 = vld1_s8(w); w = (const int8_t*) w + 8;
66       const int8x8_t vb45c0x0 = vld1_s8(w); w = (const int8_t*) w + 8;
67       const int8x8_t vb67c0x0 = vld1_s8(w); w = (const int8_t*) w + 8;
68       const int8x8_t vb01c1x0 = vld1_s8(w); w = (const int8_t*) w + 8;
69       const int8x8_t vb23c1x0 = vld1_s8(w); w = (const int8_t*) w + 8;
70       const int8x8_t vb45c1x0 = vld1_s8(w); w = (const int8_t*) w + 8;
71       const int8x8_t vb67c1x0 = vld1_s8(w); w = (const int8_t*) w + 8;
72 
73       int16x8_t vprod0x01c0 = vmull_s8(vb01c0x0, va0x0);
74       int16x8_t vprod1x01c0 = vmull_s8(vb01c0x0, va1x0);
75       vacc0x01 = vpadalq_s16(vacc0x01, vprod0x01c0);
76       vacc1x01 = vpadalq_s16(vacc1x01, vprod1x01c0);
77       int16x8_t vprod0x23c0 = vmull_s8(vb23c0x0, va0x0);
78       int16x8_t vprod1x23c0 = vmull_s8(vb23c0x0, va1x0);
79       vacc0x23 = vpadalq_s16(vacc0x23, vprod0x23c0);
80       vacc1x23 = vpadalq_s16(vacc1x23, vprod1x23c0);
81       int16x8_t vprod0x45c0 = vmull_s8(vb45c0x0, va0x0);
82       int16x8_t vprod1x45c0 = vmull_s8(vb45c0x0, va1x0);
83       vacc0x45 = vpadalq_s16(vacc0x45, vprod0x45c0);
84       vacc1x45 = vpadalq_s16(vacc1x45, vprod1x45c0);
85       int16x8_t vprod0x67c0 = vmull_s8(vb67c0x0, va0x0);
86       int16x8_t vprod1x67c0 = vmull_s8(vb67c0x0, va1x0);
87       vacc0x67 = vpadalq_s16(vacc0x67, vprod0x67c0);
88       vacc1x67 = vpadalq_s16(vacc1x67, vprod1x67c0);
89       va0x0 = vext_s8(va0x0, va0x0, 4);
90       va1x0 = vext_s8(va1x0, va1x0, 4);
91       int16x8_t vprod0x01c1 = vmull_s8(vb01c1x0, va0x0);
92       int16x8_t vprod1x01c1 = vmull_s8(vb01c1x0, va1x0);
93       vacc0x01 = vpadalq_s16(vacc0x01, vprod0x01c1);
94       vacc1x01 = vpadalq_s16(vacc1x01, vprod1x01c1);
95       int16x8_t vprod0x23c1 = vmull_s8(vb23c1x0, va0x0);
96       int16x8_t vprod1x23c1 = vmull_s8(vb23c1x0, va1x0);
97       vacc0x23 = vpadalq_s16(vacc0x23, vprod0x23c1);
98       vacc1x23 = vpadalq_s16(vacc1x23, vprod1x23c1);
99       int16x8_t vprod0x45c1 = vmull_s8(vb45c1x0, va0x0);
100       int16x8_t vprod1x45c1 = vmull_s8(vb45c1x0, va1x0);
101       vacc0x45 = vpadalq_s16(vacc0x45, vprod0x45c1);
102       vacc1x45 = vpadalq_s16(vacc1x45, vprod1x45c1);
103       int16x8_t vprod0x67c1 = vmull_s8(vb67c1x0, va0x0);
104       int16x8_t vprod1x67c1 = vmull_s8(vb67c1x0, va1x0);
105       vacc0x67 = vpadalq_s16(vacc0x67, vprod0x67c1);
106       vacc1x67 = vpadalq_s16(vacc1x67, vprod1x67c1);
107 
108       k -= 8 * sizeof(int8_t);
109     } while (k != 0);
110 
111 #if XNN_ARCH_ARM64
112     int32x4_t vacc0x0123 = vpaddq_s32(vacc0x01, vacc0x23);
113     int32x4_t vacc0x4567 = vpaddq_s32(vacc0x45, vacc0x67);
114     int32x4_t vacc1x0123 = vpaddq_s32(vacc1x01, vacc1x23);
115     int32x4_t vacc1x4567 = vpaddq_s32(vacc1x45, vacc1x67);
116 #else
117     const int32x2_t vsum0x01 = vpadd_s32(vget_low_s32(vacc0x01), vget_high_s32(vacc0x01));
118     const int32x2_t vsum0x23 = vpadd_s32(vget_low_s32(vacc0x23), vget_high_s32(vacc0x23));
119     int32x4_t vacc0x0123 = vcombine_s32(vsum0x01, vsum0x23);
120     const int32x2_t vsum0x45 = vpadd_s32(vget_low_s32(vacc0x45), vget_high_s32(vacc0x45));
121     const int32x2_t vsum0x67 = vpadd_s32(vget_low_s32(vacc0x67), vget_high_s32(vacc0x67));
122     int32x4_t vacc0x4567 = vcombine_s32(vsum0x45, vsum0x67);
123     const int32x2_t vsum1x01 = vpadd_s32(vget_low_s32(vacc1x01), vget_high_s32(vacc1x01));
124     const int32x2_t vsum1x23 = vpadd_s32(vget_low_s32(vacc1x23), vget_high_s32(vacc1x23));
125     int32x4_t vacc1x0123 = vcombine_s32(vsum1x01, vsum1x23);
126     const int32x2_t vsum1x45 = vpadd_s32(vget_low_s32(vacc1x45), vget_high_s32(vacc1x45));
127     const int32x2_t vsum1x67 = vpadd_s32(vget_low_s32(vacc1x67), vget_high_s32(vacc1x67));
128     int32x4_t vacc1x4567 = vcombine_s32(vsum1x45, vsum1x67);
129 #endif
130 
131     const int32x4_t vright_pre_shift = vld1q_dup_s32(&params->rndnu_neon.right_pre_shift);
132     const int32x4_t vmultiplier = vld1q_dup_s32(&params->rndnu_neon.multiplier);
133     const int32x4_t vright_post_shift = vld1q_dup_s32(&params->rndnu_neon.right_post_shift);
134 
135     vacc0x0123 = vqshlq_s32(vacc0x0123, vright_pre_shift);
136     vacc0x4567 = vqshlq_s32(vacc0x4567, vright_pre_shift);
137     vacc1x0123 = vqshlq_s32(vacc1x0123, vright_pre_shift);
138     vacc1x4567 = vqshlq_s32(vacc1x4567, vright_pre_shift);
139 
140     vacc0x0123 = vqdmulhq_s32(vacc0x0123, vmultiplier);
141     vacc0x4567 = vqdmulhq_s32(vacc0x4567, vmultiplier);
142     vacc1x0123 = vqdmulhq_s32(vacc1x0123, vmultiplier);
143     vacc1x4567 = vqdmulhq_s32(vacc1x4567, vmultiplier);
144 
145     vacc0x0123 = vrshlq_s32(vacc0x0123, vright_post_shift);
146     vacc0x4567 = vrshlq_s32(vacc0x4567, vright_post_shift);
147     vacc1x0123 = vrshlq_s32(vacc1x0123, vright_post_shift);
148     vacc1x4567 = vrshlq_s32(vacc1x4567, vright_post_shift);
149 
150     const int16x8_t voutput_zero_point = vld1q_dup_s16(&params->rndnu_neon.output_zero_point);
151 #if XNN_ARCH_ARM64
152     int16x8_t vacc0x01234567 = vqmovn_high_s32(vqmovn_s32(vacc0x0123), vacc0x4567);
153     int16x8_t vacc1x01234567 = vqmovn_high_s32(vqmovn_s32(vacc1x0123), vacc1x4567);
154 
155     vacc0x01234567 = vqaddq_s16(vacc0x01234567, voutput_zero_point);
156     vacc1x01234567 = vqaddq_s16(vacc1x01234567, voutput_zero_point);
157 
158     int8x16_t vout0x01234567_1x01234567 = vqmovn_high_s16(vqmovn_s16(vacc0x01234567), vacc1x01234567);
159 #else
160     int16x8_t vacc0x01234567 = vcombine_s16(vqmovn_s32(vacc0x0123), vqmovn_s32(vacc0x4567));
161     int16x8_t vacc1x01234567 = vcombine_s16(vqmovn_s32(vacc1x0123), vqmovn_s32(vacc1x4567));
162 
163     vacc0x01234567 = vqaddq_s16(vacc0x01234567, voutput_zero_point);
164     vacc1x01234567 = vqaddq_s16(vacc1x01234567, voutput_zero_point);
165 
166     int8x16_t vout0x01234567_1x01234567 = vcombine_s8(vqmovn_s16(vacc0x01234567), vqmovn_s16(vacc1x01234567));
167 #endif
168 
169     const int8x16_t voutput_min = vld1q_dup_s8(&params->rndnu_neon.output_min);
170     vout0x01234567_1x01234567 = vmaxq_s8(vout0x01234567_1x01234567, voutput_min);
171 
172     const int8x16_t voutput_max = vld1q_dup_s8(&params->rndnu_neon.output_max);
173     vout0x01234567_1x01234567 = vminq_s8(vout0x01234567_1x01234567, voutput_max);
174 
175     if (nc >= 8) {
176       vst1_s8(c0 + 0, vget_low_s8(vout0x01234567_1x01234567));
177       vst1_s8(c1 + 0, vget_high_s8(vout0x01234567_1x01234567));
178 
179       c0 = (int8_t*) ((uintptr_t) c0 + cn_stride);
180       c1 = (int8_t*) ((uintptr_t) c1 + cn_stride);
181 
182       a0 = (const int8_t*) ((uintptr_t) a0 - kc);
183       a1 = (const int8_t*) ((uintptr_t) a1 - kc);
184 
185       nc -= 8;
186     } else {
187       // Final case where not all of the 8 columns fit in the destination.
188       if (nc & 4) {
189         vst1q_lane_u32((void*) c0, vreinterpretq_u32_s8(vout0x01234567_1x01234567), 0); c0 += 4;
190         vst1q_lane_u32((void*) c1, vreinterpretq_u32_s8(vout0x01234567_1x01234567), 2); c1 += 4;
191         vout0x01234567_1x01234567 = vextq_s8(vout0x01234567_1x01234567, vout0x01234567_1x01234567, 4);
192       }
193       if (nc & 2) {
194         vst1q_lane_u16((void*) c0, vreinterpretq_u16_s8(vout0x01234567_1x01234567), 0); c0 += 2;
195         vst1q_lane_u16((void*) c1, vreinterpretq_u16_s8(vout0x01234567_1x01234567), 4); c1 += 2;
196         vout0x01234567_1x01234567 = vextq_s8(vout0x01234567_1x01234567, vout0x01234567_1x01234567, 2);
197       }
198       if (nc & 1) {
199         vst1q_lane_s8(c0, vout0x01234567_1x01234567, 0);
200         vst1q_lane_s8(c1, vout0x01234567_1x01234567, 8);
201       }
202 
203       nc = 0;
204     }
205   } while (nc != 0);
206 }
207