1 // Auto-generated file. Do not edit!
2 // Template: src/qs8-igemm/c4-neon-mull-shuffle.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2021 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <arm_neon.h>
13
14 #include <xnnpack/gemm.h>
15 #include <xnnpack/math.h>
16
17
xnn_qs8_igemm_minmax_rndnu_ukernel_2x8c4s2__neon_mull(size_t mr,size_t nc,size_t kc,size_t ks,const int8_t ** restrict a,const void * restrict w,int8_t * restrict c,size_t cm_stride,size_t cn_stride,size_t a_offset,const int8_t * zero,const union xnn_qs8_conv_minmax_params params[restrict XNN_MIN_ELEMENTS (1)])18 void xnn_qs8_igemm_minmax_rndnu_ukernel_2x8c4s2__neon_mull(
19 size_t mr,
20 size_t nc,
21 size_t kc,
22 size_t ks,
23 const int8_t** restrict a,
24 const void* restrict w,
25 int8_t* restrict c,
26 size_t cm_stride,
27 size_t cn_stride,
28 size_t a_offset,
29 const int8_t* zero,
30 const union xnn_qs8_conv_minmax_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
31 {
32 assert(mr != 0);
33 assert(mr <= 2);
34 assert(nc != 0);
35 assert(kc != 0);
36 assert(ks != 0);
37 assert(ks % (2 * sizeof(void*)) == 0);
38 assert(a_offset % sizeof(int8_t) == 0);
39 assert(a != NULL);
40 assert(w != NULL);
41 assert(c != NULL);
42
43 int8_t* c0 = c;
44 int8_t* c1 = (int8_t*) ((uintptr_t) c0 + cm_stride);
45 if XNN_UNPREDICTABLE(mr != 2) {
46 c1 = c0;
47 }
48
49 kc = round_up_po2(kc, 8 * sizeof(int8_t));
50 do {
51 int32x4_t vacc0x01 = vreinterpretq_s32_u64(vmovl_u32(vld1_u32(w))); w = (const int32_t*) w + 2;
52 int32x4_t vacc0x23 = vreinterpretq_s32_u64(vmovl_u32(vld1_u32(w))); w = (const int32_t*) w + 2;
53 int32x4_t vacc0x45 = vreinterpretq_s32_u64(vmovl_u32(vld1_u32(w))); w = (const int32_t*) w + 2;
54 int32x4_t vacc0x67 = vreinterpretq_s32_u64(vmovl_u32(vld1_u32(w))); w = (const int32_t*) w + 2;
55 int32x4_t vacc1x01 = vacc0x01;
56 int32x4_t vacc1x23 = vacc0x23;
57 int32x4_t vacc1x45 = vacc0x45;
58 int32x4_t vacc1x67 = vacc0x67;
59
60 size_t p = ks;
61 do {
62 const int8_t* restrict a0 = a[0];
63 if XNN_UNPREDICTABLE(a0 != zero) {
64 a0 = (const int8_t*) ((uintptr_t) a0 + a_offset);
65 }
66 const int8_t* restrict a1 = a[1];
67 if XNN_UNPREDICTABLE(a1 != zero) {
68 a1 = (const int8_t*) ((uintptr_t) a1 + a_offset);
69 }
70 a += 2;
71
72 size_t k = kc;
73 do {
74 int8x8_t va0x0 = vld1_s8(a0); a0 += 8;
75 int8x8_t va1x0 = vld1_s8(a1); a1 += 8;
76
77 const int8x8_t vb01c0x0 = vld1_s8(w); w = (const int8_t*) w + 8;
78 const int8x8_t vb23c0x0 = vld1_s8(w); w = (const int8_t*) w + 8;
79 const int8x8_t vb45c0x0 = vld1_s8(w); w = (const int8_t*) w + 8;
80 const int8x8_t vb67c0x0 = vld1_s8(w); w = (const int8_t*) w + 8;
81 const int8x8_t vb01c1x0 = vld1_s8(w); w = (const int8_t*) w + 8;
82 const int8x8_t vb23c1x0 = vld1_s8(w); w = (const int8_t*) w + 8;
83 const int8x8_t vb45c1x0 = vld1_s8(w); w = (const int8_t*) w + 8;
84 const int8x8_t vb67c1x0 = vld1_s8(w); w = (const int8_t*) w + 8;
85
86 int16x8_t vprod0x01c0 = vmull_s8(vb01c0x0, va0x0);
87 int16x8_t vprod1x01c0 = vmull_s8(vb01c0x0, va1x0);
88 vacc0x01 = vpadalq_s16(vacc0x01, vprod0x01c0);
89 vacc1x01 = vpadalq_s16(vacc1x01, vprod1x01c0);
90 int16x8_t vprod0x23c0 = vmull_s8(vb23c0x0, va0x0);
91 int16x8_t vprod1x23c0 = vmull_s8(vb23c0x0, va1x0);
92 vacc0x23 = vpadalq_s16(vacc0x23, vprod0x23c0);
93 vacc1x23 = vpadalq_s16(vacc1x23, vprod1x23c0);
94 int16x8_t vprod0x45c0 = vmull_s8(vb45c0x0, va0x0);
95 int16x8_t vprod1x45c0 = vmull_s8(vb45c0x0, va1x0);
96 vacc0x45 = vpadalq_s16(vacc0x45, vprod0x45c0);
97 vacc1x45 = vpadalq_s16(vacc1x45, vprod1x45c0);
98 int16x8_t vprod0x67c0 = vmull_s8(vb67c0x0, va0x0);
99 int16x8_t vprod1x67c0 = vmull_s8(vb67c0x0, va1x0);
100 vacc0x67 = vpadalq_s16(vacc0x67, vprod0x67c0);
101 vacc1x67 = vpadalq_s16(vacc1x67, vprod1x67c0);
102 va0x0 = vext_s8(va0x0, va0x0, 4);
103 va1x0 = vext_s8(va1x0, va1x0, 4);
104 int16x8_t vprod0x01c1 = vmull_s8(vb01c1x0, va0x0);
105 int16x8_t vprod1x01c1 = vmull_s8(vb01c1x0, va1x0);
106 vacc0x01 = vpadalq_s16(vacc0x01, vprod0x01c1);
107 vacc1x01 = vpadalq_s16(vacc1x01, vprod1x01c1);
108 int16x8_t vprod0x23c1 = vmull_s8(vb23c1x0, va0x0);
109 int16x8_t vprod1x23c1 = vmull_s8(vb23c1x0, va1x0);
110 vacc0x23 = vpadalq_s16(vacc0x23, vprod0x23c1);
111 vacc1x23 = vpadalq_s16(vacc1x23, vprod1x23c1);
112 int16x8_t vprod0x45c1 = vmull_s8(vb45c1x0, va0x0);
113 int16x8_t vprod1x45c1 = vmull_s8(vb45c1x0, va1x0);
114 vacc0x45 = vpadalq_s16(vacc0x45, vprod0x45c1);
115 vacc1x45 = vpadalq_s16(vacc1x45, vprod1x45c1);
116 int16x8_t vprod0x67c1 = vmull_s8(vb67c1x0, va0x0);
117 int16x8_t vprod1x67c1 = vmull_s8(vb67c1x0, va1x0);
118 vacc0x67 = vpadalq_s16(vacc0x67, vprod0x67c1);
119 vacc1x67 = vpadalq_s16(vacc1x67, vprod1x67c1);
120
121 k -= 8 * sizeof(int8_t);
122 } while (k != 0);
123
124 p -= 2 * sizeof(void*);
125 } while (p != 0);
126
127 #if XNN_ARCH_ARM64
128 int32x4_t vacc0x0123 = vpaddq_s32(vacc0x01, vacc0x23);
129 int32x4_t vacc0x4567 = vpaddq_s32(vacc0x45, vacc0x67);
130 int32x4_t vacc1x0123 = vpaddq_s32(vacc1x01, vacc1x23);
131 int32x4_t vacc1x4567 = vpaddq_s32(vacc1x45, vacc1x67);
132 #else
133 const int32x2_t vsum0x01 = vpadd_s32(vget_low_s32(vacc0x01), vget_high_s32(vacc0x01));
134 const int32x2_t vsum0x23 = vpadd_s32(vget_low_s32(vacc0x23), vget_high_s32(vacc0x23));
135 int32x4_t vacc0x0123 = vcombine_s32(vsum0x01, vsum0x23);
136 const int32x2_t vsum0x45 = vpadd_s32(vget_low_s32(vacc0x45), vget_high_s32(vacc0x45));
137 const int32x2_t vsum0x67 = vpadd_s32(vget_low_s32(vacc0x67), vget_high_s32(vacc0x67));
138 int32x4_t vacc0x4567 = vcombine_s32(vsum0x45, vsum0x67);
139 const int32x2_t vsum1x01 = vpadd_s32(vget_low_s32(vacc1x01), vget_high_s32(vacc1x01));
140 const int32x2_t vsum1x23 = vpadd_s32(vget_low_s32(vacc1x23), vget_high_s32(vacc1x23));
141 int32x4_t vacc1x0123 = vcombine_s32(vsum1x01, vsum1x23);
142 const int32x2_t vsum1x45 = vpadd_s32(vget_low_s32(vacc1x45), vget_high_s32(vacc1x45));
143 const int32x2_t vsum1x67 = vpadd_s32(vget_low_s32(vacc1x67), vget_high_s32(vacc1x67));
144 int32x4_t vacc1x4567 = vcombine_s32(vsum1x45, vsum1x67);
145 #endif
146
147 const int32x4_t vright_pre_shift = vld1q_dup_s32(¶ms->rndnu_neon.right_pre_shift);
148 const int32x4_t vmultiplier = vld1q_dup_s32(¶ms->rndnu_neon.multiplier);
149 const int32x4_t vright_post_shift = vld1q_dup_s32(¶ms->rndnu_neon.right_post_shift);
150
151 vacc0x0123 = vqshlq_s32(vacc0x0123, vright_pre_shift);
152 vacc0x4567 = vqshlq_s32(vacc0x4567, vright_pre_shift);
153 vacc1x0123 = vqshlq_s32(vacc1x0123, vright_pre_shift);
154 vacc1x4567 = vqshlq_s32(vacc1x4567, vright_pre_shift);
155
156 vacc0x0123 = vqdmulhq_s32(vacc0x0123, vmultiplier);
157 vacc0x4567 = vqdmulhq_s32(vacc0x4567, vmultiplier);
158 vacc1x0123 = vqdmulhq_s32(vacc1x0123, vmultiplier);
159 vacc1x4567 = vqdmulhq_s32(vacc1x4567, vmultiplier);
160
161 vacc0x0123 = vrshlq_s32(vacc0x0123, vright_post_shift);
162 vacc0x4567 = vrshlq_s32(vacc0x4567, vright_post_shift);
163 vacc1x0123 = vrshlq_s32(vacc1x0123, vright_post_shift);
164 vacc1x4567 = vrshlq_s32(vacc1x4567, vright_post_shift);
165
166 const int16x8_t voutput_zero_point = vld1q_dup_s16(¶ms->rndnu_neon.output_zero_point);
167 #if XNN_ARCH_ARM64
168 int16x8_t vacc0x01234567 = vqmovn_high_s32(vqmovn_s32(vacc0x0123), vacc0x4567);
169 int16x8_t vacc1x01234567 = vqmovn_high_s32(vqmovn_s32(vacc1x0123), vacc1x4567);
170
171 vacc0x01234567 = vqaddq_s16(vacc0x01234567, voutput_zero_point);
172 vacc1x01234567 = vqaddq_s16(vacc1x01234567, voutput_zero_point);
173
174 int8x16_t vout0x01234567_1x01234567 = vqmovn_high_s16(vqmovn_s16(vacc0x01234567), vacc1x01234567);
175 #else
176 int16x8_t vacc0x01234567 = vcombine_s16(vqmovn_s32(vacc0x0123), vqmovn_s32(vacc0x4567));
177 int16x8_t vacc1x01234567 = vcombine_s16(vqmovn_s32(vacc1x0123), vqmovn_s32(vacc1x4567));
178
179 vacc0x01234567 = vqaddq_s16(vacc0x01234567, voutput_zero_point);
180 vacc1x01234567 = vqaddq_s16(vacc1x01234567, voutput_zero_point);
181
182 int8x16_t vout0x01234567_1x01234567 = vcombine_s8(vqmovn_s16(vacc0x01234567), vqmovn_s16(vacc1x01234567));
183 #endif
184
185 const int8x16_t voutput_min = vld1q_dup_s8(¶ms->rndnu_neon.output_min);
186 vout0x01234567_1x01234567 = vmaxq_s8(vout0x01234567_1x01234567, voutput_min);
187
188 const int8x16_t voutput_max = vld1q_dup_s8(¶ms->rndnu_neon.output_max);
189 vout0x01234567_1x01234567 = vminq_s8(vout0x01234567_1x01234567, voutput_max);
190
191 if (nc >= 8) {
192 vst1_s8(c1 + 0, vget_high_s8(vout0x01234567_1x01234567));
193 vst1_s8(c0 + 0, vget_low_s8(vout0x01234567_1x01234567));
194
195 c1 = (int8_t*) ((uintptr_t) c1 + cn_stride);
196 c0 = (int8_t*) ((uintptr_t) c0 + cn_stride);
197
198 a = (const int8_t**restrict) ((uintptr_t) a - ks);
199
200 nc -= 8;
201 } else {
202 if (nc & 4) {
203 vst1q_lane_u32((void*) c1, vreinterpretq_u32_s8(vout0x01234567_1x01234567), 2); c1 += 4;
204 vst1q_lane_u32((void*) c0, vreinterpretq_u32_s8(vout0x01234567_1x01234567), 0); c0 += 4;
205 vout0x01234567_1x01234567 = vextq_s8(vout0x01234567_1x01234567, vout0x01234567_1x01234567, 4);
206 }
207 if (nc & 2) {
208 vst1q_lane_u16((void*) c1, vreinterpretq_u16_s8(vout0x01234567_1x01234567), 4); c1 += 2;
209 vst1q_lane_u16((void*) c0, vreinterpretq_u16_s8(vout0x01234567_1x01234567), 0); c0 += 2;
210 vout0x01234567_1x01234567 = vextq_s8(vout0x01234567_1x01234567, vout0x01234567_1x01234567, 2);
211 }
212 if (nc & 1) {
213 vst1q_lane_s8(c1, vout0x01234567_1x01234567, 8);
214 vst1q_lane_s8(c0, vout0x01234567_1x01234567, 0);
215 }
216
217 nc = 0;
218 }
219 } while (nc != 0);
220 }
221