1 /*
2 * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h> /* for uint32_t */
8 #include <lib/mmio.h>
9 #include "pfc_init_e3.h"
10 #include "rcar_def.h"
11 #include "../pfc_regs.h"
12
13 /* PFC */
14 #define GPSR0_SDA4 BIT(17)
15 #define GPSR0_SCL4 BIT(16)
16 #define GPSR0_D15 BIT(15)
17 #define GPSR0_D14 BIT(14)
18 #define GPSR0_D13 BIT(13)
19 #define GPSR0_D12 BIT(12)
20 #define GPSR0_D11 BIT(11)
21 #define GPSR0_D10 BIT(10)
22 #define GPSR0_D9 BIT(9)
23 #define GPSR0_D8 BIT(8)
24 #define GPSR0_D7 BIT(7)
25 #define GPSR0_D6 BIT(6)
26 #define GPSR0_D5 BIT(5)
27 #define GPSR0_D4 BIT(4)
28 #define GPSR0_D3 BIT(3)
29 #define GPSR0_D2 BIT(2)
30 #define GPSR0_D1 BIT(1)
31 #define GPSR0_D0 BIT(0)
32 #define GPSR1_WE0 BIT(22)
33 #define GPSR1_CS0 BIT(21)
34 #define GPSR1_CLKOUT BIT(20)
35 #define GPSR1_A19 BIT(19)
36 #define GPSR1_A18 BIT(18)
37 #define GPSR1_A17 BIT(17)
38 #define GPSR1_A16 BIT(16)
39 #define GPSR1_A15 BIT(15)
40 #define GPSR1_A14 BIT(14)
41 #define GPSR1_A13 BIT(13)
42 #define GPSR1_A12 BIT(12)
43 #define GPSR1_A11 BIT(11)
44 #define GPSR1_A10 BIT(10)
45 #define GPSR1_A9 BIT(9)
46 #define GPSR1_A8 BIT(8)
47 #define GPSR1_A7 BIT(7)
48 #define GPSR1_A6 BIT(6)
49 #define GPSR1_A5 BIT(5)
50 #define GPSR1_A4 BIT(4)
51 #define GPSR1_A3 BIT(3)
52 #define GPSR1_A2 BIT(2)
53 #define GPSR1_A1 BIT(1)
54 #define GPSR1_A0 BIT(0)
55 #define GPSR2_BIT27_REVERSED BIT(27)
56 #define GPSR2_BIT26_REVERSED BIT(26)
57 #define GPSR2_EX_WAIT0 BIT(25)
58 #define GPSR2_RD_WR BIT(24)
59 #define GPSR2_RD BIT(23)
60 #define GPSR2_BS BIT(22)
61 #define GPSR2_AVB_PHY_INT BIT(21)
62 #define GPSR2_AVB_TXCREFCLK BIT(20)
63 #define GPSR2_AVB_RD3 BIT(19)
64 #define GPSR2_AVB_RD2 BIT(18)
65 #define GPSR2_AVB_RD1 BIT(17)
66 #define GPSR2_AVB_RD0 BIT(16)
67 #define GPSR2_AVB_RXC BIT(15)
68 #define GPSR2_AVB_RX_CTL BIT(14)
69 #define GPSR2_RPC_RESET BIT(13)
70 #define GPSR2_RPC_RPC_INT BIT(12)
71 #define GPSR2_QSPI1_SSL BIT(11)
72 #define GPSR2_QSPI1_IO3 BIT(10)
73 #define GPSR2_QSPI1_IO2 BIT(9)
74 #define GPSR2_QSPI1_MISO_IO1 BIT(8)
75 #define GPSR2_QSPI1_MOSI_IO0 BIT(7)
76 #define GPSR2_QSPI1_SPCLK BIT(6)
77 #define GPSR2_QSPI0_SSL BIT(5)
78 #define GPSR2_QSPI0_IO3 BIT(4)
79 #define GPSR2_QSPI0_IO2 BIT(3)
80 #define GPSR2_QSPI0_MISO_IO1 BIT(2)
81 #define GPSR2_QSPI0_MOSI_IO0 BIT(1)
82 #define GPSR2_QSPI0_SPCLK BIT(0)
83 #define GPSR3_SD1_WP BIT(15)
84 #define GPSR3_SD1_CD BIT(14)
85 #define GPSR3_SD0_WP BIT(13)
86 #define GPSR3_SD0_CD BIT(12)
87 #define GPSR3_SD1_DAT3 BIT(11)
88 #define GPSR3_SD1_DAT2 BIT(10)
89 #define GPSR3_SD1_DAT1 BIT(9)
90 #define GPSR3_SD1_DAT0 BIT(8)
91 #define GPSR3_SD1_CMD BIT(7)
92 #define GPSR3_SD1_CLK BIT(6)
93 #define GPSR3_SD0_DAT3 BIT(5)
94 #define GPSR3_SD0_DAT2 BIT(4)
95 #define GPSR3_SD0_DAT1 BIT(3)
96 #define GPSR3_SD0_DAT0 BIT(2)
97 #define GPSR3_SD0_CMD BIT(1)
98 #define GPSR3_SD0_CLK BIT(0)
99 #define GPSR4_SD3_DS BIT(10)
100 #define GPSR4_SD3_DAT7 BIT(9)
101 #define GPSR4_SD3_DAT6 BIT(8)
102 #define GPSR4_SD3_DAT5 BIT(7)
103 #define GPSR4_SD3_DAT4 BIT(6)
104 #define GPSR4_SD3_DAT3 BIT(5)
105 #define GPSR4_SD3_DAT2 BIT(4)
106 #define GPSR4_SD3_DAT1 BIT(3)
107 #define GPSR4_SD3_DAT0 BIT(2)
108 #define GPSR4_SD3_CMD BIT(1)
109 #define GPSR4_SD3_CLK BIT(0)
110 #define GPSR5_MLB_DAT BIT(19)
111 #define GPSR5_MLB_SIG BIT(18)
112 #define GPSR5_MLB_CLK BIT(17)
113 #define GPSR5_SSI_SDATA9 BIT(16)
114 #define GPSR5_MSIOF0_SS2 BIT(15)
115 #define GPSR5_MSIOF0_SS1 BIT(14)
116 #define GPSR5_MSIOF0_SYNC BIT(13)
117 #define GPSR5_MSIOF0_TXD BIT(12)
118 #define GPSR5_MSIOF0_RXD BIT(11)
119 #define GPSR5_MSIOF0_SCK BIT(10)
120 #define GPSR5_RX2_A BIT(9)
121 #define GPSR5_TX2_A BIT(8)
122 #define GPSR5_SCK2_A BIT(7)
123 #define GPSR5_TX1 BIT(6)
124 #define GPSR5_RX1 BIT(5)
125 #define GPSR5_RTS0_A BIT(4)
126 #define GPSR5_CTS0_A BIT(3)
127 #define GPSR5_TX0_A BIT(2)
128 #define GPSR5_RX0_A BIT(1)
129 #define GPSR5_SCK0_A BIT(0)
130 #define GPSR6_USB30_PWEN BIT(17)
131 #define GPSR6_SSI_SDATA6 BIT(16)
132 #define GPSR6_SSI_WS6 BIT(15)
133 #define GPSR6_SSI_SCK6 BIT(14)
134 #define GPSR6_SSI_SDATA5 BIT(13)
135 #define GPSR6_SSI_WS5 BIT(12)
136 #define GPSR6_SSI_SCK5 BIT(11)
137 #define GPSR6_SSI_SDATA4 BIT(10)
138 #define GPSR6_USB30_OVC BIT(9)
139 #define GPSR6_AUDIO_CLKA BIT(8)
140 #define GPSR6_SSI_SDATA3 BIT(7)
141 #define GPSR6_SSI_WS349 BIT(6)
142 #define GPSR6_SSI_SCK349 BIT(5)
143 #define GPSR6_SSI_SDATA2 BIT(4)
144 #define GPSR6_SSI_SDATA1 BIT(3)
145 #define GPSR6_SSI_SDATA0 BIT(2)
146 #define GPSR6_SSI_WS01239 BIT(1)
147 #define GPSR6_SSI_SCK01239 BIT(0)
148
149 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
150 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
151 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
152 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
153 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
154 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
155 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
156 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
157
158 #define POCCTRL0_MASK (0x0007F000U)
159 #define POC_SD3_DS_33V BIT(29)
160 #define POC_SD3_DAT7_33V BIT(28)
161 #define POC_SD3_DAT6_33V BIT(27)
162 #define POC_SD3_DAT5_33V BIT(26)
163 #define POC_SD3_DAT4_33V BIT(25)
164 #define POC_SD3_DAT3_33V BIT(24)
165 #define POC_SD3_DAT2_33V BIT(23)
166 #define POC_SD3_DAT1_33V BIT(22)
167 #define POC_SD3_DAT0_33V BIT(21)
168 #define POC_SD3_CMD_33V BIT(20)
169 #define POC_SD3_CLK_33V BIT(19)
170 #define POC_SD1_DAT3_33V BIT(11)
171 #define POC_SD1_DAT2_33V BIT(10)
172 #define POC_SD1_DAT1_33V BIT(9)
173 #define POC_SD1_DAT0_33V BIT(8)
174 #define POC_SD1_CMD_33V BIT(7)
175 #define POC_SD1_CLK_33V BIT(6)
176 #define POC_SD0_DAT3_33V BIT(5)
177 #define POC_SD0_DAT2_33V BIT(4)
178 #define POC_SD0_DAT1_33V BIT(3)
179 #define POC_SD0_DAT0_33V BIT(2)
180 #define POC_SD0_CMD_33V BIT(1)
181 #define POC_SD0_CLK_33V BIT(0)
182
183 #define POCCTRL2_MASK (0xFFFFFFFEU)
184 #define POC2_VREF_33V BIT(0)
185
186 #define MOD_SEL0_ADGB_A ((uint32_t)0U << 29U)
187 #define MOD_SEL0_ADGB_B ((uint32_t)1U << 29U)
188 #define MOD_SEL0_ADGB_C ((uint32_t)2U << 29U)
189 #define MOD_SEL0_DRIF0_A ((uint32_t)0U << 28U)
190 #define MOD_SEL0_DRIF0_B ((uint32_t)1U << 28U)
191 #define MOD_SEL0_FM_A ((uint32_t)0U << 26U)
192 #define MOD_SEL0_FM_B ((uint32_t)1U << 26U)
193 #define MOD_SEL0_FM_C ((uint32_t)2U << 26U)
194 #define MOD_SEL0_FSO_A ((uint32_t)0U << 25U)
195 #define MOD_SEL0_FSO_B ((uint32_t)1U << 25U)
196 #define MOD_SEL0_HSCIF0_A ((uint32_t)0U << 24U)
197 #define MOD_SEL0_HSCIF0_B ((uint32_t)1U << 24U)
198 #define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 23U)
199 #define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 23U)
200 #define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 22U)
201 #define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 22U)
202 #define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
203 #define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
204 #define MOD_SEL0_I2C1_C ((uint32_t)2U << 20U)
205 #define MOD_SEL0_I2C1_D ((uint32_t)3U << 20U)
206 #define MOD_SEL0_I2C2_A ((uint32_t)0U << 17U)
207 #define MOD_SEL0_I2C2_B ((uint32_t)1U << 17U)
208 #define MOD_SEL0_I2C2_C ((uint32_t)2U << 17U)
209 #define MOD_SEL0_I2C2_D ((uint32_t)3U << 17U)
210 #define MOD_SEL0_I2C2_E ((uint32_t)4U << 17U)
211 #define MOD_SEL0_NDFC_A ((uint32_t)0U << 16U)
212 #define MOD_SEL0_NDFC_B ((uint32_t)1U << 16U)
213 #define MOD_SEL0_PWM0_A ((uint32_t)0U << 15U)
214 #define MOD_SEL0_PWM0_B ((uint32_t)1U << 15U)
215 #define MOD_SEL0_PWM1_A ((uint32_t)0U << 14U)
216 #define MOD_SEL0_PWM1_B ((uint32_t)1U << 14U)
217 #define MOD_SEL0_PWM2_A ((uint32_t)0U << 12U)
218 #define MOD_SEL0_PWM2_B ((uint32_t)1U << 12U)
219 #define MOD_SEL0_PWM2_C ((uint32_t)2U << 12U)
220 #define MOD_SEL0_PWM3_A ((uint32_t)0U << 10U)
221 #define MOD_SEL0_PWM3_B ((uint32_t)1U << 10U)
222 #define MOD_SEL0_PWM3_C ((uint32_t)2U << 10U)
223 #define MOD_SEL0_PWM4_A ((uint32_t)0U << 9U)
224 #define MOD_SEL0_PWM4_B ((uint32_t)1U << 9U)
225 #define MOD_SEL0_PWM5_A ((uint32_t)0U << 8U)
226 #define MOD_SEL0_PWM5_B ((uint32_t)1U << 8U)
227 #define MOD_SEL0_PWM6_A ((uint32_t)0U << 7U)
228 #define MOD_SEL0_PWM6_B ((uint32_t)1U << 7U)
229 #define MOD_SEL0_REMOCON_A ((uint32_t)0U << 5U)
230 #define MOD_SEL0_REMOCON_B ((uint32_t)1U << 5U)
231 #define MOD_SEL0_REMOCON_C ((uint32_t)2U << 5U)
232 #define MOD_SEL0_SCIF_A ((uint32_t)0U << 4U)
233 #define MOD_SEL0_SCIF_B ((uint32_t)1U << 4U)
234 #define MOD_SEL0_SCIF0_A ((uint32_t)0U << 3U)
235 #define MOD_SEL0_SCIF0_B ((uint32_t)1U << 3U)
236 #define MOD_SEL0_SCIF2_A ((uint32_t)0U << 2U)
237 #define MOD_SEL0_SCIF2_B ((uint32_t)1U << 2U)
238 #define MOD_SEL0_SPEED_PULSE_IF_A ((uint32_t)0U << 0U)
239 #define MOD_SEL0_SPEED_PULSE_IF_B ((uint32_t)1U << 0U)
240 #define MOD_SEL0_SPEED_PULSE_IF_C ((uint32_t)2U << 0U)
241 #define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 31U)
242 #define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 31U)
243 #define MOD_SEL1_SSI2_A ((uint32_t)0U << 30U)
244 #define MOD_SEL1_SSI2_B ((uint32_t)1U << 30U)
245 #define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 29U)
246 #define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 29U)
247 #define MOD_SEL1_USB20_CH0_A ((uint32_t)0U << 28U)
248 #define MOD_SEL1_USB20_CH0_B ((uint32_t)1U << 28U)
249 #define MOD_SEL1_DRIF2_A ((uint32_t)0U << 26U)
250 #define MOD_SEL1_DRIF2_B ((uint32_t)1U << 26U)
251 #define MOD_SEL1_DRIF3_A ((uint32_t)0U << 25U)
252 #define MOD_SEL1_DRIF3_B ((uint32_t)1U << 25U)
253 #define MOD_SEL1_HSCIF3_A ((uint32_t)0U << 22U)
254 #define MOD_SEL1_HSCIF3_B ((uint32_t)1U << 22U)
255 #define MOD_SEL1_HSCIF3_C ((uint32_t)2U << 22U)
256 #define MOD_SEL1_HSCIF3_D ((uint32_t)3U << 22U)
257 #define MOD_SEL1_HSCIF3_E ((uint32_t)4U << 22U)
258 #define MOD_SEL1_HSCIF4_A ((uint32_t)0U << 19U)
259 #define MOD_SEL1_HSCIF4_B ((uint32_t)1U << 19U)
260 #define MOD_SEL1_HSCIF4_C ((uint32_t)2U << 19U)
261 #define MOD_SEL1_HSCIF4_D ((uint32_t)3U << 19U)
262 #define MOD_SEL1_HSCIF4_E ((uint32_t)4U << 19U)
263 #define MOD_SEL1_I2C6_A ((uint32_t)0U << 18U)
264 #define MOD_SEL1_I2C6_B ((uint32_t)1U << 18U)
265 #define MOD_SEL1_I2C7_A ((uint32_t)0U << 17U)
266 #define MOD_SEL1_I2C7_B ((uint32_t)1U << 17U)
267 #define MOD_SEL1_MSIOF2_A ((uint32_t)0U << 16U)
268 #define MOD_SEL1_MSIOF2_B ((uint32_t)1U << 16U)
269 #define MOD_SEL1_MSIOF3_A ((uint32_t)0U << 15U)
270 #define MOD_SEL1_MSIOF3_B ((uint32_t)1U << 15U)
271 #define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
272 #define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
273 #define MOD_SEL1_SCIF3_C ((uint32_t)2U << 13U)
274 #define MOD_SEL1_SCIF4_A ((uint32_t)0U << 11U)
275 #define MOD_SEL1_SCIF4_B ((uint32_t)1U << 11U)
276 #define MOD_SEL1_SCIF4_C ((uint32_t)2U << 11U)
277 #define MOD_SEL1_SCIF5_A ((uint32_t)0U << 9U)
278 #define MOD_SEL1_SCIF5_B ((uint32_t)1U << 9U)
279 #define MOD_SEL1_SCIF5_C ((uint32_t)2U << 9U)
280 #define MOD_SEL1_VIN4_A ((uint32_t)0U << 8U)
281 #define MOD_SEL1_VIN4_B ((uint32_t)1U << 8U)
282 #define MOD_SEL1_VIN5_A ((uint32_t)0U << 7U)
283 #define MOD_SEL1_VIN5_B ((uint32_t)1U << 7U)
284 #define MOD_SEL1_ADGC_A ((uint32_t)0U << 5U)
285 #define MOD_SEL1_ADGC_B ((uint32_t)1U << 5U)
286 #define MOD_SEL1_ADGC_C ((uint32_t)2U << 5U)
287 #define MOD_SEL1_SSI9_A ((uint32_t)0U << 4U)
288 #define MOD_SEL1_SSI9_B ((uint32_t)1U << 4U)
289
pfc_reg_write(uint32_t addr,uint32_t data)290 static void pfc_reg_write(uint32_t addr, uint32_t data)
291 {
292 mmio_write_32(PFC_PMMR, ~data);
293 mmio_write_32((uintptr_t)addr, data);
294 }
295
pfc_init_e3(void)296 void pfc_init_e3(void)
297 {
298 uint32_t reg;
299
300 /* initialize module select */
301 pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_ADGB_A
302 | MOD_SEL0_DRIF0_A
303 | MOD_SEL0_FM_A
304 | MOD_SEL0_FSO_A
305 | MOD_SEL0_HSCIF0_A
306 | MOD_SEL0_HSCIF1_A
307 | MOD_SEL0_HSCIF2_A
308 | MOD_SEL0_I2C1_A
309 | MOD_SEL0_I2C2_A
310 | MOD_SEL0_NDFC_A
311 | MOD_SEL0_PWM0_A
312 | MOD_SEL0_PWM1_A
313 | MOD_SEL0_PWM2_A
314 | MOD_SEL0_PWM3_A
315 | MOD_SEL0_PWM4_A
316 | MOD_SEL0_PWM5_A
317 | MOD_SEL0_PWM6_A
318 | MOD_SEL0_REMOCON_A
319 | MOD_SEL0_SCIF_A
320 | MOD_SEL0_SCIF0_A
321 | MOD_SEL0_SCIF2_A
322 | MOD_SEL0_SPEED_PULSE_IF_A);
323 pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_SIMCARD_A
324 | MOD_SEL1_SSI2_A
325 | MOD_SEL1_TIMER_TMU_A
326 | MOD_SEL1_USB20_CH0_B
327 | MOD_SEL1_DRIF2_A
328 | MOD_SEL1_DRIF3_A
329 | MOD_SEL1_HSCIF3_A
330 | MOD_SEL1_HSCIF4_A
331 | MOD_SEL1_I2C6_A
332 | MOD_SEL1_I2C7_A
333 | MOD_SEL1_MSIOF2_A
334 | MOD_SEL1_MSIOF3_A
335 | MOD_SEL1_SCIF3_A
336 | MOD_SEL1_SCIF4_A
337 | MOD_SEL1_SCIF5_A
338 | MOD_SEL1_VIN4_A
339 | MOD_SEL1_VIN5_A
340 | MOD_SEL1_ADGC_A
341 | MOD_SEL1_SSI9_A);
342
343 /* initialize peripheral function select */
344 pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) /* QSPI1_MISO/IO1 */
345 | IPSR_24_FUNC(0) /* QSPI1_MOSI/IO0 */
346 | IPSR_20_FUNC(0) /* QSPI1_SPCLK */
347 | IPSR_16_FUNC(0) /* QSPI0_IO3 */
348 | IPSR_12_FUNC(0) /* QSPI0_IO2 */
349 | IPSR_8_FUNC(0) /* QSPI0_MISO/IO1 */
350 | IPSR_4_FUNC(0) /* QSPI0_MOSI/IO0 */
351 | IPSR_0_FUNC(0)); /* QSPI0_SPCLK */
352 pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0) /* AVB_RD2 */
353 | IPSR_24_FUNC(0) /* AVB_RD1 */
354 | IPSR_20_FUNC(0) /* AVB_RD0 */
355 | IPSR_16_FUNC(0) /* RPC_RESET# */
356 | IPSR_12_FUNC(0) /* RPC_INT# */
357 | IPSR_8_FUNC(0) /* QSPI1_SSL */
358 | IPSR_4_FUNC(0) /* QSPI1_IO3 */
359 | IPSR_0_FUNC(0)); /* QSPI1_IO2 */
360 pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(1) /* IRQ0 */
361 | IPSR_24_FUNC(0)
362 | IPSR_20_FUNC(0)
363 | IPSR_16_FUNC(2) /* AVB_LINK */
364 | IPSR_12_FUNC(0)
365 | IPSR_8_FUNC(0) /* AVB_MDC */
366 | IPSR_4_FUNC(0) /* AVB_MDIO */
367 | IPSR_0_FUNC(0)); /* AVB_TXCREFCLK */
368 pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(5) /* DU_HSYNC */
369 | IPSR_24_FUNC(0)
370 | IPSR_20_FUNC(0)
371 | IPSR_16_FUNC(0)
372 | IPSR_12_FUNC(5) /* DU_DG4 */
373 | IPSR_8_FUNC(5) /* DU_DOTCLKOUT0 */
374 | IPSR_4_FUNC(5) /* DU_DISP */
375 | IPSR_0_FUNC(1)); /* IRQ1 */
376 pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(5) /* DU_DB5 */
377 | IPSR_24_FUNC(5) /* DU_DB4 */
378 | IPSR_20_FUNC(5) /* DU_DB3 */
379 | IPSR_16_FUNC(5) /* DU_DB2 */
380 | IPSR_12_FUNC(5) /* DU_DG6 */
381 | IPSR_8_FUNC(5) /* DU_VSYNC */
382 | IPSR_4_FUNC(5) /* DU_DG5 */
383 | IPSR_0_FUNC(5)); /* DU_DG7 */
384 pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(5) /* DU_DR3 */
385 | IPSR_24_FUNC(5) /* DU_DB7 */
386 | IPSR_20_FUNC(5) /* DU_DR2 */
387 | IPSR_16_FUNC(5) /* DU_DR1 */
388 | IPSR_12_FUNC(5) /* DU_DR0 */
389 | IPSR_8_FUNC(5) /* DU_DB1 */
390 | IPSR_4_FUNC(5) /* DU_DB0 */
391 | IPSR_0_FUNC(5)); /* DU_DB6 */
392 pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(5) /* DU_DG1 */
393 | IPSR_24_FUNC(5) /* DU_DG0 */
394 | IPSR_20_FUNC(5) /* DU_DR7 */
395 | IPSR_16_FUNC(2) /* IRQ5 */
396 | IPSR_12_FUNC(5) /* DU_DR6 */
397 | IPSR_8_FUNC(5) /* DU_DR5 */
398 | IPSR_4_FUNC(0)
399 | IPSR_0_FUNC(5)); /* DU_DR4 */
400 pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) /* SD0_CLK */
401 | IPSR_24_FUNC(0)
402 | IPSR_20_FUNC(5) /* DU_DOTCLKIN0 */
403 | IPSR_16_FUNC(5) /* DU_DG3 */
404 | IPSR_12_FUNC(0)
405 | IPSR_8_FUNC(0)
406 | IPSR_4_FUNC(0)
407 | IPSR_0_FUNC(5)); /* DU_DG2 */
408 pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0) /* SD1_DAT0 */
409 | IPSR_24_FUNC(0) /* SD1_CMD */
410 | IPSR_20_FUNC(0) /* SD1_CLK */
411 | IPSR_16_FUNC(0) /* SD0_DAT3 */
412 | IPSR_12_FUNC(0) /* SD0_DAT2 */
413 | IPSR_8_FUNC(0) /* SD0_DAT1 */
414 | IPSR_4_FUNC(0) /* SD0_DAT0 */
415 | IPSR_0_FUNC(0)); /* SD0_CMD */
416 pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0) /* SD3_DAT2 */
417 | IPSR_24_FUNC(0) /* SD3_DAT1 */
418 | IPSR_20_FUNC(0) /* SD3_DAT0 */
419 | IPSR_16_FUNC(0) /* SD3_CMD */
420 | IPSR_12_FUNC(0) /* SD3_CLK */
421 | IPSR_8_FUNC(0) /* SD1_DAT3 */
422 | IPSR_4_FUNC(0) /* SD1_DAT2 */
423 | IPSR_0_FUNC(0)); /* SD1_DAT1 */
424 pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0) /* SD0_WP */
425 | IPSR_24_FUNC(0) /* SD0_CD */
426 | IPSR_20_FUNC(0) /* SD3_DS */
427 | IPSR_16_FUNC(0) /* SD3_DAT7 */
428 | IPSR_12_FUNC(0) /* SD3_DAT6 */
429 | IPSR_8_FUNC(0) /* SD3_DAT5 */
430 | IPSR_4_FUNC(0) /* SD3_DAT4 */
431 | IPSR_0_FUNC(0)); /* SD3_DAT3 */
432 pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
433 | IPSR_24_FUNC(0)
434 | IPSR_20_FUNC(2) /* AUDIO_CLKOUT1_A */
435 | IPSR_16_FUNC(2) /* AUDIO_CLKOUT_A */
436 | IPSR_12_FUNC(0)
437 | IPSR_8_FUNC(0)
438 | IPSR_4_FUNC(0) /* SD1_WP */
439 | IPSR_0_FUNC(0)); /* SD1_CD */
440 pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
441 | IPSR_24_FUNC(0)
442 | IPSR_20_FUNC(0)
443 | IPSR_16_FUNC(0)
444 | IPSR_12_FUNC(0) /* RX2_A */
445 | IPSR_8_FUNC(0) /* TX2_A */
446 | IPSR_4_FUNC(2) /* AUDIO_CLKB_A */
447 | IPSR_0_FUNC(0));
448 pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
449 | IPSR_24_FUNC(0)
450 | IPSR_20_FUNC(0)
451 | IPSR_16_FUNC(0)
452 | IPSR_12_FUNC(0)
453 | IPSR_8_FUNC(2) /* AUDIO_CLKC_A */
454 | IPSR_4_FUNC(1) /* HTX2_A */
455 | IPSR_0_FUNC(1)); /* HRX2_A */
456 pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(3) /* USB0_PWEN_B */
457 | IPSR_24_FUNC(0) /* SSI_SDATA4 */
458 | IPSR_20_FUNC(0) /* SSI_SDATA3 */
459 | IPSR_16_FUNC(0) /* SSI_WS349 */
460 | IPSR_12_FUNC(0) /* SSI_SCK349 */
461 | IPSR_8_FUNC(0)
462 | IPSR_4_FUNC(0) /* SSI_SDATA1 */
463 | IPSR_0_FUNC(0)); /* SSI_SDATA0 */
464 pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0) /* USB30_OVC */
465 | IPSR_24_FUNC(0) /* USB30_PWEN */
466 | IPSR_20_FUNC(0) /* AUDIO_CLKA */
467 | IPSR_16_FUNC(1) /* HRTS2#_A */
468 | IPSR_12_FUNC(1) /* HCTS2#_A */
469 | IPSR_8_FUNC(0)
470 | IPSR_4_FUNC(0)
471 | IPSR_0_FUNC(3)); /* USB0_OVC_B */
472
473 /* initialize GPIO/perihperal function select */
474 pfc_reg_write(PFC_GPSR0, GPSR0_SCL4
475 | GPSR0_D15
476 | GPSR0_D11
477 | GPSR0_D10
478 | GPSR0_D9
479 | GPSR0_D8
480 | GPSR0_D7
481 | GPSR0_D6
482 | GPSR0_D5
483 | GPSR0_D3
484 | GPSR0_D2
485 | GPSR0_D1
486 | GPSR0_D0);
487 pfc_reg_write(PFC_GPSR1, GPSR1_WE0
488 | GPSR1_CS0
489 | GPSR1_A19
490 | GPSR1_A18
491 | GPSR1_A17
492 | GPSR1_A16
493 | GPSR1_A15
494 | GPSR1_A14
495 | GPSR1_A13
496 | GPSR1_A12
497 | GPSR1_A11
498 | GPSR1_A10
499 | GPSR1_A9
500 | GPSR1_A8
501 | GPSR1_A4
502 | GPSR1_A3
503 | GPSR1_A2
504 | GPSR1_A1
505 | GPSR1_A0);
506 pfc_reg_write(PFC_GPSR2, GPSR2_BIT27_REVERSED
507 | GPSR2_BIT26_REVERSED
508 | GPSR2_RD
509 | GPSR2_AVB_PHY_INT
510 | GPSR2_AVB_TXCREFCLK
511 | GPSR2_AVB_RD3
512 | GPSR2_AVB_RD2
513 | GPSR2_AVB_RD1
514 | GPSR2_AVB_RD0
515 | GPSR2_AVB_RXC
516 | GPSR2_AVB_RX_CTL
517 | GPSR2_RPC_RESET
518 | GPSR2_RPC_RPC_INT
519 | GPSR2_QSPI1_SSL
520 | GPSR2_QSPI1_IO3
521 | GPSR2_QSPI1_IO2
522 | GPSR2_QSPI1_MISO_IO1
523 | GPSR2_QSPI1_MOSI_IO0
524 | GPSR2_QSPI1_SPCLK
525 | GPSR2_QSPI0_SSL
526 | GPSR2_QSPI0_IO3
527 | GPSR2_QSPI0_IO2
528 | GPSR2_QSPI0_MISO_IO1
529 | GPSR2_QSPI0_MOSI_IO0
530 | GPSR2_QSPI0_SPCLK);
531 pfc_reg_write(PFC_GPSR3, GPSR3_SD1_WP
532 | GPSR3_SD1_CD
533 | GPSR3_SD0_WP
534 | GPSR3_SD0_CD
535 | GPSR3_SD1_DAT3
536 | GPSR3_SD1_DAT2
537 | GPSR3_SD1_DAT1
538 | GPSR3_SD1_DAT0
539 | GPSR3_SD1_CMD
540 | GPSR3_SD1_CLK
541 | GPSR3_SD0_DAT3
542 | GPSR3_SD0_DAT2
543 | GPSR3_SD0_DAT1
544 | GPSR3_SD0_DAT0
545 | GPSR3_SD0_CMD
546 | GPSR3_SD0_CLK);
547 pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DS
548 | GPSR4_SD3_DAT7
549 | GPSR4_SD3_DAT6
550 | GPSR4_SD3_DAT5
551 | GPSR4_SD3_DAT4
552 | GPSR4_SD3_DAT3
553 | GPSR4_SD3_DAT2
554 | GPSR4_SD3_DAT1
555 | GPSR4_SD3_DAT0
556 | GPSR4_SD3_CMD
557 | GPSR4_SD3_CLK);
558 pfc_reg_write(PFC_GPSR5, GPSR5_SSI_SDATA9
559 | GPSR5_MSIOF0_SS2
560 | GPSR5_MSIOF0_SS1
561 | GPSR5_RX2_A
562 | GPSR5_TX2_A
563 | GPSR5_SCK2_A
564 | GPSR5_RTS0_A
565 | GPSR5_CTS0_A);
566 pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
567 | GPSR6_SSI_SDATA6
568 | GPSR6_SSI_WS6
569 | GPSR6_SSI_WS5
570 | GPSR6_SSI_SCK5
571 | GPSR6_SSI_SDATA4
572 | GPSR6_USB30_OVC
573 | GPSR6_AUDIO_CLKA
574 | GPSR6_SSI_SDATA3
575 | GPSR6_SSI_WS349
576 | GPSR6_SSI_SCK349
577 | GPSR6_SSI_SDATA1
578 | GPSR6_SSI_SDATA0
579 | GPSR6_SSI_WS01239
580 | GPSR6_SSI_SCK01239);
581
582 /* initialize POC control */
583 reg = mmio_read_32(PFC_POCCTRL0);
584 reg = ((reg & POCCTRL0_MASK) | POC_SD1_DAT3_33V
585 | POC_SD1_DAT2_33V
586 | POC_SD1_DAT1_33V
587 | POC_SD1_DAT0_33V
588 | POC_SD1_CMD_33V
589 | POC_SD1_CLK_33V
590 | POC_SD0_DAT3_33V
591 | POC_SD0_DAT2_33V
592 | POC_SD0_DAT1_33V
593 | POC_SD0_DAT0_33V
594 | POC_SD0_CMD_33V
595 | POC_SD0_CLK_33V);
596 pfc_reg_write(PFC_POCCTRL0, reg);
597 reg = mmio_read_32(PFC_POCCTRL2);
598 reg = (reg & POCCTRL2_MASK);
599 pfc_reg_write(PFC_POCCTRL2, reg);
600
601 /* initialize LSI pin pull-up/down control */
602 pfc_reg_write(PFC_PUD0, 0xFDF80000U);
603 pfc_reg_write(PFC_PUD1, 0xCE298464U);
604 pfc_reg_write(PFC_PUD2, 0xA4C380F4U);
605 pfc_reg_write(PFC_PUD3, 0x0000079FU);
606 pfc_reg_write(PFC_PUD4, 0xFFF0FFFFU);
607 pfc_reg_write(PFC_PUD5, 0x40000000U);
608
609 /* initialize LSI pin pull-enable register */
610 pfc_reg_write(PFC_PUEN0, 0xFFF00000U);
611 pfc_reg_write(PFC_PUEN1, 0x00000000U);
612 pfc_reg_write(PFC_PUEN2, 0x00000004U);
613 pfc_reg_write(PFC_PUEN3, 0x00000000U);
614 pfc_reg_write(PFC_PUEN4, 0x07800010U);
615 pfc_reg_write(PFC_PUEN5, 0x00000000U);
616
617 /* initialize positive/negative logic select */
618 mmio_write_32(GPIO_POSNEG0, 0x00000000U);
619 mmio_write_32(GPIO_POSNEG1, 0x00000000U);
620 mmio_write_32(GPIO_POSNEG2, 0x00000000U);
621 mmio_write_32(GPIO_POSNEG3, 0x00000000U);
622 mmio_write_32(GPIO_POSNEG4, 0x00000000U);
623 mmio_write_32(GPIO_POSNEG5, 0x00000000U);
624 mmio_write_32(GPIO_POSNEG6, 0x00000000U);
625
626 /* initialize general IO/interrupt switching */
627 mmio_write_32(GPIO_IOINTSEL0, 0x00020000U);
628 mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
629 mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
630 mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
631 mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
632 mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
633 mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
634
635 /* initialize general output register */
636 mmio_write_32(GPIO_OUTDT0, 0x00000010U);
637 mmio_write_32(GPIO_OUTDT1, 0x00100000U);
638 mmio_write_32(GPIO_OUTDT2, 0x00000000U);
639 mmio_write_32(GPIO_OUTDT3, 0x00008000U);
640 mmio_write_32(GPIO_OUTDT5, 0x00060000U);
641 mmio_write_32(GPIO_OUTDT6, 0x00000000U);
642
643 /* initialize general input/output switching */
644 mmio_write_32(GPIO_INOUTSEL0, 0x00000010U);
645 mmio_write_32(GPIO_INOUTSEL1, 0x00100020U);
646 mmio_write_32(GPIO_INOUTSEL2, 0x03000000U);
647 mmio_write_32(GPIO_INOUTSEL3, 0x00008000U);
648 mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
649 mmio_write_32(GPIO_INOUTSEL5, 0x00060000U);
650 mmio_write_32(GPIO_INOUTSEL6, 0x00004000U);
651 }
652