1 /* 2 * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #if TRUSTED_BOARD_BOOT 12 #include <drivers/auth/mbedtls/mbedtls_config.h> 13 #endif 14 #include <plat/arm/board/common/board_css_def.h> 15 #include <plat/arm/board/common/v2m_def.h> 16 #include <plat/arm/common/arm_def.h> 17 #include <plat/arm/css/common/css_def.h> 18 #include <plat/arm/soc/common/soc_css_def.h> 19 #include <plat/common/common_def.h> 20 21 #include "../juno_def.h" 22 23 /* Required platform porting definitions */ 24 /* Juno supports system power domain */ 25 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 26 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 27 JUNO_CLUSTER_COUNT + \ 28 PLATFORM_CORE_COUNT) 29 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 30 JUNO_CLUSTER1_CORE_COUNT) 31 32 /* Cryptocell HW Base address */ 33 #define PLAT_CRYPTOCELL_BASE UL(0x60050000) 34 35 /* 36 * Other platform porting definitions are provided by included headers 37 */ 38 39 /* 40 * Required ARM standard platform porting definitions 41 */ 42 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 43 44 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 45 46 /* Use the bypass address */ 47 #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ 48 BL1_ROM_BYPASS_OFFSET) 49 50 #define NSRAM_BASE UL(0x2e000000) 51 #define NSRAM_SIZE UL(0x00008000) /* 32KB */ 52 53 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 54 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 55 56 /* Range of kernel DTB load address */ 57 #define JUNO_DTB_DRAM_MAP_START ULL(0x82000000) 58 #define JUNO_DTB_DRAM_MAP_SIZE ULL(0x00008000) /* 32KB */ 59 60 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 61 JUNO_DTB_DRAM_MAP_START, \ 62 JUNO_DTB_DRAM_MAP_SIZE, \ 63 MT_MEMORY | MT_RO | MT_NS) 64 65 /* virtual address used by dynamic mem_protect for chunk_base */ 66 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 67 68 /* 69 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 70 */ 71 72 #if USE_ROMLIB 73 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 74 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 75 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000) 76 #else 77 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 78 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 79 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0) 80 #endif 81 82 /* 83 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 84 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 85 * flash 86 */ 87 88 #if TRUSTED_BOARD_BOOT 89 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) 90 #else 91 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) 92 #endif /* TRUSTED_BOARD_BOOT */ 93 94 /* 95 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 96 * plat_arm_mmap array defined for each BL stage. 97 */ 98 #ifdef IMAGE_BL1 99 # define PLAT_ARM_MMAP_ENTRIES 7 100 # define MAX_XLAT_TABLES 4 101 #endif 102 103 #ifdef IMAGE_BL2 104 #ifdef SPD_opteed 105 # define PLAT_ARM_MMAP_ENTRIES 11 106 # define MAX_XLAT_TABLES 5 107 #else 108 # define PLAT_ARM_MMAP_ENTRIES 10 109 # define MAX_XLAT_TABLES 4 110 #endif 111 #endif 112 113 #ifdef IMAGE_BL2U 114 # define PLAT_ARM_MMAP_ENTRIES 5 115 # define MAX_XLAT_TABLES 3 116 #endif 117 118 #ifdef IMAGE_BL31 119 # define PLAT_ARM_MMAP_ENTRIES 7 120 # define MAX_XLAT_TABLES 5 121 #endif 122 123 #ifdef IMAGE_BL32 124 # define PLAT_ARM_MMAP_ENTRIES 6 125 # define MAX_XLAT_TABLES 4 126 #endif 127 128 /* 129 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 130 * plus a little space for growth. 131 */ 132 #if TRUSTED_BOARD_BOOT 133 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 134 #else 135 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) 136 #endif 137 138 /* 139 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 140 * little space for growth. 141 */ 142 #if TRUSTED_BOARD_BOOT 143 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 144 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 145 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 146 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 147 #else 148 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 149 #endif 150 #else 151 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 152 #endif 153 154 /* 155 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 156 * calculated using the current BL31 PROGBITS debug size plus the sizes of 157 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 158 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 159 */ 160 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) 161 162 #if JUNO_AARCH32_EL3_RUNTIME 163 /* 164 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 165 * calculated using the current BL32 PROGBITS debug size plus the sizes of 166 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 167 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 168 */ 169 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3D000) 170 #endif 171 172 /* 173 * Size of cacheable stacks 174 */ 175 #if defined(IMAGE_BL1) 176 # if TRUSTED_BOARD_BOOT 177 # define PLATFORM_STACK_SIZE UL(0x1000) 178 # else 179 # define PLATFORM_STACK_SIZE UL(0x440) 180 # endif 181 #elif defined(IMAGE_BL2) 182 # if TRUSTED_BOARD_BOOT 183 # define PLATFORM_STACK_SIZE UL(0x1000) 184 # else 185 # define PLATFORM_STACK_SIZE UL(0x400) 186 # endif 187 #elif defined(IMAGE_BL2U) 188 # define PLATFORM_STACK_SIZE UL(0x400) 189 #elif defined(IMAGE_BL31) 190 # if PLAT_XLAT_TABLES_DYNAMIC 191 # define PLATFORM_STACK_SIZE UL(0x800) 192 # else 193 # define PLATFORM_STACK_SIZE UL(0x400) 194 # endif 195 #elif defined(IMAGE_BL32) 196 # define PLATFORM_STACK_SIZE UL(0x440) 197 #endif 198 199 /* 200 * Since free SRAM space is scant, enable the ASSERTION message size 201 * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). 202 */ 203 #define PLAT_LOG_LEVEL_ASSERT 40 204 205 /* CCI related constants */ 206 #define PLAT_ARM_CCI_BASE UL(0x2c090000) 207 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 208 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 209 210 /* System timer related constants */ 211 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 212 213 /* TZC related constants */ 214 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 215 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 216 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 217 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 218 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 219 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 220 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 221 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 222 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 223 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 224 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 225 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 226 227 /* TZC related constants */ 228 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 229 230 /* 231 * Required ARM CSS based platform porting definitions 232 */ 233 234 /* GIC related constants (no GICR in GIC-400) */ 235 #define PLAT_ARM_GICD_BASE UL(0x2c010000) 236 #define PLAT_ARM_GICC_BASE UL(0x2c02f000) 237 #define PLAT_ARM_GICH_BASE UL(0x2c04f000) 238 #define PLAT_ARM_GICV_BASE UL(0x2c06f000) 239 240 /* MHU related constants */ 241 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) 242 243 /* 244 * Base address of the first memory region used for communication between AP 245 * and SCP. Used by the BOM and SCPI protocols. 246 */ 247 #if !CSS_USE_SCMI_SDS_DRIVER 248 /* 249 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 250 * means the SCP/AP configuration data gets overwritten when the AP initiates 251 * communication with the SCP. The configuration data is expected to be a 252 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 253 * which CPU is the primary, according to the shift and mask definitions below. 254 */ 255 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) 256 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 257 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 258 #endif 259 260 /* 261 * SCP_BL2 uses up whatever remaining space is available as it is loaded before 262 * anything else in this memory region and is handed over to the SCP before 263 * BL31 is loaded over the top. 264 */ 265 #define PLAT_CSS_MAX_SCP_BL2_SIZE \ 266 ((SCP_BL2_LIMIT - ARM_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK) 267 268 #define PLAT_CSS_MAX_SCP_BL2U_SIZE PLAT_CSS_MAX_SCP_BL2_SIZE 269 270 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 271 CSS_G1S_IRQ_PROPS(grp), \ 272 ARM_G1S_IRQ_PROPS(grp), \ 273 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 274 (grp), GIC_INTR_CFG_LEVEL), \ 275 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 276 (grp), GIC_INTR_CFG_LEVEL), \ 277 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 278 (grp), GIC_INTR_CFG_LEVEL), \ 279 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 280 (grp), GIC_INTR_CFG_LEVEL), \ 281 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 282 (grp), GIC_INTR_CFG_LEVEL), \ 283 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 284 (grp), GIC_INTR_CFG_LEVEL), \ 285 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 286 (grp), GIC_INTR_CFG_LEVEL), \ 287 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 288 (grp), GIC_INTR_CFG_LEVEL) 289 290 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 291 292 /* 293 * Required ARM CSS SoC based platform porting definitions 294 */ 295 296 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 297 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) 298 299 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 300 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 301 302 /* System power domain level */ 303 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 304 305 /* 306 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 307 */ 308 #ifdef __aarch64__ 309 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 310 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 311 #else 312 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 313 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 314 #endif 315 316 /* Number of SCMI channels on the platform */ 317 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 318 319 #endif /* PLATFORM_DEF_H */ 320