1 /*
2 * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <drivers/console.h>
9 #include <lib/mmio.h>
10 #include <mtk_apusys.h>
11 #include <plat/common/platform.h>
12
apusys_kernel_ctrl(uint64_t x1,uint64_t x2,uint64_t x3,uint64_t x4,uint32_t * ret1)13 uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
14 uint32_t *ret1)
15 {
16 uint32_t request_ops;
17
18 request_ops = (uint32_t)x1;
19 INFO("[APUSYS] ops=0x%x\n", request_ops);
20
21 switch (request_ops) {
22 case MTK_SIP_APU_START_MCU:
23 /* setup addr[33:32] in reviser */
24 mmio_write_32(REVISER_SECUREFW_CTXT, 0U);
25 mmio_write_32(REVISER_USDRFW_CTXT, 0U);
26
27 /* setup secure sideband */
28 mmio_write_32(AO_SEC_FW,
29 (SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) |
30 (0U << SEC_FW_DOMAIN_SHIFT));
31
32 /* setup boot address */
33 mmio_write_32(AO_MD32_BOOT_CTRL, 0U);
34
35 /* setup pre-define region */
36 mmio_write_32(AO_MD32_PRE_DEFINE,
37 (PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) |
38 (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) |
39 (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) |
40 (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G));
41
42 /* release runstall */
43 mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN);
44
45 INFO("[APUSYS] reviser_ctxt=%x,%x\n",
46 mmio_read_32(REVISER_SECUREFW_CTXT),
47 mmio_read_32(REVISER_USDRFW_CTXT));
48 INFO("[APUSYS]fw=0x%08x,boot=0x%08x,def=0x%08x,sys=0x%08x\n",
49 mmio_read_32(AO_SEC_FW),
50 mmio_read_32(AO_MD32_BOOT_CTRL),
51 mmio_read_32(AO_MD32_PRE_DEFINE),
52 mmio_read_32(AO_MD32_SYS_CTRL));
53 break;
54 case MTK_SIP_APU_STOP_MCU:
55 /* hold runstall */
56 mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL);
57
58 INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n",
59 mmio_read_32(AO_MD32_BOOT_CTRL),
60 mmio_read_32(AO_MD32_SYS_CTRL));
61 break;
62 default:
63 ERROR("%s, unknown request_ops = %x\n", __func__, request_ops);
64 break;
65 }
66
67 return 0UL;
68 }
69