1/* 2 * Copyright 2020 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8.section .text, "ax" 9 10#include <asm_macros.S> 11 12#ifndef NXP_COINED_BB 13#include <flash_info.h> 14#include <fspi.h> 15#endif 16#include <regs.h> 17#ifdef NXP_COINED_BB 18#include <snvs.h> 19#endif 20 21#include <plat_warm_rst.h> 22#include <platform_def.h> 23 24#define SDRAM_CFG 0x110 25#define SDRAM_CFG_2 0x114 26#define SDRAM_MD_CNTL 0x120 27#define SDRAM_INTERVAL 0x124 28#define TIMING_CFG_10 0x258 29#define DEBUG_2 0xF04 30#define DEBUG_26 0xF64 31#define DDR_DSR2 0xB24 32 33#define DDR_CNTRLR_2 0x2 34#define COUNT_100 1000 35 36 .globl _soc_sys_warm_reset 37 .align 12 38 39func _soc_sys_warm_reset 40 mov x3, xzr 41 b touch_line0 42start_line0: 43 mov x3, #1 44 mov x2, #NUM_OF_DDRC 45 ldr x1, =NXP_DDR_ADDR 461: 47 ldr w0, [x1, #SDRAM_CFG] 48 orr w0, w0, #SDRAM_CFG_MEM_HLT 49 str w0, [x1, #SDRAM_CFG] 502: 51 ldr w0, [x1, #DEBUG_2] 52 and w0, w0, #DDR_DBG_2_MEM_IDLE 53 cbz w0, 2b 54 55 ldr w0, [x1, #DEBUG_26] 56 orr w0, w0, #DDR_DEBUG_26_BIT_12 57 orr w0, w0, #DDR_DEBUG_26_BIT_13 58 orr w0, w0, #DDR_DEBUG_26_BIT_14 59touch_line0: 60 cbz x3, touch_line1 61 62 orr w0, w0, #DDR_DEBUG_26_BIT_15 63 orr w0, w0, #DDR_DEBUG_26_BIT_16 64 str w0, [x1, #DEBUG_26] 65 66 ldr w0, [x1, #SDRAM_CFG_2] 67 orr w0, w0, #SDRAM_CFG2_FRC_SR 68 str w0, [x1, #SDRAM_CFG_2] 69 703: 71 ldr w0, [x1, #DDR_DSR2] 72 orr w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT 73 str w0, [x1, #DDR_DSR2] 74 ldr w0, [x1, #DDR_DSR2] 75 and w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT 76 cbnz w0, 3b 77 78 ldr w0, [x1, #SDRAM_INTERVAL] 79 and w0, w0, #SDRAM_INTERVAL_REFINT_CLEAR 80 str w0, [x1, #SDRAM_INTERVAL] 81touch_line1: 82 cbz x3, touch_line2 83 84 ldr w0, [x1, #SDRAM_MD_CNTL] 85 orr w0, w0, #MD_CNTL_CKE(1) 86 orr w0, w0, #MD_CNTL_MD_EN 87 str w0, [x1, #SDRAM_MD_CNTL] 88 89 ldr w0, [x1, #TIMING_CFG_10] 90 orr w0, w0, #DDR_TIMING_CFG_10_T_STAB 91 str w0, [x1, #TIMING_CFG_10] 92 93 ldr w0, [x1, #SDRAM_CFG_2] 94 and w0, w0, #SDRAM_CFG2_FRC_SR_CLEAR 95 str w0, [x1, #SDRAM_CFG_2] 96 974: 98 ldr w0, [x1, #DDR_DSR2] 99 and w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT 100 cbz w0, 4b 101 nop 102touch_line2: 103 cbz x3, touch_line3 104 105 ldr w0, [x1, #DEBUG_26] 106 orr w0, w0, #DDR_DEBUG_26_BIT_25 107 and w0, w0, #DDR_DEBUG_26_BIT_24_CLEAR 108 str w0, [x1, #DEBUG_26] 109 110 cmp x2, #DDR_CNTRLR_2 111 b.ne 5f 112 ldr x1, =NXP_DDR2_ADDR 113 mov x2, xzr 114 b 1b 115 1165: 117 mov x5, xzr 1186: 119 add x5, x5, #1 120 cmp x5, #COUNT_100 121 b.ne 6b 122 nop 123touch_line3: 124 cbz x3, touch_line4 125#ifdef NXP_COINED_BB 126 ldr x1, =NXP_SNVS_ADDR 127 ldr w0, [x1, #NXP_APP_DATA_LP_GPR_OFFSET] 128 129 /* On Warm Boot is enabled, then zeroth bit 130 * of SNVS LP GPR register 0 will used 131 * to save the status of warm-reset as a cause. 132 */ 133 orr w0, w0, #(1 << NXP_LPGPR_ZEROTH_BIT) 134 135 /* write back */ 136 str w0, [x1, #NXP_APP_DATA_LP_GPR_OFFSET] 137 nop 138 nop 139 nop 140 nop 141 nop 142 nop 143 nop 144 nop 145 nop 146 nop 147 nop 148touch_line4: 149 cbz x3, touch_line6 150#elif !(ERLY_WRM_RST_FLG_FLSH_UPDT) 151 ldr x1, =NXP_FLEXSPI_ADDR 152 ldr w0, [x1, #FSPI_IPCMD] 153 orr w0, w0, #FSPI_IPCMD_TRG_MASK 154 str w0, [x1, #FSPI_IPCMD] 1557: 156 ldr w0, [x1, #FSPI_INTR] 157 and w0, w0, #FSPI_INTR_IPCMDDONE_MASK 158 cmp w0, #0 159 b.eq 7b 160 161 ldr w0, [x1, #FSPI_IPTXFCR] 162 orr w0, w0, #FSPI_IPTXFCR_CLR 163 str w0, [x1, #FSPI_IPTXFCR] 164 165 ldr w0, [x1, #FSPI_INTR] 166 orr w0, w0, #FSPI_INTR_IPCMDDONE_MASK 167 str w0, [x1, #FSPI_INTR] 168 nop 169touch_line4: 170 cbz x3, touch_line5 171 /* flexspi driver has an api 172 * is_flash_busy(). 173 * Impelementation of the api will not 174 * fit-in in 1 cache line. 175 * instead a nop-cycles are introduced to 176 * simulate the wait time for flash write 177 * completion. 178 * 179 * Note: This wait time varies from flash to flash. 180 */ 181 182 mov x0, #FLASH_WR_COMP_WAIT_BY_NOP_COUNT 1838: 184 sub x0, x0, #1 185 nop 186 cmp x0, #0 187 b.ne 8b 188 nop 189 nop 190 nop 191 nop 192 nop 193 nop 194 nop 195 nop 196 nop 197touch_line5: 198 cbz x3, touch_line6 199#endif 200 ldr x2, =NXP_RST_ADDR 201 /* clear the RST_REQ_MSK and SW_RST_REQ */ 202 mov w0, #0x00000000 203 str w0, [x2, #RSTCNTL_OFFSET] 204 205 /* initiate the sw reset request */ 206 mov w0, #SW_RST_REQ_INIT 207 str w0, [x2, #RSTCNTL_OFFSET] 208 209 /* In case this address range is mapped as cacheable, 210 * flush the write out of the dcaches. 211 */ 212 add x2, x2, #RSTCNTL_OFFSET 213 dc cvac, x2 214 dsb st 215 isb 216 217 /* Function does not return */ 218 b . 219 nop 220 nop 221 nop 222 nop 223 nop 224 nop 225 nop 226touch_line6: 227 cbz x3, start_line0 228 229endfunc _soc_sys_warm_reset 230