1From 5d631cb16e7ba5dd0380ff1ee9dda192b1cdad18 Mon Sep 17 00:00:00 2001 2From: mephi42 <mephi42@gmail.com> 3Date: Tue, 7 Aug 2018 17:02:40 +0200 4Subject: [PATCH 1/7] capstone: generate *GenRegisterInfo.inc 5 6--- 7 utils/TableGen/RegisterInfoEmitter.cpp | 130 ++++++++++++++++++++++--- 8 1 file changed, 115 insertions(+), 15 deletions(-) 9 10diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp 11index 49016cca799..6ebb7148b1b 100644 12--- a/utils/TableGen/RegisterInfoEmitter.cpp 13+++ b/utils/TableGen/RegisterInfoEmitter.cpp 14@@ -99,6 +99,12 @@ private: 15 16 } // end anonymous namespace 17 18+#ifdef CAPSTONE 19+#define NAME_PREFIX Target.getName() << "_" << 20+#else 21+#define NAME_PREFIX 22+#endif 23+ 24 // runEnums - Print out enum values for all of the registers. 25 void RegisterInfoEmitter::runEnums(raw_ostream &OS, 26 CodeGenTarget &Target, CodeGenRegBank &Bank) { 27@@ -107,13 +113,22 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, 28 // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 29 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 30 31+#ifndef CAPSTONE 32 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); 33+#endif 34 35 emitSourceFileHeader("Target Register Enum Values", OS); 36 37+#ifdef CAPSTONE 38+ OS << "/* Capstone Disassembly Engine */\n" 39+ "/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */\n" 40+ "\n"; 41+#endif 42+ 43 OS << "\n#ifdef GET_REGINFO_ENUM\n"; 44 OS << "#undef GET_REGINFO_ENUM\n\n"; 45 46+#ifndef CAPSTONE 47 OS << "namespace llvm {\n\n"; 48 49 OS << "class MCRegisterClass;\n" 50@@ -122,16 +137,20 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, 51 52 if (!Namespace.empty()) 53 OS << "namespace " << Namespace << " {\n"; 54- OS << "enum {\n NoRegister,\n"; 55+#endif 56+ 57+ OS << "enum {\n " << NAME_PREFIX "NoRegister,\n"; 58 59 for (const auto &Reg : Registers) 60- OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; 61+ OS << " " << NAME_PREFIX Reg.getName() << " = " << Reg.EnumValue << ",\n"; 62 assert(Registers.size() == Registers.back().EnumValue && 63 "Register enum value mismatch!"); 64- OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 65+ OS << " " << NAME_PREFIX "NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 66 OS << "};\n"; 67+#ifndef CAPSTONE 68 if (!Namespace.empty()) 69 OS << "} // end namespace " << Namespace << "\n"; 70+#endif 71 72 const auto &RegisterClasses = Bank.getRegClasses(); 73 if (!RegisterClasses.empty()) { 74@@ -140,18 +159,29 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, 75 assert(RegisterClasses.size() <= 0xffff && 76 "Too many register classes to fit in tables"); 77 78- OS << "\n// Register classes\n\n"; 79+ OS << "\n// Register classes\n"; 80+#ifndef CAPSTONE 81+ OS << "\n"; 82 if (!Namespace.empty()) 83 OS << "namespace " << Namespace << " {\n"; 84+#endif 85 OS << "enum {\n"; 86 for (const auto &RC : RegisterClasses) 87- OS << " " << RC.getName() << "RegClassID" 88+ OS << " " << NAME_PREFIX RC.getName() << "RegClassID" 89 << " = " << RC.EnumValue << ",\n"; 90- OS << "\n };\n"; 91+#ifdef CAPSTONE 92+ OS 93+#else 94+ OS << "\n " 95+#endif 96+ << "};\n"; 97+#ifndef CAPSTONE 98 if (!Namespace.empty()) 99 OS << "} // end namespace " << Namespace << "\n\n"; 100+#endif 101 } 102 103+#ifndef CAPSTONE 104 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); 105 // If the only definition is the default NoRegAltName, we don't need to 106 // emit anything. 107@@ -182,8 +212,11 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, 108 if (!Namespace.empty()) 109 OS << "} // end namespace " << Namespace << "\n\n"; 110 } 111+#endif 112 113+#ifndef CAPSTONE 114 OS << "} // end namespace llvm\n\n"; 115+#endif 116 OS << "#endif // GET_REGINFO_ENUM\n\n"; 117 } 118 119@@ -830,7 +863,9 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 120 121 const auto &Regs = RegBank.getRegisters(); 122 123+#ifndef CAPSTONE 124 auto &SubRegIndices = RegBank.getSubRegIndices(); 125+#endif 126 // The lists of sub-registers and super-registers go in the same array. That 127 // allows us to share suffixes. 128 typedef std::vector<const CodeGenRegister*> RegVec; 129@@ -922,25 +957,40 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 130 LaneMaskSeqs.layout(); 131 SubRegIdxSeqs.layout(); 132 133+#ifndef CAPSTONE 134 OS << "namespace llvm {\n\n"; 135+#endif 136 137 const std::string &TargetName = Target.getName(); 138 139 // Emit the shared table of differential lists. 140- OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 141+#ifdef CAPSTONE 142+ OS << "static" 143+#else 144+ OS << "extern" 145+#endif 146+ << " const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 147 DiffSeqs.emit(OS, printDiff16); 148 OS << "};\n\n"; 149 150+#ifndef CAPSTONE 151 // Emit the shared table of regunit lane mask sequences. 152 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; 153 LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); 154 OS << "};\n\n"; 155+#endif 156 157 // Emit the table of sub-register indexes. 158- OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 159+#ifdef CAPSTONE 160+ OS << "static" 161+#else 162+ OS << "extern" 163+#endif 164+ << " const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 165 SubRegIdxSeqs.emit(OS, printSubRegIndex); 166 OS << "};\n\n"; 167 168+#ifndef CAPSTONE 169 // Emit the table of sub-register index sizes. 170 OS << "extern const MCRegisterInfo::SubRegCoveredBits " 171 << TargetName << "SubRegIdxRanges[] = {\n"; 172@@ -950,14 +1000,22 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 173 << Idx.getName() << "\n"; 174 } 175 OS << "};\n\n"; 176+#endif 177 178 // Emit the string table. 179 RegStrings.layout(); 180+#ifndef CAPSTONE 181 OS << "extern const char " << TargetName << "RegStrings[] = {\n"; 182 RegStrings.emit(OS, printChar); 183 OS << "};\n\n"; 184+#endif 185 186- OS << "extern const MCRegisterDesc " << TargetName 187+#ifdef CAPSTONE 188+ OS << "static" 189+#else 190+ OS << "extern" 191+#endif 192+ << " const MCRegisterDesc " << TargetName 193 << "RegDesc[] = { // Descriptors\n"; 194 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 195 196@@ -973,6 +1031,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 197 } 198 OS << "};\n\n"; // End of register descriptors... 199 200+#ifndef CAPSTONE 201 // Emit the table of register unit roots. Each regunit has one or two root 202 // registers. 203 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; 204@@ -986,11 +1045,14 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 205 OS << " },\n"; 206 } 207 OS << "};\n\n"; 208+#endif 209 210 const auto &RegisterClasses = RegBank.getRegClasses(); 211 212 // Loop over all of the register classes... emitting each one. 213+#ifndef CAPSTONE 214 OS << "namespace { // Register classes...\n"; 215+#endif 216 217 SequenceToOffsetTable<std::string> RegClassStrings; 218 219@@ -1005,15 +1067,28 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 220 221 // Emit the register list now. 222 OS << " // " << Name << " Register Class...\n" 223- << " const MCPhysReg " << Name 224+ << " " 225+#ifdef CAPSTONE 226+ << "static " 227+#endif 228+ << "const MCPhysReg " << Name 229 << "[] = {\n "; 230 for (Record *Reg : Order) { 231- OS << getQualifiedName(Reg) << ", "; 232+#ifdef CAPSTONE 233+ OS << NAME_PREFIX Reg->getName() 234+#else 235+ OS << getQualifiedName(Reg) 236+#endif 237+ << ", "; 238 } 239 OS << "\n };\n\n"; 240 241 OS << " // " << Name << " Bit set.\n" 242- << " const uint8_t " << Name 243+ << " " 244+#ifdef CAPSTONE 245+ << "static " 246+#endif 247+ << "const uint8_t " << Name 248 << "Bits[] = {\n "; 249 BitVectorEmitter BVE; 250 for (Record *Reg : Order) { 251@@ -1023,14 +1098,23 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 252 OS << "\n };\n\n"; 253 254 } 255+#ifndef CAPSTONE 256 OS << "} // end anonymous namespace\n\n"; 257+#endif 258 259 RegClassStrings.layout(); 260+#ifndef CAPSTONE 261 OS << "extern const char " << TargetName << "RegClassStrings[] = {\n"; 262 RegClassStrings.emit(OS, printChar); 263 OS << "};\n\n"; 264+#endif 265 266- OS << "extern const MCRegisterClass " << TargetName 267+#ifdef CAPSTONE 268+ OS << "static" 269+#else 270+ OS << "extern" 271+#endif 272+ << " const MCRegisterClass " << TargetName 273 << "MCRegisterClasses[] = {\n"; 274 275 for (const auto &RC : RegisterClasses) { 276@@ -1041,7 +1125,12 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 277 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " 278 << RegClassStrings.get(RC.getName()) << ", " 279 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " 280- << RC.getQualifiedName() + "RegClassID" << ", " 281+#ifdef CAPSTONE 282+ << NAME_PREFIX RC.getName() 283+#else 284+ << RC.getQualifiedName() 285+#endif 286+ << "RegClassID" << ", " 287 << RegSize/8 << ", " 288 << RC.CopyCost << ", " 289 << ( RC.Allocatable ? "true" : "false" ) << " },\n"; 290@@ -1049,6 +1138,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 291 292 OS << "};\n\n"; 293 294+#ifndef CAPSTONE 295 EmitRegMappingTables(OS, Regs, false); 296 297 // Emit Reg encoding table 298@@ -1067,7 +1157,9 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 299 OS << " " << Value << ",\n"; 300 } 301 OS << "};\n"; // End of HW encoding table 302+#endif 303 304+#ifndef CAPSTONE 305 // MCRegisterInfo initialization routine. 306 OS << "static inline void Init" << TargetName 307 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 308@@ -1088,7 +1180,12 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 309 OS << "}\n\n"; 310 311 OS << "} // end namespace llvm\n\n"; 312- OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 313+#endif 314+ OS << "#endif // GET_REGINFO_MC_DESC\n" 315+#ifndef CAPSTONE 316+ << "\n" 317+#endif 318+ ; 319 } 320 321 void 322@@ -1568,10 +1665,13 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 323 324 void RegisterInfoEmitter::run(raw_ostream &OS) { 325 CodeGenRegBank &RegBank = Target.getRegBank(); 326+ 327 runEnums(OS, Target, RegBank); 328 runMCDesc(OS, Target, RegBank); 329+#ifndef CAPSTONE 330 runTargetHeader(OS, Target, RegBank); 331 runTargetDesc(OS, Target, RegBank); 332+#endif 333 334 if (RegisterInfoDebug) 335 debugDump(errs()); 336-- 3372.19.1 338 339