1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Mika Kuoppala <mika.kuoppala@intel.com>
25 */
26
27 #include "intel_renderstate.h"
28 #include "intel_batchbuffer.h"
29 #include <lib/gen8_render.h>
30 #include <lib/intel_reg.h>
31 #include <string.h>
32
gen8_emit_wm(struct intel_batchbuffer * batch)33 static void gen8_emit_wm(struct intel_batchbuffer *batch)
34 {
35 OUT_BATCH(GEN6_3DSTATE_WM | (2 - 2));
36 OUT_BATCH(GEN8_WM_LEGACY_DIAMOND_LINE_RASTERIZATION);
37 }
38
gen8_emit_ps(struct intel_batchbuffer * batch)39 static void gen8_emit_ps(struct intel_batchbuffer *batch)
40 {
41 OUT_BATCH(GEN7_3DSTATE_PS | (12 - 2));
42 OUT_BATCH(0);
43 OUT_BATCH(0); /* kernel hi */
44 OUT_BATCH(GEN7_PS_SPF_MODE);
45 OUT_BATCH(0); /* scratch space stuff */
46 OUT_BATCH(0); /* scratch hi */
47 OUT_BATCH(0);
48 OUT_BATCH(0);
49 OUT_BATCH(0); // kernel 1
50 OUT_BATCH(0); /* kernel 1 hi */
51 OUT_BATCH(0); // kernel 2
52 OUT_BATCH(0); /* kernel 2 hi */
53 }
54
gen8_emit_sf(struct intel_batchbuffer * batch)55 static void gen8_emit_sf(struct intel_batchbuffer *batch)
56 {
57 OUT_BATCH(GEN6_3DSTATE_SF | (4 - 2));
58 OUT_BATCH(0);
59 OUT_BATCH(0);
60 OUT_BATCH(1 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT |
61 1 << GEN6_3DSTATE_SF_VERTEX_SUB_PIXEL_PRECISION_SHIFT |
62 GEN8_SF_POINT_WIDTH_FROM_SOURCE |
63 8);
64 }
65
gen8_emit_vs(struct intel_batchbuffer * batch)66 static void gen8_emit_vs(struct intel_batchbuffer *batch)
67 {
68 OUT_BATCH(GEN6_3DSTATE_VS | (9 - 2));
69 OUT_BATCH(0);
70 OUT_BATCH(0);
71 OUT_BATCH(GEN8_VS_FLOATING_POINT_MODE_ALTERNATE);
72 OUT_BATCH(0);
73 OUT_BATCH(0);
74 OUT_BATCH(0);
75 OUT_BATCH(0);
76 OUT_BATCH(0);
77 }
78
gen8_emit_hs(struct intel_batchbuffer * batch)79 static void gen8_emit_hs(struct intel_batchbuffer *batch)
80 {
81 OUT_BATCH(GEN7_3DSTATE_HS | (9 - 2));
82 OUT_BATCH(0);
83 OUT_BATCH(0);
84 OUT_BATCH(0);
85 OUT_BATCH(0);
86 OUT_BATCH(0);
87 OUT_BATCH(0);
88 OUT_BATCH(1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT);
89 OUT_BATCH(0);
90 }
91
gen8_emit_raster(struct intel_batchbuffer * batch)92 static void gen8_emit_raster(struct intel_batchbuffer *batch)
93 {
94 OUT_BATCH(GEN8_3DSTATE_RASTER | (5 - 2));
95 OUT_BATCH(0);
96 OUT_BATCH(0.0);
97 OUT_BATCH(0.0);
98 OUT_BATCH(0.0);
99 }
100
gen8_emit_urb(struct intel_batchbuffer * batch)101 static void gen8_emit_urb(struct intel_batchbuffer *batch)
102 {
103 const int vs_entries = 64;
104 const int vs_size = 2;
105 const int vs_start = 4;
106
107 OUT_BATCH(GEN7_3DSTATE_URB_VS);
108 OUT_BATCH(vs_entries | ((vs_size - 1) << 16) | (vs_start << 25));
109
110 OUT_BATCH(GEN7_3DSTATE_URB_HS);
111 OUT_BATCH(0x0f << 25);
112
113 OUT_BATCH(GEN7_3DSTATE_URB_DS);
114 OUT_BATCH(0x0f << 25);
115
116 OUT_BATCH(GEN7_3DSTATE_URB_GS);
117 OUT_BATCH(0x0f << 25);
118 }
119
gen8_emit_vf_topology(struct intel_batchbuffer * batch)120 static void gen8_emit_vf_topology(struct intel_batchbuffer *batch)
121 {
122 OUT_BATCH(GEN8_3DSTATE_VF_TOPOLOGY);
123 OUT_BATCH(_3DPRIM_TRILIST);
124 }
125
gen8_emit_so_decl_list(struct intel_batchbuffer * batch)126 static void gen8_emit_so_decl_list(struct intel_batchbuffer *batch)
127 {
128 const int num_decls = 128;
129 int i;
130
131 OUT_BATCH(GEN8_3DSTATE_SO_DECL_LIST | ((2 * num_decls) + 1));
132 OUT_BATCH(0);
133 OUT_BATCH(num_decls);
134
135 for (i = 0; i < num_decls; i++) {
136 OUT_BATCH(0);
137 OUT_BATCH(0);
138 }
139 }
140
gen8_emit_so_buffer(struct intel_batchbuffer * batch,const int index)141 static void gen8_emit_so_buffer(struct intel_batchbuffer *batch, const int index)
142 {
143 OUT_BATCH(GEN8_3DSTATE_SO_BUFFER | (8 - 2));
144 OUT_BATCH(index << 29);
145 OUT_BATCH(0);
146 OUT_BATCH(0);
147 OUT_BATCH(0);
148 OUT_BATCH(0);
149 OUT_BATCH(0);
150 OUT_BATCH(0);
151 }
152
gen8_emit_state_base_address(struct intel_batchbuffer * batch)153 static void gen8_emit_state_base_address(struct intel_batchbuffer *batch) {
154 const unsigned offset = 0;
155 OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (16 - 2));
156
157 /* general */
158 OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY);
159 OUT_BATCH(0);
160
161 /* stateless data port */
162 OUT_BATCH(0);
163
164 /* surface state base addess */
165 OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY);
166 OUT_BATCH(0);
167
168 /* dynamic state base address */
169 OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY);
170 OUT_BATCH(0);
171
172 /* indirect */
173 OUT_BATCH(BASE_ADDRESS_MODIFY);
174 OUT_BATCH(0);
175
176 /* instruction */
177 OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY);
178 OUT_BATCH(0);
179
180 /* general state buffer size */
181 OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY);
182 /* dynamic state buffer size */
183 OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY);
184 /* indirect object buffer size */
185 OUT_BATCH(0 | BUFFER_SIZE_MODIFY);
186 /* intruction buffer size */
187 OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY);
188 }
189
gen8_emit_chroma_key(struct intel_batchbuffer * batch,const int index)190 static void gen8_emit_chroma_key(struct intel_batchbuffer *batch, const int index)
191 {
192 OUT_BATCH(GEN6_3DSTATE_CHROMA_KEY | (4 - 2));
193 OUT_BATCH(index << 30);
194 OUT_BATCH(0);
195 OUT_BATCH(0);
196 }
197
gen8_emit_vertex_buffers(struct intel_batchbuffer * batch)198 static void gen8_emit_vertex_buffers(struct intel_batchbuffer *batch)
199 {
200 const int buffers = 33;
201 int i;
202
203 OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | ((4 * buffers) - 1));
204
205 for (i = 0; i < buffers; i++) {
206 OUT_BATCH(i << GEN6_VB0_BUFFER_INDEX_SHIFT |
207 GEN8_VB0_BUFFER_ADDR_MOD_EN);
208 OUT_BATCH(0); /* Addr */
209 OUT_BATCH(0);
210 OUT_BATCH(0);
211 }
212 }
213
gen6_emit_vertex_elements(struct intel_batchbuffer * batch)214 static void gen6_emit_vertex_elements(struct intel_batchbuffer *batch)
215 {
216 const int elements = 34;
217 int i;
218
219 OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | ((2 * elements - 1)));
220
221 for (i = 0; i < elements; i++) {
222 if (i == 0) {
223 OUT_BATCH(GEN6_VE0_VALID | i);
224 OUT_BATCH(
225 GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
226 GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
227 GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
228 GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT
229 );
230 } else {
231 OUT_BATCH(0);
232 OUT_BATCH(0);
233 }
234 }
235 }
236
gen8_emit_cc_state_pointers(struct intel_batchbuffer * batch)237 static void gen8_emit_cc_state_pointers(struct intel_batchbuffer *batch)
238 {
239 union {
240 float fval;
241 uint32_t uval;
242 } u;
243
244 unsigned offset;
245
246 u.fval = 1.0f;
247
248 offset = intel_batch_state_offset(batch, 64);
249 OUT_STATE(0);
250 OUT_STATE(0); /* Alpha reference value */
251 OUT_STATE(u.uval); /* Blend constant color RED */
252 OUT_STATE(u.uval); /* Blend constant color BLUE */
253 OUT_STATE(u.uval); /* Blend constant color GREEN */
254 OUT_STATE(u.uval); /* Blend constant color ALPHA */
255
256 OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS);
257 OUT_BATCH_STATE_OFFSET(offset | 1);
258 }
259
gen8_emit_blend_state_pointers(struct intel_batchbuffer * batch)260 static void gen8_emit_blend_state_pointers(struct intel_batchbuffer *batch)
261 {
262 unsigned offset;
263 int i;
264
265 offset = intel_batch_state_offset(batch, 64);
266
267 for (i = 0; i < 17; i++)
268 OUT_STATE(0);
269
270 OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
271 OUT_BATCH_STATE_OFFSET(offset | 1);
272 }
273
gen8_emit_ps_extra(struct intel_batchbuffer * batch)274 static void gen8_emit_ps_extra(struct intel_batchbuffer *batch)
275 {
276 OUT_BATCH(GEN8_3DSTATE_PS_EXTRA | (2 - 2));
277 OUT_BATCH(GEN8_PSX_PIXEL_SHADER_VALID |
278 GEN8_PSX_ATTRIBUTE_ENABLE);
279
280 }
281
gen8_emit_ps_blend(struct intel_batchbuffer * batch)282 static void gen8_emit_ps_blend(struct intel_batchbuffer *batch)
283 {
284 OUT_BATCH(GEN8_3DSTATE_PS_BLEND | (2 - 2));
285 OUT_BATCH(GEN8_PS_BLEND_HAS_WRITEABLE_RT);
286 }
287
gen8_emit_viewport_state_pointers_cc(struct intel_batchbuffer * batch)288 static void gen8_emit_viewport_state_pointers_cc(struct intel_batchbuffer *batch)
289 {
290 unsigned offset;
291
292 offset = intel_batch_state_offset(batch, 32);
293
294 OUT_STATE((uint32_t)0.0f); /* Minimum depth */
295 OUT_STATE((uint32_t)0.0f); /* Maximum depth */
296
297 OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
298 OUT_BATCH_STATE_OFFSET(offset);
299 }
300
gen8_emit_viewport_state_pointers_sf_clip(struct intel_batchbuffer * batch)301 static void gen8_emit_viewport_state_pointers_sf_clip(struct intel_batchbuffer *batch)
302 {
303 unsigned offset;
304 int i;
305
306 offset = intel_batch_state_offset(batch, 64);
307
308 for (i = 0; i < 16; i++)
309 OUT_STATE(0);
310
311 OUT_BATCH(GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP | (2 - 2));
312 OUT_BATCH_STATE_OFFSET(offset);
313 }
314
gen8_emit_primitive(struct intel_batchbuffer * batch)315 static void gen8_emit_primitive(struct intel_batchbuffer *batch)
316 {
317 OUT_BATCH(GEN4_3DPRIMITIVE | (7 - 2));
318 OUT_BATCH(4); /* gen8+ ignore the topology type field */
319 OUT_BATCH(1); /* vertex count */
320 OUT_BATCH(0);
321 OUT_BATCH(1); /* single instance */
322 OUT_BATCH(0); /* start instance location */
323 OUT_BATCH(0); /* index buffer offset, ignored */
324 }
325
gen8_setup_null_render_state(struct intel_batchbuffer * batch)326 void gen8_setup_null_render_state(struct intel_batchbuffer *batch)
327 {
328 #define GEN8_PIPE_CONTROL_GLOBAL_GTT (1 << 24)
329
330 OUT_BATCH(GEN6_PIPE_CONTROL | (6 - 2));
331 OUT_BATCH(GEN8_PIPE_CONTROL_GLOBAL_GTT);
332 OUT_BATCH(0);
333 OUT_BATCH(0);
334 OUT_BATCH(0);
335 OUT_BATCH(0);
336
337 OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D);
338
339 gen8_emit_wm(batch);
340 gen8_emit_ps(batch);
341 gen8_emit_sf(batch);
342
343 OUT_CMD(GEN7_3DSTATE_SBE, 4);
344 OUT_CMD(GEN8_3DSTATE_SBE_SWIZ, 11);
345
346 gen8_emit_vs(batch);
347 gen8_emit_hs(batch);
348
349 OUT_CMD(GEN6_3DSTATE_GS, 10);
350 OUT_CMD(GEN7_3DSTATE_STREAMOUT, 5);
351 OUT_CMD(GEN7_3DSTATE_DS, 9);
352 OUT_CMD(GEN6_3DSTATE_CLIP, 4);
353 gen8_emit_raster(batch);
354 OUT_CMD(GEN7_3DSTATE_TE, 4);
355 OUT_CMD(GEN8_3DSTATE_VF, 2);
356 OUT_CMD(GEN8_3DSTATE_WM_HZ_OP, 5);
357
358 gen8_emit_urb(batch);
359
360 OUT_CMD(GEN8_3DSTATE_BIND_TABLE_POOL_ALLOC, 4);
361 OUT_CMD(GEN8_3DSTATE_GATHER_POOL_ALLOC, 4);
362 OUT_CMD(GEN8_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC, 4);
363 OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS, 2);
364 OUT_CMD(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS, 2);
365 OUT_CMD(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS, 2);
366 OUT_CMD(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS, 2);
367 OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS, 2);
368 OUT_CMD(GEN6_3DSTATE_CONSTANT_VS, 11);
369 OUT_CMD(GEN7_3DSTATE_CONSTANT_HS, 11);
370 OUT_CMD(GEN7_3DSTATE_CONSTANT_DS, 11);
371 OUT_CMD(GEN6_3DSTATE_CONSTANT_GS, 11);
372 OUT_CMD(GEN6_3DSTATE_CONSTANT_PS, 11);
373 OUT_CMD(GEN8_3DSTATE_VF_INSTANCING, 3);
374 OUT_CMD(GEN8_3DSTATE_VF_SGVS, 2);
375
376 gen8_emit_vf_topology(batch);
377 gen8_emit_so_decl_list(batch);
378
379 gen8_emit_so_buffer(batch, 0);
380 gen8_emit_so_buffer(batch, 1);
381 gen8_emit_so_buffer(batch, 2);
382 gen8_emit_so_buffer(batch, 3);
383
384 gen8_emit_state_base_address(batch);
385
386 OUT_CMD(GEN4_STATE_SIP, 3);
387 OUT_CMD(GEN4_3DSTATE_DRAWING_RECTANGLE, 4);
388 OUT_CMD(GEN7_3DSTATE_DEPTH_BUFFER, 8);
389
390 gen8_emit_chroma_key(batch, 0);
391 gen8_emit_chroma_key(batch, 1);
392 gen8_emit_chroma_key(batch, 2);
393 gen8_emit_chroma_key(batch, 3);
394
395 OUT_CMD(GEN6_3DSTATE_LINE_STIPPLE, 3);
396 OUT_CMD(GEN6_3DSTATE_AA_LINE_PARAMS, 3);
397 OUT_CMD(GEN8_3DSTATE_STENCIL_BUFFER, 5);
398 OUT_CMD(GEN8_3DSTATE_HIER_DEPTH_BUFFER, 5);
399 OUT_CMD(GEN7_3DSTATE_CLEAR_PARAMS, 3);
400 OUT_CMD(GEN6_3DSTATE_MONOFILTER_SIZE, 2);
401 OUT_CMD(GEN8_3DSTATE_MULTISAMPLE, 2);
402 OUT_CMD(GEN6_3DSTATE_POLY_STIPPLE_OFFSET, 2);
403 OUT_CMD(GEN6_3DSTATE_POLY_STIPPLE_PATTERN, 33);
404 OUT_CMD(GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0, 16 + 1);
405 OUT_CMD(GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1, 16 + 1);
406 OUT_CMD(GEN6_3DSTATE_INDEX_BUFFER, 5);
407
408 gen8_emit_vertex_buffers(batch);
409 gen6_emit_vertex_elements(batch);
410
411 OUT_BATCH(GEN6_3DSTATE_VF_STATISTICS | 1); /* Enable */
412
413 OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS, 2);
414 OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS, 2);
415 OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS, 2);
416 OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS, 2);
417 OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS, 2);
418
419 gen8_emit_cc_state_pointers(batch);
420 gen8_emit_blend_state_pointers(batch);
421
422 gen8_emit_ps_extra(batch);
423 gen8_emit_ps_blend(batch);
424
425 OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS, 2);
426 OUT_CMD(GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS, 2);
427 OUT_CMD(GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS, 2);
428 OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS, 2);
429 OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS, 2);
430
431 OUT_CMD(GEN8_3DSTATE_SCISSOR_STATE_POINTERS, 2);
432
433 gen8_emit_viewport_state_pointers_cc(batch);
434 gen8_emit_viewport_state_pointers_sf_clip(batch);
435
436 gen8_emit_primitive(batch);
437
438 OUT_BATCH(MI_BATCH_BUFFER_END);
439 }
440