1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Armin Reese <armin.c.reese@intel.com>
25 * Mika Kuoppala <mika.kuoppala@intel.com>
26 */
27
28 #include "intel_renderstate.h"
29 #include <lib/gen9_render.h>
30 #include <lib/intel_reg.h>
31
gen8_emit_wm(struct intel_batchbuffer * batch)32 static void gen8_emit_wm(struct intel_batchbuffer *batch)
33 {
34 OUT_BATCH(GEN6_3DSTATE_WM | (2 - 2));
35 OUT_BATCH(GEN8_WM_LEGACY_DIAMOND_LINE_RASTERIZATION);
36 }
37
gen8_emit_ps(struct intel_batchbuffer * batch)38 static void gen8_emit_ps(struct intel_batchbuffer *batch)
39 {
40 OUT_BATCH(GEN7_3DSTATE_PS | (12 - 2));
41 OUT_BATCH(0);
42 OUT_BATCH(0); /* kernel hi */
43 OUT_BATCH(GEN7_PS_SPF_MODE);
44 OUT_BATCH(0); /* scratch space stuff */
45 OUT_BATCH(0); /* scratch hi */
46 OUT_BATCH(0);
47 OUT_BATCH(0);
48 OUT_BATCH(0); // kernel 1
49 OUT_BATCH(0); /* kernel 1 hi */
50 OUT_BATCH(0); // kernel 2
51 OUT_BATCH(0); /* kernel 2 hi */
52 }
53
gen8_emit_sf(struct intel_batchbuffer * batch)54 static void gen8_emit_sf(struct intel_batchbuffer *batch)
55 {
56 OUT_BATCH(GEN6_3DSTATE_SF | (4 - 2));
57 OUT_BATCH(0);
58 OUT_BATCH(0);
59 OUT_BATCH(1 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT |
60 1 << GEN6_3DSTATE_SF_VERTEX_SUB_PIXEL_PRECISION_SHIFT |
61 GEN8_SF_POINT_WIDTH_FROM_SOURCE |
62 8);
63 }
64
gen8_emit_vs(struct intel_batchbuffer * batch)65 static void gen8_emit_vs(struct intel_batchbuffer *batch)
66 {
67 OUT_BATCH(GEN6_3DSTATE_VS | (9 - 2));
68 OUT_BATCH(0);
69 OUT_BATCH(0);
70 OUT_BATCH(GEN8_VS_FLOATING_POINT_MODE_ALTERNATE);
71 OUT_BATCH(0);
72 OUT_BATCH(0);
73 OUT_BATCH(0);
74 OUT_BATCH(0);
75 OUT_BATCH(0);
76 }
77
gen8_emit_hs(struct intel_batchbuffer * batch)78 static void gen8_emit_hs(struct intel_batchbuffer *batch)
79 {
80 OUT_BATCH(GEN7_3DSTATE_HS | (9 - 2));
81 OUT_BATCH(0);
82 OUT_BATCH(0);
83 OUT_BATCH(0);
84 OUT_BATCH(0);
85 OUT_BATCH(0);
86 OUT_BATCH(0);
87 OUT_BATCH(1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT);
88 OUT_BATCH(0);
89 }
90
gen8_emit_raster(struct intel_batchbuffer * batch)91 static void gen8_emit_raster(struct intel_batchbuffer *batch)
92 {
93 OUT_BATCH(GEN8_3DSTATE_RASTER | (5 - 2));
94 OUT_BATCH(0);
95 OUT_BATCH(0.0);
96 OUT_BATCH(0.0);
97 OUT_BATCH(0.0);
98 }
99
gen8_emit_urb(struct intel_batchbuffer * batch)100 static void gen8_emit_urb(struct intel_batchbuffer *batch)
101 {
102 const int vs_entries = 64;
103 const int vs_size = 2;
104 const int vs_start = 4;
105
106 OUT_BATCH(GEN7_3DSTATE_URB_VS);
107 OUT_BATCH(vs_entries | ((vs_size - 1) << 16) | (vs_start << 25));
108
109 OUT_BATCH(GEN7_3DSTATE_URB_HS);
110 OUT_BATCH(0x0f << 25);
111
112 OUT_BATCH(GEN7_3DSTATE_URB_DS);
113 OUT_BATCH(0x0f << 25);
114
115 OUT_BATCH(GEN7_3DSTATE_URB_GS);
116 OUT_BATCH(0x0f << 25);
117 }
118
gen8_emit_vf_topology(struct intel_batchbuffer * batch)119 static void gen8_emit_vf_topology(struct intel_batchbuffer *batch)
120 {
121 OUT_BATCH(GEN8_3DSTATE_VF_TOPOLOGY);
122 OUT_BATCH(_3DPRIM_TRILIST);
123 }
124
gen8_emit_so_decl_list(struct intel_batchbuffer * batch)125 static void gen8_emit_so_decl_list(struct intel_batchbuffer *batch)
126 {
127 const int num_decls = 128;
128 int i;
129
130 OUT_BATCH(GEN8_3DSTATE_SO_DECL_LIST |
131 (((2 * num_decls) + 3) - 2) /* DWORD count - 2 */);
132 OUT_BATCH(0);
133 OUT_BATCH(num_decls);
134
135 for (i = 0; i < num_decls; i++) {
136 OUT_BATCH(0);
137 OUT_BATCH(0);
138 }
139 }
140
gen8_emit_so_buffer(struct intel_batchbuffer * batch,const int index)141 static void gen8_emit_so_buffer(struct intel_batchbuffer *batch, const int index)
142 {
143 OUT_BATCH(GEN8_3DSTATE_SO_BUFFER | (8 - 2));
144 OUT_BATCH(index << 29);
145 OUT_BATCH(0);
146 OUT_BATCH(0);
147 OUT_BATCH(0);
148 OUT_BATCH(0);
149 OUT_BATCH(0);
150 OUT_BATCH(0);
151 }
152
gen8_emit_chroma_key(struct intel_batchbuffer * batch,const int index)153 static void gen8_emit_chroma_key(struct intel_batchbuffer *batch, const int index)
154 {
155 OUT_BATCH(GEN6_3DSTATE_CHROMA_KEY | (4 - 2));
156 OUT_BATCH(index << 30);
157 OUT_BATCH(0);
158 OUT_BATCH(0);
159 }
160
gen8_emit_vertex_buffers(struct intel_batchbuffer * batch)161 static void gen8_emit_vertex_buffers(struct intel_batchbuffer *batch)
162 {
163 const int buffers = 33;
164 int i;
165
166 OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS |
167 (((4 * buffers) + 1)- 2) /* DWORD count - 2 */);
168
169 for (i = 0; i < buffers; i++) {
170 OUT_BATCH(i << GEN6_VB0_BUFFER_INDEX_SHIFT |
171 GEN8_VB0_BUFFER_ADDR_MOD_EN);
172 OUT_BATCH(0); /* Address */
173 OUT_BATCH(0);
174 OUT_BATCH(0);
175 }
176 }
177
gen8_emit_vertex_elements(struct intel_batchbuffer * batch)178 static void gen8_emit_vertex_elements(struct intel_batchbuffer *batch)
179 {
180 const int elements = 34;
181 int i;
182
183 OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS |
184 (((2 * elements) + 1) - 2) /* DWORD count - 2 */);
185
186 /* Element 0 */
187 OUT_BATCH(GEN6_VE0_VALID);
188 OUT_BATCH(
189 GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
190 GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
191 GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
192 GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
193 /* Elements 1 -> 33 */
194 for (i = 1; i < elements; i++) {
195 OUT_BATCH(0);
196 OUT_BATCH(0);
197 }
198 }
199
gen8_emit_cc_state_pointers(struct intel_batchbuffer * batch)200 static void gen8_emit_cc_state_pointers(struct intel_batchbuffer *batch)
201 {
202 union {
203 float fval;
204 uint32_t uval;
205 } u;
206
207 unsigned offset;
208
209 u.fval = 1.0f;
210
211 offset = intel_batch_state_offset(batch, 64);
212 OUT_STATE(0);
213 OUT_STATE(0); /* Alpha reference value */
214 OUT_STATE(u.uval); /* Blend constant color RED */
215 OUT_STATE(u.uval); /* Blend constant color BLUE */
216 OUT_STATE(u.uval); /* Blend constant color GREEN */
217 OUT_STATE(u.uval); /* Blend constant color ALPHA */
218
219 OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS);
220 OUT_BATCH_STATE_OFFSET(offset | 1);
221 }
222
gen8_emit_blend_state_pointers(struct intel_batchbuffer * batch)223 static void gen8_emit_blend_state_pointers(struct intel_batchbuffer *batch)
224 {
225 unsigned offset;
226 int i;
227
228 offset = intel_batch_state_offset(batch, 64);
229
230 for (i = 0; i < 17; i++)
231 OUT_STATE(0);
232
233 OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
234 OUT_BATCH_STATE_OFFSET(offset | 1);
235 }
236
gen8_emit_ps_extra(struct intel_batchbuffer * batch)237 static void gen8_emit_ps_extra(struct intel_batchbuffer *batch)
238 {
239 OUT_BATCH(GEN8_3DSTATE_PS_EXTRA | (2 - 2));
240 OUT_BATCH(GEN8_PSX_PIXEL_SHADER_VALID |
241 GEN8_PSX_ATTRIBUTE_ENABLE);
242
243 }
244
gen8_emit_ps_blend(struct intel_batchbuffer * batch)245 static void gen8_emit_ps_blend(struct intel_batchbuffer *batch)
246 {
247 OUT_BATCH(GEN8_3DSTATE_PS_BLEND | (2 - 2));
248 OUT_BATCH(GEN8_PS_BLEND_HAS_WRITEABLE_RT);
249 }
250
gen8_emit_viewport_state_pointers_cc(struct intel_batchbuffer * batch)251 static void gen8_emit_viewport_state_pointers_cc(struct intel_batchbuffer *batch)
252 {
253 unsigned offset;
254
255 offset = intel_batch_state_offset(batch, 32);
256
257 OUT_STATE((uint32_t)0.0f); /* Minimum depth */
258 OUT_STATE((uint32_t)0.0f); /* Maximum depth */
259
260 OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
261 OUT_BATCH_STATE_OFFSET(offset);
262 }
263
gen8_emit_viewport_state_pointers_sf_clip(struct intel_batchbuffer * batch)264 static void gen8_emit_viewport_state_pointers_sf_clip(struct intel_batchbuffer *batch)
265 {
266 unsigned offset;
267 int i;
268
269 offset = intel_batch_state_offset(batch, 64);
270
271 for (i = 0; i < 16; i++)
272 OUT_STATE(0);
273
274 OUT_BATCH(GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP | (2 - 2));
275 OUT_BATCH_STATE_OFFSET(offset);
276 }
277
gen8_emit_primitive(struct intel_batchbuffer * batch)278 static void gen8_emit_primitive(struct intel_batchbuffer *batch)
279 {
280 OUT_BATCH(GEN4_3DPRIMITIVE | (7 - 2));
281 OUT_BATCH(4); /* gen8+ ignore the topology type field */
282 OUT_BATCH(1); /* vertex count */
283 OUT_BATCH(0);
284 OUT_BATCH(1); /* single instance */
285 OUT_BATCH(0); /* start instance location */
286 OUT_BATCH(0); /* index buffer offset, ignored */
287 }
288
gen9_emit_state_base_address(struct intel_batchbuffer * batch)289 static void gen9_emit_state_base_address(struct intel_batchbuffer *batch) {
290 const unsigned offset = 0;
291 OUT_BATCH(GEN4_STATE_BASE_ADDRESS |
292 (19 - 2) /* DWORD count - 2 */);
293
294 /* general state base address - requires BB address
295 * added to state offset to be stored in this location
296 */
297 OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY);
298 OUT_BATCH(0);
299
300 /* stateless data port */
301 OUT_BATCH(0);
302
303 /* surface state base address - requires BB address
304 * added to state offset to be stored in this location
305 */
306 OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY);
307 OUT_BATCH(0);
308
309 /* dynamic state base address - requires BB address
310 * added to state offset to be stored in this location
311 */
312 OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY);
313 OUT_BATCH(0);
314
315 /* indirect state base address */
316 OUT_BATCH(BASE_ADDRESS_MODIFY);
317 OUT_BATCH(0);
318
319 /* instruction state base address - requires BB address
320 * added to state offset to be stored in this location
321 */
322 OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY);
323 OUT_BATCH(0);
324
325 /* general state buffer size */
326 OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY);
327 /* dynamic state buffer size */
328 OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY);
329 /* indirect object buffer size */
330 OUT_BATCH(0x0 | BUFFER_SIZE_MODIFY);
331 /* intruction buffer size */
332 OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY);
333
334 /* bindless surface state base address */
335 OUT_BATCH(0);
336 OUT_BATCH(0);
337 /* bindless surface state size */
338 OUT_BATCH(0);
339 }
340
341 /*
342 * Generate the batch buffer commands needed to initialize the 3D engine
343 * to its "golden state".
344 */
gen9_setup_null_render_state(struct intel_batchbuffer * batch)345 void gen9_setup_null_render_state(struct intel_batchbuffer *batch)
346 {
347 int i;
348
349 #define GEN8_PIPE_CONTROL_GLOBAL_GTT (1 << 24)
350 /* PIPE_CONTROL */
351 OUT_BATCH(GEN6_PIPE_CONTROL |
352 (6 - 2)); /* DWORD count - 2 */
353 OUT_BATCH(GEN8_PIPE_CONTROL_GLOBAL_GTT);
354 OUT_BATCH(0);
355 OUT_BATCH(0);
356 OUT_BATCH(0);
357 OUT_BATCH(0);
358
359 /* PIPELINE_SELECT */
360 OUT_BATCH(GEN9_PIPELINE_SELECT | PIPELINE_SELECT_3D);
361
362 gen8_emit_wm(batch);
363 gen8_emit_ps(batch);
364 gen8_emit_sf(batch);
365
366 OUT_CMD(GEN7_3DSTATE_SBE, 6); /* Check w/ Gen8 code */
367 OUT_CMD(GEN8_3DSTATE_SBE_SWIZ, 11);
368
369 gen8_emit_vs(batch);
370 gen8_emit_hs(batch);
371
372 OUT_CMD(GEN6_3DSTATE_GS, 10);
373 OUT_CMD(GEN7_3DSTATE_STREAMOUT, 5);
374 OUT_CMD(GEN7_3DSTATE_DS, 11); /* Check w/ Gen8 code */
375 OUT_CMD(GEN6_3DSTATE_CLIP, 4);
376 gen8_emit_raster(batch);
377 OUT_CMD(GEN7_3DSTATE_TE, 4);
378 OUT_CMD(GEN8_3DSTATE_VF, 2);
379 OUT_CMD(GEN8_3DSTATE_WM_HZ_OP, 5);
380
381 /* URB States */
382 gen8_emit_urb(batch);
383
384 OUT_CMD(GEN8_3DSTATE_BIND_TABLE_POOL_ALLOC, 4);
385 OUT_CMD(GEN8_3DSTATE_GATHER_POOL_ALLOC, 4);
386 OUT_CMD(GEN8_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC, 4);
387
388 /* Push Constants */
389 OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS, 2);
390 OUT_CMD(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS, 2);
391 OUT_CMD(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS, 2);
392 OUT_CMD(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS, 2);
393 OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS, 2);
394
395 /* Constants */
396 OUT_CMD(GEN6_3DSTATE_CONSTANT_VS, 11);
397 OUT_CMD(GEN7_3DSTATE_CONSTANT_HS, 11);
398 OUT_CMD(GEN7_3DSTATE_CONSTANT_DS, 11);
399 OUT_CMD(GEN6_3DSTATE_CONSTANT_GS, 11);
400 OUT_CMD(GEN6_3DSTATE_CONSTANT_PS, 11);
401
402 OUT_CMD(GEN8_3DSTATE_VF_INSTANCING, 3);
403 OUT_CMD(GEN8_3DSTATE_VF_SGVS, 2);
404 gen8_emit_vf_topology(batch);
405
406 /* Streamer out declaration list */
407 gen8_emit_so_decl_list(batch);
408
409 /* Streamer out buffers */
410 for (i = 0; i < 4; i++) {
411 gen8_emit_so_buffer(batch, i);
412 }
413
414 /* State base addresses */
415 gen9_emit_state_base_address(batch);
416
417 OUT_CMD(GEN4_STATE_SIP, 3);
418 OUT_CMD(GEN4_3DSTATE_DRAWING_RECTANGLE, 4);
419 OUT_CMD(GEN7_3DSTATE_DEPTH_BUFFER, 8);
420
421 /* Chroma key */
422 for (i = 0; i < 4; i++) {
423 gen8_emit_chroma_key(batch, i);
424 }
425
426 OUT_CMD(GEN6_3DSTATE_LINE_STIPPLE, 3);
427 OUT_CMD(GEN6_3DSTATE_AA_LINE_PARAMS, 3);
428 OUT_CMD(GEN8_3DSTATE_STENCIL_BUFFER, 5);
429 OUT_CMD(GEN8_3DSTATE_HIER_DEPTH_BUFFER, 5);
430 OUT_CMD(GEN7_3DSTATE_CLEAR_PARAMS, 3);
431 OUT_CMD(GEN6_3DSTATE_MONOFILTER_SIZE, 2);
432 OUT_CMD(GEN8_3DSTATE_MULTISAMPLE, 2);
433 OUT_CMD(GEN6_3DSTATE_POLY_STIPPLE_OFFSET, 2);
434 OUT_CMD(GEN6_3DSTATE_POLY_STIPPLE_PATTERN, 1 + 32);
435 OUT_CMD(GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0, 1 + 16);
436 OUT_CMD(GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1, 1 + 16);
437 OUT_CMD(GEN6_3DSTATE_INDEX_BUFFER, 5);
438
439 /* Vertex buffers */
440 gen8_emit_vertex_buffers(batch);
441 gen8_emit_vertex_elements(batch);
442
443 OUT_BATCH(GEN9_3DSTATE_COMPONENT_PACKING | 3);
444 OUT_BATCH(0xf);
445 OUT_BATCH(0);
446 OUT_BATCH(0);
447 OUT_BATCH(0);
448
449 OUT_BATCH(GEN6_3DSTATE_VF_STATISTICS | 1 /* Enable */);
450
451 gen8_emit_cc_state_pointers(batch);
452 gen8_emit_blend_state_pointers(batch);
453 gen8_emit_ps_extra(batch);
454 gen8_emit_ps_blend(batch);
455
456 /* 3D state sampler state pointers */
457 OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS, 2);
458 OUT_CMD(GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS, 2);
459 OUT_CMD(GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS, 2);
460 OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS, 2);
461 OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS, 2);
462
463 OUT_CMD(GEN8_3DSTATE_SCISSOR_STATE_POINTERS, 2);
464
465 gen8_emit_viewport_state_pointers_cc(batch);
466 gen8_emit_viewport_state_pointers_sf_clip(batch);
467
468 /* 3D state binding table pointers */
469 OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS, 2);
470 OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS, 2);
471 OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS, 2);
472 OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS, 2);
473 OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS, 2);
474
475 /* Launch 3D operation */
476 gen8_emit_primitive(batch);
477
478 OUT_BATCH(MI_BATCH_BUFFER_END);
479 }
480