1 /*
2 * Copyright (c) 2017, Alliance for Open Media. All rights reserved
3 *
4 * This source code is subject to the terms of the BSD 2 Clause License and
5 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6 * was not distributed with this source code in the LICENSE file, you can
7 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
8 * Media Patent License 1.0 was not distributed with this source code in the
9 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
10 */
11
12 #ifndef AOM_AOM_DSP_X86_OBMC_INTRINSIC_SSSE3_H_
13 #define AOM_AOM_DSP_X86_OBMC_INTRINSIC_SSSE3_H_
14
15 #include <immintrin.h>
16
17 #include "config/aom_config.h"
18
xx_hsum_epi32_si32(__m128i v_d)19 static INLINE int32_t xx_hsum_epi32_si32(__m128i v_d) {
20 v_d = _mm_hadd_epi32(v_d, v_d);
21 v_d = _mm_hadd_epi32(v_d, v_d);
22 return _mm_cvtsi128_si32(v_d);
23 }
24
xx_hsum_epi64_si64(__m128i v_q)25 static INLINE int64_t xx_hsum_epi64_si64(__m128i v_q) {
26 v_q = _mm_add_epi64(v_q, _mm_srli_si128(v_q, 8));
27 #if ARCH_X86_64
28 return _mm_cvtsi128_si64(v_q);
29 #else
30 {
31 int64_t tmp;
32 _mm_storel_epi64((__m128i *)&tmp, v_q);
33 return tmp;
34 }
35 #endif
36 }
37
xx_hsum_epi32_si64(__m128i v_d)38 static INLINE int64_t xx_hsum_epi32_si64(__m128i v_d) {
39 const __m128i v_sign_d = _mm_cmplt_epi32(v_d, _mm_setzero_si128());
40 const __m128i v_0_q = _mm_unpacklo_epi32(v_d, v_sign_d);
41 const __m128i v_1_q = _mm_unpackhi_epi32(v_d, v_sign_d);
42 return xx_hsum_epi64_si64(_mm_add_epi64(v_0_q, v_1_q));
43 }
44
45 // This is equivalent to ROUND_POWER_OF_TWO_SIGNED(v_val_d, bits)
xx_roundn_epi32(__m128i v_val_d,int bits)46 static INLINE __m128i xx_roundn_epi32(__m128i v_val_d, int bits) {
47 const __m128i v_bias_d = _mm_set1_epi32((1 << bits) >> 1);
48 const __m128i v_sign_d = _mm_srai_epi32(v_val_d, 31);
49 const __m128i v_tmp_d =
50 _mm_add_epi32(_mm_add_epi32(v_val_d, v_bias_d), v_sign_d);
51 return _mm_srai_epi32(v_tmp_d, bits);
52 }
53
54 #endif // AOM_AOM_DSP_X86_OBMC_INTRINSIC_SSSE3_H_
55