1//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the MIPS register file 12//===----------------------------------------------------------------------===// 13let Namespace = "Mips" in { 14def sub_32 : SubRegIndex<32>; 15def sub_64 : SubRegIndex<64>; 16def sub_lo : SubRegIndex<32>; 17def sub_hi : SubRegIndex<32, 32>; 18def sub_dsp16_19 : SubRegIndex<4, 16>; 19def sub_dsp20 : SubRegIndex<1, 20>; 20def sub_dsp21 : SubRegIndex<1, 21>; 21def sub_dsp22 : SubRegIndex<1, 22>; 22def sub_dsp23 : SubRegIndex<1, 23>; 23} 24 25class Unallocatable { 26 bit isAllocatable = 0; 27} 28 29// We have banks of 32 registers each. 30class MipsReg<bits<16> Enc, string n> : Register<n> { 31 let HWEncoding = Enc; 32 let Namespace = "Mips"; 33} 34 35class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs> 36 : RegisterWithSubRegs<n, subregs> { 37 let HWEncoding = Enc; 38 let Namespace = "Mips"; 39} 40 41// Mips CPU Registers 42class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>; 43 44// Mips 64-bit CPU Registers 45class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs> 46 : MipsRegWithSubRegs<Enc, n, subregs> { 47 let SubRegIndices = [sub_32]; 48} 49 50// Mips 32-bit FPU Registers 51class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>; 52 53// Mips 64-bit (aliased) FPU Registers 54class AFPR<bits<16> Enc, string n, list<Register> subregs> 55 : MipsRegWithSubRegs<Enc, n, subregs> { 56 let SubRegIndices = [sub_lo, sub_hi]; 57 let CoveredBySubRegs = 1; 58} 59 60class AFPR64<bits<16> Enc, string n, list<Register> subregs> 61 : MipsRegWithSubRegs<Enc, n, subregs> { 62 let SubRegIndices = [sub_lo, sub_hi]; 63 let CoveredBySubRegs = 1; 64} 65 66// Mips 128-bit (aliased) MSA Registers 67class AFPR128<bits<16> Enc, string n, list<Register> subregs> 68 : MipsRegWithSubRegs<Enc, n, subregs> { 69 let SubRegIndices = [sub_64]; 70} 71 72// Accumulator Registers 73class ACCReg<bits<16> Enc, string n, list<Register> subregs> 74 : MipsRegWithSubRegs<Enc, n, subregs> { 75 let SubRegIndices = [sub_lo, sub_hi]; 76 let CoveredBySubRegs = 1; 77} 78 79// Mips Hardware Registers 80class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>; 81 82//===----------------------------------------------------------------------===// 83// Registers 84//===----------------------------------------------------------------------===// 85 86let Namespace = "Mips" in { 87 // General Purpose Registers 88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 89 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; 90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 91 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 92 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 93 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 94 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 95 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 96 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 97 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 98 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 99 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 100 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 101 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 102 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 103 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 104 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 105 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 106 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 107 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 108 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 109 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 110 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 111 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 112 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 113 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 114 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 115 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 116 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 117 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 118 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 119 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 120 121 // General Purpose 64-bit Registers 122 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 123 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; 124 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 125 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 126 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 127 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 128 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 129 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 130 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 131 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 132 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 133 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 134 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 135 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 136 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 137 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 138 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 139 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 140 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 141 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 142 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 143 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 144 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 145 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 146 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 147 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 148 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 149 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 150 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 151 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 152 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 153 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 154 155 /// Mips Single point precision FPU Registers 156 foreach I = 0-31 in 157 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 158 159 // Higher half of 64-bit FP registers. 160 foreach I = 0-31 in 161 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 162 163 /// Mips Double point precision FPU Registers (aliased 164 /// with the single precision to hold 64 bit values) 165 foreach I = 0-15 in 166 def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1), 167 [!cast<FPR>("F"#!shl(I, 1)), 168 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>; 169 170 /// Mips Double point precision FPU Registers in MFP64 mode. 171 foreach I = 0-31 in 172 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>, 173 DwarfRegNum<[!add(I, 32)]>; 174 175 /// Mips MSA registers 176 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers 177 foreach I = 0-31 in 178 def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>, 179 DwarfRegNum<[!add(I, 32)]>; 180 181 // Hi/Lo registers 182 def HI0 : MipsReg<0, "ac0">, DwarfRegNum<[64]>; 183 def HI1 : MipsReg<1, "ac1">, DwarfRegNum<[176]>; 184 def HI2 : MipsReg<2, "ac2">, DwarfRegNum<[178]>; 185 def HI3 : MipsReg<3, "ac3">, DwarfRegNum<[180]>; 186 def LO0 : MipsReg<0, "ac0">, DwarfRegNum<[65]>; 187 def LO1 : MipsReg<1, "ac1">, DwarfRegNum<[177]>; 188 def LO2 : MipsReg<2, "ac2">, DwarfRegNum<[179]>; 189 def LO3 : MipsReg<3, "ac3">, DwarfRegNum<[181]>; 190 191 let SubRegIndices = [sub_32] in { 192 def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>; 193 def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>; 194 } 195 196 // FP control registers. 197 foreach I = 0-31 in 198 def FCR#I : MipsReg<#I, ""#I>; 199 200 // FP condition code registers. 201 foreach I = 0-7 in 202 def FCC#I : MipsReg<#I, "fcc"#I>; 203 204 // COP0 registers. 205 foreach I = 0-31 in 206 def COP0#I : MipsReg<#I, ""#I>; 207 208 // COP2 registers. 209 foreach I = 0-31 in 210 def COP2#I : MipsReg<#I, ""#I>; 211 212 // COP3 registers. 213 foreach I = 0-31 in 214 def COP3#I : MipsReg<#I, ""#I>; 215 216 // PC register 217 def PC : Register<"pc">; 218 219 // Hardware registers 220 def HWR0 : MipsReg<0, "hwr_cpunum">; 221 def HWR1 : MipsReg<1, "hwr_synci_step">; 222 def HWR2 : MipsReg<2, "hwr_cc">; 223 def HWR3 : MipsReg<3, "hwr_ccres">; 224 225 foreach I = 4-31 in 226 def HWR#I : MipsReg<#I, ""#I>; 227 228 // Accum registers 229 foreach I = 0-3 in 230 def AC#I : ACCReg<#I, "ac"#I, 231 [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>; 232 233 def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>; 234 235 // DSP-ASE control register fields. 236 def DSPPos : Register<"">; 237 def DSPSCount : Register<"">; 238 def DSPCarry : Register<"">; 239 def DSPEFI : Register<"">; 240 def DSPOutFlag16_19 : Register<"">; 241 def DSPOutFlag20 : Register<"">; 242 def DSPOutFlag21 : Register<"">; 243 def DSPOutFlag22 : Register<"">; 244 def DSPOutFlag23 : Register<"">; 245 def DSPCCond : Register<"">; 246 247 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22, 248 sub_dsp23] in 249 def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, 250 DSPOutFlag21, DSPOutFlag22, 251 DSPOutFlag23]>; 252 253 // MSA-ASE control registers. 254 def MSAIR : MipsReg<0, "0">; 255 def MSACSR : MipsReg<1, "1">; 256 def MSAAccess : MipsReg<2, "2">; 257 def MSASave : MipsReg<3, "3">; 258 def MSAModify : MipsReg<4, "4">; 259 def MSARequest : MipsReg<5, "5">; 260 def MSAMap : MipsReg<6, "6">; 261 def MSAUnmap : MipsReg<7, "7">; 262 263 // Octeon multiplier and product registers 264 def MPL0 : MipsReg<0, "mpl0">; 265 def MPL1 : MipsReg<1, "mpl1">; 266 def MPL2 : MipsReg<2, "mpl2">; 267 def P0 : MipsReg<0, "p0">; 268 def P1 : MipsReg<1, "p1">; 269 def P2 : MipsReg<2, "p2">; 270 271} 272 273//===----------------------------------------------------------------------===// 274// Register Classes 275//===----------------------------------------------------------------------===// 276 277class GPR32Class<list<ValueType> regTypes> : 278 RegisterClass<"Mips", regTypes, 32, (add 279 // Reserved 280 ZERO, AT, 281 // Return Values and Arguments 282 V0, V1, A0, A1, A2, A3, 283 // Not preserved across procedure calls 284 T0, T1, T2, T3, T4, T5, T6, T7, 285 // Callee save 286 S0, S1, S2, S3, S4, S5, S6, S7, 287 // Not preserved across procedure calls 288 T8, T9, 289 // Reserved 290 K0, K1, GP, SP, FP, RA)>; 291 292def GPR32 : GPR32Class<[i32]>; 293def DSPR : GPR32Class<[v4i8, v2i16]>; 294 295def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add 296 // Callee save 297 S0, S1, 298 // Return Values and Arguments 299 V0, V1, A0, A1, A2, A3)>; 300 301def GPRMM16Zero : RegisterClass<"Mips", [i32], 32, (add 302 // Reserved 303 ZERO, 304 // Callee save 305 S1, 306 // Return Values and Arguments 307 V0, V1, A0, A1, A2, A3)>; 308 309def GPRMM16MoveP : RegisterClass<"Mips", [i32], 32, (add 310 // Reserved 311 ZERO, 312 // Callee save 313 S1, 314 // Return Values and Arguments 315 V0, V1, 316 // Callee save 317 S0, S2, S3, S4)>; 318 319def GPR64 : RegisterClass<"Mips", [i64], 64, (add 320// Reserved 321 ZERO_64, AT_64, 322 // Return Values and Arguments 323 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 324 // Not preserved across procedure calls 325 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 326 // Callee save 327 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 328 // Not preserved across procedure calls 329 T8_64, T9_64, 330 // Reserved 331 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 332 333def GPRMM16_64 : RegisterClass<"Mips", [i64], 64, (add 334 // Callee save 335 S0_64, S1_64, 336 // Return Values and Arguments 337 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64)>; 338 339def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 340 // Return Values and Arguments 341 V0, V1, A0, A1, A2, A3, 342 // Callee save 343 S0, S1)>; 344 345def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add 346 // Return Values and Arguments 347 V0, V1, A0, A1, A2, A3, 348 // Callee save 349 S0, S1, 350 SP)>; 351 352def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable; 353 354def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; 355 356// 64bit fp: 357// * FGR64 - 32 64-bit registers 358// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 359// 360// 32bit fp: 361// * FGR32 - 16 32-bit even registers 362// * FGR32 - 32 32-bit registers (single float only mode) 363def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 364 365def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>, 366 Unallocatable; 367 368def AFGR64 : RegisterClass<"Mips", [f64], 64, (add 369 // Return Values and Arguments 370 D0, D1, 371 // Not preserved across procedure calls 372 D2, D3, D4, D5, 373 // Return Values and Arguments 374 D6, D7, 375 // Not preserved across procedure calls 376 D8, D9, 377 // Callee save 378 D10, D11, D12, D13, D14, D15)>; 379 380def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 381 382// Used to reserve odd registers when given -mattr=+nooddspreg 383// FIXME: Remove double precision registers from this set. 384def OddSP : RegisterClass<"Mips", [f32], 32, 385 (add (decimate (sequence "F%u", 1, 31), 2), 386 (decimate (sequence "F_HI%u", 1, 31), 2), 387 (decimate (sequence "D%u", 1, 15), 2), 388 (decimate (sequence "D%u_64", 1, 31), 2))>, 389 Unallocatable; 390 391// FP control registers. 392def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, 393 Unallocatable; 394 395// FP condition code registers. 396def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, 397 Unallocatable; 398 399// MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers. 400// This class allows us to represent this in codegen patterns. 401def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>; 402 403def MSA128B: RegisterClass<"Mips", [v16i8], 128, 404 (sequence "W%u", 0, 31)>; 405def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128, 406 (sequence "W%u", 0, 31)>; 407def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128, 408 (sequence "W%u", 0, 31)>; 409def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128, 410 (sequence "W%u", 0, 31)>; 411def MSA128WEvens: RegisterClass<"Mips", [v4i32, v4f32], 128, 412 (decimate (sequence "W%u", 0, 31), 2)>; 413 414def MSACtrl: RegisterClass<"Mips", [i32], 32, (add 415 MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>; 416 417// Hi/Lo Registers 418def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>; 419def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>; 420def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>; 421def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>; 422def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>; 423def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>; 424 425// Hardware registers 426def HWRegs : RegisterClass<"Mips", [i32], 32, (sequence "HWR%u", 0, 31)>, 427 Unallocatable; 428 429// Accumulator Registers 430def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> { 431 let Size = 64; 432} 433 434def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> { 435 let Size = 128; 436} 437 438def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { 439 let Size = 64; 440} 441 442def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; 443 444// Coprocessor 0 registers. 445def COP0 : RegisterClass<"Mips", [i32], 32, (sequence "COP0%u", 0, 31)>, 446 Unallocatable; 447 448// Coprocessor 2 registers. 449def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>, 450 Unallocatable; 451 452// Coprocessor 3 registers. 453def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>, 454 Unallocatable; 455 456// Stack pointer and global pointer classes for instructions that are limited 457// to a single register such as lwgp/lwsp in microMIPS. 458def SP32 : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; 459def SP64 : RegisterClass<"Mips", [i64], 64, (add SP_64)>, Unallocatable; 460def GP32 : RegisterClass<"Mips", [i32], 32, (add GP)>, Unallocatable; 461def GP64 : RegisterClass<"Mips", [i64], 64, (add GP_64)>, Unallocatable; 462 463// Octeon multiplier and product registers 464def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>, 465 Unallocatable; 466def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>, 467 Unallocatable; 468 469// Register Operands. 470 471class MipsAsmRegOperand : AsmOperandClass { 472 let ParserMethod = "parseAnyRegister"; 473} 474 475def GPR64AsmOperand : MipsAsmRegOperand { 476 let Name = "GPR64AsmReg"; 477 let PredicateMethod = "isGPRAsmReg"; 478} 479 480def GPR32AsmOperand : MipsAsmRegOperand { 481 let Name = "GPR32AsmReg"; 482 let PredicateMethod = "isGPRAsmReg"; 483} 484 485def GPRMM16AsmOperand : MipsAsmRegOperand { 486 let Name = "GPRMM16AsmReg"; 487 let PredicateMethod = "isMM16AsmReg"; 488} 489 490def GPRMM16AsmOperandZero : MipsAsmRegOperand { 491 let Name = "GPRMM16AsmRegZero"; 492 let PredicateMethod = "isMM16AsmRegZero"; 493} 494 495def GPRMM16AsmOperandMoveP : MipsAsmRegOperand { 496 let Name = "GPRMM16AsmRegMoveP"; 497 let PredicateMethod = "isMM16AsmRegMoveP"; 498} 499 500def ACC64DSPAsmOperand : MipsAsmRegOperand { 501 let Name = "ACC64DSPAsmReg"; 502 let PredicateMethod = "isACCAsmReg"; 503} 504 505def HI32DSPAsmOperand : MipsAsmRegOperand { 506 let Name = "HI32DSPAsmReg"; 507 let PredicateMethod = "isACCAsmReg"; 508} 509 510def LO32DSPAsmOperand : MipsAsmRegOperand { 511 let Name = "LO32DSPAsmReg"; 512 let PredicateMethod = "isACCAsmReg"; 513} 514 515def CCRAsmOperand : MipsAsmRegOperand { 516 let Name = "CCRAsmReg"; 517} 518 519def AFGR64AsmOperand : MipsAsmRegOperand { 520 let Name = "AFGR64AsmReg"; 521 let PredicateMethod = "isFGRAsmReg"; 522} 523 524def FGR64AsmOperand : MipsAsmRegOperand { 525 let Name = "FGR64AsmReg"; 526 let PredicateMethod = "isFGRAsmReg"; 527} 528 529def FGR32AsmOperand : MipsAsmRegOperand { 530 let Name = "FGR32AsmReg"; 531 let PredicateMethod = "isFGRAsmReg"; 532} 533 534def FGRH32AsmOperand : MipsAsmRegOperand { 535 let Name = "FGRH32AsmReg"; 536 let PredicateMethod = "isFGRAsmReg"; 537} 538 539def FCCRegsAsmOperand : MipsAsmRegOperand { 540 let Name = "FCCAsmReg"; 541} 542 543def MSA128AsmOperand : MipsAsmRegOperand { 544 let Name = "MSA128AsmReg"; 545} 546 547def MSACtrlAsmOperand : MipsAsmRegOperand { 548 let Name = "MSACtrlAsmReg"; 549} 550 551def GPR32Opnd : RegisterOperand<GPR32> { 552 let ParserMatchClass = GPR32AsmOperand; 553} 554 555def GPRMM16Opnd : RegisterOperand<GPRMM16> { 556 let ParserMatchClass = GPRMM16AsmOperand; 557} 558 559def GPRMM16OpndZero : RegisterOperand<GPRMM16Zero> { 560 let ParserMatchClass = GPRMM16AsmOperandZero; 561} 562 563def GPRMM16OpndMoveP : RegisterOperand<GPRMM16MoveP> { 564 let ParserMatchClass = GPRMM16AsmOperandMoveP; 565} 566 567def GPR64Opnd : RegisterOperand<GPR64> { 568 let ParserMatchClass = GPR64AsmOperand; 569} 570 571def DSPROpnd : RegisterOperand<DSPR> { 572 let ParserMatchClass = GPR32AsmOperand; 573} 574 575def CCROpnd : RegisterOperand<CCR> { 576 let ParserMatchClass = CCRAsmOperand; 577} 578 579def HWRegsAsmOperand : MipsAsmRegOperand { 580 let Name = "HWRegsAsmReg"; 581} 582 583def COP0AsmOperand : MipsAsmRegOperand { 584 let Name = "COP0AsmReg"; 585} 586 587def COP2AsmOperand : MipsAsmRegOperand { 588 let Name = "COP2AsmReg"; 589} 590 591def COP3AsmOperand : MipsAsmRegOperand { 592 let Name = "COP3AsmReg"; 593} 594 595def HWRegsOpnd : RegisterOperand<HWRegs> { 596 let ParserMatchClass = HWRegsAsmOperand; 597} 598 599def AFGR64Opnd : RegisterOperand<AFGR64> { 600 let ParserMatchClass = AFGR64AsmOperand; 601} 602 603def FGR64Opnd : RegisterOperand<FGR64> { 604 let ParserMatchClass = FGR64AsmOperand; 605} 606 607def FGR32Opnd : RegisterOperand<FGR32> { 608 let ParserMatchClass = FGR32AsmOperand; 609} 610 611def FGRCCOpnd : RegisterOperand<FGRCC> { 612 // The assembler doesn't use register classes so we can re-use 613 // FGR32AsmOperand. 614 let ParserMatchClass = FGR32AsmOperand; 615} 616 617def FGRH32Opnd : RegisterOperand<FGRH32> { 618 let ParserMatchClass = FGRH32AsmOperand; 619} 620 621def FCCRegsOpnd : RegisterOperand<FCC> { 622 let ParserMatchClass = FCCRegsAsmOperand; 623} 624 625def LO32DSPOpnd : RegisterOperand<LO32DSP> { 626 let ParserMatchClass = LO32DSPAsmOperand; 627} 628 629def HI32DSPOpnd : RegisterOperand<HI32DSP> { 630 let ParserMatchClass = HI32DSPAsmOperand; 631} 632 633def ACC64DSPOpnd : RegisterOperand<ACC64DSP> { 634 let ParserMatchClass = ACC64DSPAsmOperand; 635} 636 637def COP0Opnd : RegisterOperand<COP0> { 638 let ParserMatchClass = COP0AsmOperand; 639} 640 641def COP2Opnd : RegisterOperand<COP2> { 642 let ParserMatchClass = COP2AsmOperand; 643} 644 645def COP3Opnd : RegisterOperand<COP3> { 646 let ParserMatchClass = COP3AsmOperand; 647} 648 649def MSA128BOpnd : RegisterOperand<MSA128B> { 650 let ParserMatchClass = MSA128AsmOperand; 651} 652 653def MSA128HOpnd : RegisterOperand<MSA128H> { 654 let ParserMatchClass = MSA128AsmOperand; 655} 656 657def MSA128WOpnd : RegisterOperand<MSA128W> { 658 let ParserMatchClass = MSA128AsmOperand; 659} 660 661def MSA128DOpnd : RegisterOperand<MSA128D> { 662 let ParserMatchClass = MSA128AsmOperand; 663} 664 665def MSA128CROpnd : RegisterOperand<MSACtrl> { 666 let ParserMatchClass = MSACtrlAsmOperand; 667} 668