1//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9/// 10/// \file 11/// \brief This is a target description file for the WebAssembly architecture, 12/// which is also known as "wasm". 13/// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// Target-independent interfaces which we are implementing 18//===----------------------------------------------------------------------===// 19 20include "llvm/Target/Target.td" 21 22//===----------------------------------------------------------------------===// 23// WebAssembly Subtarget features. 24//===----------------------------------------------------------------------===// 25 26def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false", 27 "Enable 128-bit SIMD">; 28 29//===----------------------------------------------------------------------===// 30// Architectures. 31//===----------------------------------------------------------------------===// 32 33//===----------------------------------------------------------------------===// 34// Register File Description 35//===----------------------------------------------------------------------===// 36 37include "WebAssemblyRegisterInfo.td" 38 39//===----------------------------------------------------------------------===// 40// Instruction Descriptions 41//===----------------------------------------------------------------------===// 42 43include "WebAssemblyInstrInfo.td" 44 45def WebAssemblyInstrInfo : InstrInfo; 46 47//===----------------------------------------------------------------------===// 48// WebAssembly Processors supported. 49//===----------------------------------------------------------------------===// 50 51// Minimal Viable Product. 52def : ProcessorModel<"mvp", NoSchedModel, []>; 53 54// Generic processor: latest stable version. 55def : ProcessorModel<"generic", NoSchedModel, []>; 56 57// Latest and greatest experimental version of WebAssembly. Bugs included! 58def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>; 59 60//===----------------------------------------------------------------------===// 61// Target Declaration 62//===----------------------------------------------------------------------===// 63 64def WebAssembly : Target { 65 let InstructionSet = WebAssemblyInstrInfo; 66} 67