1; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s 2 3define <8 x i8> @cmeq8xi8(<8 x i8> %A, <8 x i8> %B) { 4; CHECK-LABEL: cmeq8xi8: 5; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 6 %tmp3 = icmp eq <8 x i8> %A, %B; 7 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 8 ret <8 x i8> %tmp4 9} 10 11define <16 x i8> @cmeq16xi8(<16 x i8> %A, <16 x i8> %B) { 12; CHECK-LABEL: cmeq16xi8: 13; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 14 %tmp3 = icmp eq <16 x i8> %A, %B; 15 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 16 ret <16 x i8> %tmp4 17} 18 19define <4 x i16> @cmeq4xi16(<4 x i16> %A, <4 x i16> %B) { 20; CHECK-LABEL: cmeq4xi16: 21; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 22 %tmp3 = icmp eq <4 x i16> %A, %B; 23 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 24 ret <4 x i16> %tmp4 25} 26 27define <8 x i16> @cmeq8xi16(<8 x i16> %A, <8 x i16> %B) { 28; CHECK-LABEL: cmeq8xi16: 29; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 30 %tmp3 = icmp eq <8 x i16> %A, %B; 31 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 32 ret <8 x i16> %tmp4 33} 34 35define <2 x i32> @cmeq2xi32(<2 x i32> %A, <2 x i32> %B) { 36; CHECK-LABEL: cmeq2xi32: 37; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 38 %tmp3 = icmp eq <2 x i32> %A, %B; 39 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 40 ret <2 x i32> %tmp4 41} 42 43define <4 x i32> @cmeq4xi32(<4 x i32> %A, <4 x i32> %B) { 44; CHECK-LABEL: cmeq4xi32: 45; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 46 %tmp3 = icmp eq <4 x i32> %A, %B; 47 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 48 ret <4 x i32> %tmp4 49} 50 51define <2 x i64> @cmeq2xi64(<2 x i64> %A, <2 x i64> %B) { 52; CHECK-LABEL: cmeq2xi64: 53; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 54 %tmp3 = icmp eq <2 x i64> %A, %B; 55 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 56 ret <2 x i64> %tmp4 57} 58 59define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) { 60; CHECK-LABEL: cmne8xi8: 61; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 62; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 63 %tmp3 = icmp ne <8 x i8> %A, %B; 64 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 65 ret <8 x i8> %tmp4 66} 67 68define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) { 69; CHECK-LABEL: cmne16xi8: 70; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 71; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 72 %tmp3 = icmp ne <16 x i8> %A, %B; 73 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 74 ret <16 x i8> %tmp4 75} 76 77define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) { 78; CHECK-LABEL: cmne4xi16: 79; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 80; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 81 %tmp3 = icmp ne <4 x i16> %A, %B; 82 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 83 ret <4 x i16> %tmp4 84} 85 86define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) { 87; CHECK-LABEL: cmne8xi16: 88; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 89; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 90 %tmp3 = icmp ne <8 x i16> %A, %B; 91 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 92 ret <8 x i16> %tmp4 93} 94 95define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) { 96; CHECK-LABEL: cmne2xi32: 97; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 98; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 99 %tmp3 = icmp ne <2 x i32> %A, %B; 100 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 101 ret <2 x i32> %tmp4 102} 103 104define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) { 105; CHECK-LABEL: cmne4xi32: 106; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 107; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 108 %tmp3 = icmp ne <4 x i32> %A, %B; 109 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 110 ret <4 x i32> %tmp4 111} 112 113define <2 x i64> @cmne2xi64(<2 x i64> %A, <2 x i64> %B) { 114; CHECK-LABEL: cmne2xi64: 115; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 116; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 117 %tmp3 = icmp ne <2 x i64> %A, %B; 118 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 119 ret <2 x i64> %tmp4 120} 121 122define <8 x i8> @cmgt8xi8(<8 x i8> %A, <8 x i8> %B) { 123; CHECK-LABEL: cmgt8xi8: 124; CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 125 %tmp3 = icmp sgt <8 x i8> %A, %B; 126 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 127 ret <8 x i8> %tmp4 128} 129 130define <16 x i8> @cmgt16xi8(<16 x i8> %A, <16 x i8> %B) { 131; CHECK-LABEL: cmgt16xi8: 132; CHECK: cmgt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 133 %tmp3 = icmp sgt <16 x i8> %A, %B; 134 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 135 ret <16 x i8> %tmp4 136} 137 138define <4 x i16> @cmgt4xi16(<4 x i16> %A, <4 x i16> %B) { 139; CHECK-LABEL: cmgt4xi16: 140; CHECK: cmgt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 141 %tmp3 = icmp sgt <4 x i16> %A, %B; 142 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 143 ret <4 x i16> %tmp4 144} 145 146define <8 x i16> @cmgt8xi16(<8 x i16> %A, <8 x i16> %B) { 147; CHECK-LABEL: cmgt8xi16: 148; CHECK: cmgt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 149 %tmp3 = icmp sgt <8 x i16> %A, %B; 150 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 151 ret <8 x i16> %tmp4 152} 153 154define <2 x i32> @cmgt2xi32(<2 x i32> %A, <2 x i32> %B) { 155; CHECK-LABEL: cmgt2xi32: 156; CHECK: cmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 157 %tmp3 = icmp sgt <2 x i32> %A, %B; 158 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 159 ret <2 x i32> %tmp4 160} 161 162define <4 x i32> @cmgt4xi32(<4 x i32> %A, <4 x i32> %B) { 163; CHECK-LABEL: cmgt4xi32: 164; CHECK: cmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 165 %tmp3 = icmp sgt <4 x i32> %A, %B; 166 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 167 ret <4 x i32> %tmp4 168} 169 170define <2 x i64> @cmgt2xi64(<2 x i64> %A, <2 x i64> %B) { 171; CHECK-LABEL: cmgt2xi64: 172; CHECK: cmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 173 %tmp3 = icmp sgt <2 x i64> %A, %B; 174 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 175 ret <2 x i64> %tmp4 176} 177 178define <8 x i8> @cmlt8xi8(<8 x i8> %A, <8 x i8> %B) { 179; CHECK-LABEL: cmlt8xi8: 180; Using registers other than v0, v1 are possible, but would be odd. 181; LT implemented as GT, so check reversed operands. 182; CHECK: cmgt {{v[0-9]+}}.8b, v1.8b, v0.8b 183 %tmp3 = icmp slt <8 x i8> %A, %B; 184 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 185 ret <8 x i8> %tmp4 186} 187 188define <16 x i8> @cmlt16xi8(<16 x i8> %A, <16 x i8> %B) { 189; CHECK-LABEL: cmlt16xi8: 190; Using registers other than v0, v1 are possible, but would be odd. 191; LT implemented as GT, so check reversed operands. 192; CHECK: cmgt {{v[0-9]+}}.16b, v1.16b, v0.16b 193 %tmp3 = icmp slt <16 x i8> %A, %B; 194 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 195 ret <16 x i8> %tmp4 196} 197 198define <4 x i16> @cmlt4xi16(<4 x i16> %A, <4 x i16> %B) { 199; CHECK-LABEL: cmlt4xi16: 200; Using registers other than v0, v1 are possible, but would be odd. 201; LT implemented as GT, so check reversed operands. 202; CHECK: cmgt {{v[0-9]+}}.4h, v1.4h, v0.4h 203 %tmp3 = icmp slt <4 x i16> %A, %B; 204 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 205 ret <4 x i16> %tmp4 206} 207 208define <8 x i16> @cmlt8xi16(<8 x i16> %A, <8 x i16> %B) { 209; CHECK-LABEL: cmlt8xi16: 210; Using registers other than v0, v1 are possible, but would be odd. 211; LT implemented as GT, so check reversed operands. 212; CHECK: cmgt {{v[0-9]+}}.8h, v1.8h, v0.8h 213 %tmp3 = icmp slt <8 x i16> %A, %B; 214 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 215 ret <8 x i16> %tmp4 216} 217 218define <2 x i32> @cmlt2xi32(<2 x i32> %A, <2 x i32> %B) { 219; CHECK-LABEL: cmlt2xi32: 220; Using registers other than v0, v1 are possible, but would be odd. 221; LT implemented as GT, so check reversed operands. 222; CHECK: cmgt {{v[0-9]+}}.2s, v1.2s, v0.2s 223 %tmp3 = icmp slt <2 x i32> %A, %B; 224 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 225 ret <2 x i32> %tmp4 226} 227 228define <4 x i32> @cmlt4xi32(<4 x i32> %A, <4 x i32> %B) { 229; CHECK-LABEL: cmlt4xi32: 230; Using registers other than v0, v1 are possible, but would be odd. 231; LT implemented as GT, so check reversed operands. 232; CHECK: cmgt {{v[0-9]+}}.4s, v1.4s, v0.4s 233 %tmp3 = icmp slt <4 x i32> %A, %B; 234 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 235 ret <4 x i32> %tmp4 236} 237 238define <2 x i64> @cmlt2xi64(<2 x i64> %A, <2 x i64> %B) { 239; CHECK-LABEL: cmlt2xi64: 240; Using registers other than v0, v1 are possible, but would be odd. 241; LT implemented as GT, so check reversed operands. 242; CHECK: cmgt {{v[0-9]+}}.2d, v1.2d, v0.2d 243 %tmp3 = icmp slt <2 x i64> %A, %B; 244 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 245 ret <2 x i64> %tmp4 246} 247 248define <8 x i8> @cmge8xi8(<8 x i8> %A, <8 x i8> %B) { 249; CHECK-LABEL: cmge8xi8: 250; CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 251 %tmp3 = icmp sge <8 x i8> %A, %B; 252 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 253 ret <8 x i8> %tmp4 254} 255 256define <16 x i8> @cmge16xi8(<16 x i8> %A, <16 x i8> %B) { 257; CHECK-LABEL: cmge16xi8: 258; CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 259 %tmp3 = icmp sge <16 x i8> %A, %B; 260 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 261 ret <16 x i8> %tmp4 262} 263 264define <4 x i16> @cmge4xi16(<4 x i16> %A, <4 x i16> %B) { 265; CHECK-LABEL: cmge4xi16: 266; CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 267 %tmp3 = icmp sge <4 x i16> %A, %B; 268 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 269 ret <4 x i16> %tmp4 270} 271 272define <8 x i16> @cmge8xi16(<8 x i16> %A, <8 x i16> %B) { 273; CHECK-LABEL: cmge8xi16: 274; CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 275 %tmp3 = icmp sge <8 x i16> %A, %B; 276 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 277 ret <8 x i16> %tmp4 278} 279 280define <2 x i32> @cmge2xi32(<2 x i32> %A, <2 x i32> %B) { 281; CHECK-LABEL: cmge2xi32: 282; CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 283 %tmp3 = icmp sge <2 x i32> %A, %B; 284 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 285 ret <2 x i32> %tmp4 286} 287 288define <4 x i32> @cmge4xi32(<4 x i32> %A, <4 x i32> %B) { 289; CHECK-LABEL: cmge4xi32: 290; CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 291 %tmp3 = icmp sge <4 x i32> %A, %B; 292 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 293 ret <4 x i32> %tmp4 294} 295 296define <2 x i64> @cmge2xi64(<2 x i64> %A, <2 x i64> %B) { 297; CHECK-LABEL: cmge2xi64: 298; CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 299 %tmp3 = icmp sge <2 x i64> %A, %B; 300 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 301 ret <2 x i64> %tmp4 302} 303 304define <8 x i8> @cmle8xi8(<8 x i8> %A, <8 x i8> %B) { 305; CHECK-LABEL: cmle8xi8: 306; Using registers other than v0, v1 are possible, but would be odd. 307; LE implemented as GE, so check reversed operands. 308; CHECK: cmge {{v[0-9]+}}.8b, v1.8b, v0.8b 309 %tmp3 = icmp sle <8 x i8> %A, %B; 310 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 311 ret <8 x i8> %tmp4 312} 313 314define <16 x i8> @cmle16xi8(<16 x i8> %A, <16 x i8> %B) { 315; CHECK-LABEL: cmle16xi8: 316; Using registers other than v0, v1 are possible, but would be odd. 317; LE implemented as GE, so check reversed operands. 318; CHECK: cmge {{v[0-9]+}}.16b, v1.16b, v0.16b 319 %tmp3 = icmp sle <16 x i8> %A, %B; 320 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 321 ret <16 x i8> %tmp4 322} 323 324define <4 x i16> @cmle4xi16(<4 x i16> %A, <4 x i16> %B) { 325; CHECK-LABEL: cmle4xi16: 326; Using registers other than v0, v1 are possible, but would be odd. 327; LE implemented as GE, so check reversed operands. 328; CHECK: cmge {{v[0-9]+}}.4h, v1.4h, v0.4h 329 %tmp3 = icmp sle <4 x i16> %A, %B; 330 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 331 ret <4 x i16> %tmp4 332} 333 334define <8 x i16> @cmle8xi16(<8 x i16> %A, <8 x i16> %B) { 335; CHECK-LABEL: cmle8xi16: 336; Using registers other than v0, v1 are possible, but would be odd. 337; LE implemented as GE, so check reversed operands. 338; CHECK: cmge {{v[0-9]+}}.8h, v1.8h, v0.8h 339 %tmp3 = icmp sle <8 x i16> %A, %B; 340 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 341 ret <8 x i16> %tmp4 342} 343 344define <2 x i32> @cmle2xi32(<2 x i32> %A, <2 x i32> %B) { 345; CHECK-LABEL: cmle2xi32: 346; Using registers other than v0, v1 are possible, but would be odd. 347; LE implemented as GE, so check reversed operands. 348; CHECK: cmge {{v[0-9]+}}.2s, v1.2s, v0.2s 349 %tmp3 = icmp sle <2 x i32> %A, %B; 350 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 351 ret <2 x i32> %tmp4 352} 353 354define <4 x i32> @cmle4xi32(<4 x i32> %A, <4 x i32> %B) { 355; CHECK-LABEL: cmle4xi32: 356; Using registers other than v0, v1 are possible, but would be odd. 357; LE implemented as GE, so check reversed operands. 358; CHECK: cmge {{v[0-9]+}}.4s, v1.4s, v0.4s 359 %tmp3 = icmp sle <4 x i32> %A, %B; 360 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 361 ret <4 x i32> %tmp4 362} 363 364define <2 x i64> @cmle2xi64(<2 x i64> %A, <2 x i64> %B) { 365; CHECK-LABEL: cmle2xi64: 366; Using registers other than v0, v1 are possible, but would be odd. 367; LE implemented as GE, so check reversed operands. 368; CHECK: cmge {{v[0-9]+}}.2d, v1.2d, v0.2d 369 %tmp3 = icmp sle <2 x i64> %A, %B; 370 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 371 ret <2 x i64> %tmp4 372} 373 374define <8 x i8> @cmhi8xi8(<8 x i8> %A, <8 x i8> %B) { 375; CHECK-LABEL: cmhi8xi8: 376; CHECK: cmhi {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 377 %tmp3 = icmp ugt <8 x i8> %A, %B; 378 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 379 ret <8 x i8> %tmp4 380} 381 382define <16 x i8> @cmhi16xi8(<16 x i8> %A, <16 x i8> %B) { 383; CHECK-LABEL: cmhi16xi8: 384; CHECK: cmhi {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 385 %tmp3 = icmp ugt <16 x i8> %A, %B; 386 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 387 ret <16 x i8> %tmp4 388} 389 390define <4 x i16> @cmhi4xi16(<4 x i16> %A, <4 x i16> %B) { 391; CHECK-LABEL: cmhi4xi16: 392; CHECK: cmhi {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 393 %tmp3 = icmp ugt <4 x i16> %A, %B; 394 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 395 ret <4 x i16> %tmp4 396} 397 398define <8 x i16> @cmhi8xi16(<8 x i16> %A, <8 x i16> %B) { 399; CHECK-LABEL: cmhi8xi16: 400; CHECK: cmhi {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 401 %tmp3 = icmp ugt <8 x i16> %A, %B; 402 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 403 ret <8 x i16> %tmp4 404} 405 406define <2 x i32> @cmhi2xi32(<2 x i32> %A, <2 x i32> %B) { 407; CHECK-LABEL: cmhi2xi32: 408; CHECK: cmhi {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 409 %tmp3 = icmp ugt <2 x i32> %A, %B; 410 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 411 ret <2 x i32> %tmp4 412} 413 414define <4 x i32> @cmhi4xi32(<4 x i32> %A, <4 x i32> %B) { 415; CHECK-LABEL: cmhi4xi32: 416; CHECK: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 417 %tmp3 = icmp ugt <4 x i32> %A, %B; 418 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 419 ret <4 x i32> %tmp4 420} 421 422define <2 x i64> @cmhi2xi64(<2 x i64> %A, <2 x i64> %B) { 423; CHECK-LABEL: cmhi2xi64: 424; CHECK: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 425 %tmp3 = icmp ugt <2 x i64> %A, %B; 426 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 427 ret <2 x i64> %tmp4 428} 429 430define <8 x i8> @cmlo8xi8(<8 x i8> %A, <8 x i8> %B) { 431; CHECK-LABEL: cmlo8xi8: 432; Using registers other than v0, v1 are possible, but would be odd. 433; LO implemented as HI, so check reversed operands. 434; CHECK: cmhi {{v[0-9]+}}.8b, v1.8b, v0.8b 435 %tmp3 = icmp ult <8 x i8> %A, %B; 436 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 437 ret <8 x i8> %tmp4 438} 439 440define <16 x i8> @cmlo16xi8(<16 x i8> %A, <16 x i8> %B) { 441; CHECK-LABEL: cmlo16xi8: 442; Using registers other than v0, v1 are possible, but would be odd. 443; LO implemented as HI, so check reversed operands. 444; CHECK: cmhi {{v[0-9]+}}.16b, v1.16b, v0.16b 445 %tmp3 = icmp ult <16 x i8> %A, %B; 446 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 447 ret <16 x i8> %tmp4 448} 449 450define <4 x i16> @cmlo4xi16(<4 x i16> %A, <4 x i16> %B) { 451; CHECK-LABEL: cmlo4xi16: 452; Using registers other than v0, v1 are possible, but would be odd. 453; LO implemented as HI, so check reversed operands. 454; CHECK: cmhi {{v[0-9]+}}.4h, v1.4h, v0.4h 455 %tmp3 = icmp ult <4 x i16> %A, %B; 456 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 457 ret <4 x i16> %tmp4 458} 459 460define <8 x i16> @cmlo8xi16(<8 x i16> %A, <8 x i16> %B) { 461; CHECK-LABEL: cmlo8xi16: 462; Using registers other than v0, v1 are possible, but would be odd. 463; LO implemented as HI, so check reversed operands. 464; CHECK: cmhi {{v[0-9]+}}.8h, v1.8h, v0.8h 465 %tmp3 = icmp ult <8 x i16> %A, %B; 466 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 467 ret <8 x i16> %tmp4 468} 469 470define <2 x i32> @cmlo2xi32(<2 x i32> %A, <2 x i32> %B) { 471; CHECK-LABEL: cmlo2xi32: 472; Using registers other than v0, v1 are possible, but would be odd. 473; LO implemented as HI, so check reversed operands. 474; CHECK: cmhi {{v[0-9]+}}.2s, v1.2s, v0.2s 475 %tmp3 = icmp ult <2 x i32> %A, %B; 476 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 477 ret <2 x i32> %tmp4 478} 479 480define <4 x i32> @cmlo4xi32(<4 x i32> %A, <4 x i32> %B) { 481; CHECK-LABEL: cmlo4xi32: 482; Using registers other than v0, v1 are possible, but would be odd. 483; LO implemented as HI, so check reversed operands. 484; CHECK: cmhi {{v[0-9]+}}.4s, v1.4s, v0.4s 485 %tmp3 = icmp ult <4 x i32> %A, %B; 486 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 487 ret <4 x i32> %tmp4 488} 489 490define <2 x i64> @cmlo2xi64(<2 x i64> %A, <2 x i64> %B) { 491; CHECK-LABEL: cmlo2xi64: 492; Using registers other than v0, v1 are possible, but would be odd. 493; LO implemented as HI, so check reversed operands. 494; CHECK: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d 495 %tmp3 = icmp ult <2 x i64> %A, %B; 496 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 497 ret <2 x i64> %tmp4 498} 499 500define <8 x i8> @cmhs8xi8(<8 x i8> %A, <8 x i8> %B) { 501; CHECK-LABEL: cmhs8xi8: 502; CHECK: cmhs {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 503 %tmp3 = icmp uge <8 x i8> %A, %B; 504 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 505 ret <8 x i8> %tmp4 506} 507 508define <16 x i8> @cmhs16xi8(<16 x i8> %A, <16 x i8> %B) { 509; CHECK-LABEL: cmhs16xi8: 510; CHECK: cmhs {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 511 %tmp3 = icmp uge <16 x i8> %A, %B; 512 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 513 ret <16 x i8> %tmp4 514} 515 516define <4 x i16> @cmhs4xi16(<4 x i16> %A, <4 x i16> %B) { 517; CHECK-LABEL: cmhs4xi16: 518; CHECK: cmhs {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 519 %tmp3 = icmp uge <4 x i16> %A, %B; 520 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 521 ret <4 x i16> %tmp4 522} 523 524define <8 x i16> @cmhs8xi16(<8 x i16> %A, <8 x i16> %B) { 525; CHECK-LABEL: cmhs8xi16: 526; CHECK: cmhs {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 527 %tmp3 = icmp uge <8 x i16> %A, %B; 528 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 529 ret <8 x i16> %tmp4 530} 531 532define <2 x i32> @cmhs2xi32(<2 x i32> %A, <2 x i32> %B) { 533; CHECK-LABEL: cmhs2xi32: 534; CHECK: cmhs {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 535 %tmp3 = icmp uge <2 x i32> %A, %B; 536 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 537 ret <2 x i32> %tmp4 538} 539 540define <4 x i32> @cmhs4xi32(<4 x i32> %A, <4 x i32> %B) { 541; CHECK-LABEL: cmhs4xi32: 542; CHECK: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 543 %tmp3 = icmp uge <4 x i32> %A, %B; 544 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 545 ret <4 x i32> %tmp4 546} 547 548define <2 x i64> @cmhs2xi64(<2 x i64> %A, <2 x i64> %B) { 549; CHECK-LABEL: cmhs2xi64: 550; CHECK: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 551 %tmp3 = icmp uge <2 x i64> %A, %B; 552 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 553 ret <2 x i64> %tmp4 554} 555 556define <8 x i8> @cmls8xi8(<8 x i8> %A, <8 x i8> %B) { 557; CHECK-LABEL: cmls8xi8: 558; Using registers other than v0, v1 are possible, but would be odd. 559; LS implemented as HS, so check reversed operands. 560; CHECK: cmhs {{v[0-9]+}}.8b, v1.8b, v0.8b 561 %tmp3 = icmp ule <8 x i8> %A, %B; 562 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 563 ret <8 x i8> %tmp4 564} 565 566define <16 x i8> @cmls16xi8(<16 x i8> %A, <16 x i8> %B) { 567; CHECK-LABEL: cmls16xi8: 568; Using registers other than v0, v1 are possible, but would be odd. 569; LS implemented as HS, so check reversed operands. 570; CHECK: cmhs {{v[0-9]+}}.16b, v1.16b, v0.16b 571 %tmp3 = icmp ule <16 x i8> %A, %B; 572 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 573 ret <16 x i8> %tmp4 574} 575 576define <4 x i16> @cmls4xi16(<4 x i16> %A, <4 x i16> %B) { 577; CHECK-LABEL: cmls4xi16: 578; Using registers other than v0, v1 are possible, but would be odd. 579; LS implemented as HS, so check reversed operands. 580; CHECK: cmhs {{v[0-9]+}}.4h, v1.4h, v0.4h 581 %tmp3 = icmp ule <4 x i16> %A, %B; 582 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 583 ret <4 x i16> %tmp4 584} 585 586define <8 x i16> @cmls8xi16(<8 x i16> %A, <8 x i16> %B) { 587; CHECK-LABEL: cmls8xi16: 588; Using registers other than v0, v1 are possible, but would be odd. 589; LS implemented as HS, so check reversed operands. 590; CHECK: cmhs {{v[0-9]+}}.8h, v1.8h, v0.8h 591 %tmp3 = icmp ule <8 x i16> %A, %B; 592 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 593 ret <8 x i16> %tmp4 594} 595 596define <2 x i32> @cmls2xi32(<2 x i32> %A, <2 x i32> %B) { 597; CHECK-LABEL: cmls2xi32: 598; Using registers other than v0, v1 are possible, but would be odd. 599; LS implemented as HS, so check reversed operands. 600; CHECK: cmhs {{v[0-9]+}}.2s, v1.2s, v0.2s 601 %tmp3 = icmp ule <2 x i32> %A, %B; 602 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 603 ret <2 x i32> %tmp4 604} 605 606define <4 x i32> @cmls4xi32(<4 x i32> %A, <4 x i32> %B) { 607; CHECK-LABEL: cmls4xi32: 608; Using registers other than v0, v1 are possible, but would be odd. 609; LS implemented as HS, so check reversed operands. 610; CHECK: cmhs {{v[0-9]+}}.4s, v1.4s, v0.4s 611 %tmp3 = icmp ule <4 x i32> %A, %B; 612 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 613 ret <4 x i32> %tmp4 614} 615 616define <2 x i64> @cmls2xi64(<2 x i64> %A, <2 x i64> %B) { 617; CHECK-LABEL: cmls2xi64: 618; Using registers other than v0, v1 are possible, but would be odd. 619; LS implemented as HS, so check reversed operands. 620; CHECK: cmhs {{v[0-9]+}}.2d, v1.2d, v0.2d 621 %tmp3 = icmp ule <2 x i64> %A, %B; 622 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 623 ret <2 x i64> %tmp4 624} 625 626define <8 x i8> @cmtst8xi8(<8 x i8> %A, <8 x i8> %B) { 627; CHECK-LABEL: cmtst8xi8: 628; CHECK: cmtst {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 629 %tmp3 = and <8 x i8> %A, %B 630 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer 631 %tmp5 = sext <8 x i1> %tmp4 to <8 x i8> 632 ret <8 x i8> %tmp5 633} 634 635define <16 x i8> @cmtst16xi8(<16 x i8> %A, <16 x i8> %B) { 636; CHECK-LABEL: cmtst16xi8: 637; CHECK: cmtst {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 638 %tmp3 = and <16 x i8> %A, %B 639 %tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer 640 %tmp5 = sext <16 x i1> %tmp4 to <16 x i8> 641 ret <16 x i8> %tmp5 642} 643 644define <4 x i16> @cmtst4xi16(<4 x i16> %A, <4 x i16> %B) { 645; CHECK-LABEL: cmtst4xi16: 646; CHECK: cmtst {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 647 %tmp3 = and <4 x i16> %A, %B 648 %tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer 649 %tmp5 = sext <4 x i1> %tmp4 to <4 x i16> 650 ret <4 x i16> %tmp5 651} 652 653define <8 x i16> @cmtst8xi16(<8 x i16> %A, <8 x i16> %B) { 654; CHECK-LABEL: cmtst8xi16: 655; CHECK: cmtst {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 656 %tmp3 = and <8 x i16> %A, %B 657 %tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer 658 %tmp5 = sext <8 x i1> %tmp4 to <8 x i16> 659 ret <8 x i16> %tmp5 660} 661 662define <2 x i32> @cmtst2xi32(<2 x i32> %A, <2 x i32> %B) { 663; CHECK-LABEL: cmtst2xi32: 664; CHECK: cmtst {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 665 %tmp3 = and <2 x i32> %A, %B 666 %tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer 667 %tmp5 = sext <2 x i1> %tmp4 to <2 x i32> 668 ret <2 x i32> %tmp5 669} 670 671define <4 x i32> @cmtst4xi32(<4 x i32> %A, <4 x i32> %B) { 672; CHECK-LABEL: cmtst4xi32: 673; CHECK: cmtst {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 674 %tmp3 = and <4 x i32> %A, %B 675 %tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer 676 %tmp5 = sext <4 x i1> %tmp4 to <4 x i32> 677 ret <4 x i32> %tmp5 678} 679 680define <2 x i64> @cmtst2xi64(<2 x i64> %A, <2 x i64> %B) { 681; CHECK-LABEL: cmtst2xi64: 682; CHECK: cmtst {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 683 %tmp3 = and <2 x i64> %A, %B 684 %tmp4 = icmp ne <2 x i64> %tmp3, zeroinitializer 685 %tmp5 = sext <2 x i1> %tmp4 to <2 x i64> 686 ret <2 x i64> %tmp5 687} 688 689 690 691define <8 x i8> @cmeqz8xi8(<8 x i8> %A) { 692; CHECK-LABEL: cmeqz8xi8: 693; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} 694 %tmp3 = icmp eq <8 x i8> %A, zeroinitializer; 695 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 696 ret <8 x i8> %tmp4 697} 698 699define <16 x i8> @cmeqz16xi8(<16 x i8> %A) { 700; CHECK-LABEL: cmeqz16xi8: 701; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} 702 %tmp3 = icmp eq <16 x i8> %A, zeroinitializer; 703 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 704 ret <16 x i8> %tmp4 705} 706 707define <4 x i16> @cmeqz4xi16(<4 x i16> %A) { 708; CHECK-LABEL: cmeqz4xi16: 709; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} 710 %tmp3 = icmp eq <4 x i16> %A, zeroinitializer; 711 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 712 ret <4 x i16> %tmp4 713} 714 715define <8 x i16> @cmeqz8xi16(<8 x i16> %A) { 716; CHECK-LABEL: cmeqz8xi16: 717; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} 718 %tmp3 = icmp eq <8 x i16> %A, zeroinitializer; 719 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 720 ret <8 x i16> %tmp4 721} 722 723define <2 x i32> @cmeqz2xi32(<2 x i32> %A) { 724; CHECK-LABEL: cmeqz2xi32: 725; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} 726 %tmp3 = icmp eq <2 x i32> %A, zeroinitializer; 727 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 728 ret <2 x i32> %tmp4 729} 730 731define <4 x i32> @cmeqz4xi32(<4 x i32> %A) { 732; CHECK-LABEL: cmeqz4xi32: 733; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} 734 %tmp3 = icmp eq <4 x i32> %A, zeroinitializer; 735 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 736 ret <4 x i32> %tmp4 737} 738 739define <2 x i64> @cmeqz2xi64(<2 x i64> %A) { 740; CHECK-LABEL: cmeqz2xi64: 741; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} 742 %tmp3 = icmp eq <2 x i64> %A, zeroinitializer; 743 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 744 ret <2 x i64> %tmp4 745} 746 747 748define <8 x i8> @cmgez8xi8(<8 x i8> %A) { 749; CHECK-LABEL: cmgez8xi8: 750; CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} 751 %tmp3 = icmp sge <8 x i8> %A, zeroinitializer; 752 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 753 ret <8 x i8> %tmp4 754} 755 756define <16 x i8> @cmgez16xi8(<16 x i8> %A) { 757; CHECK-LABEL: cmgez16xi8: 758; CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} 759 %tmp3 = icmp sge <16 x i8> %A, zeroinitializer; 760 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 761 ret <16 x i8> %tmp4 762} 763 764define <4 x i16> @cmgez4xi16(<4 x i16> %A) { 765; CHECK-LABEL: cmgez4xi16: 766; CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} 767 %tmp3 = icmp sge <4 x i16> %A, zeroinitializer; 768 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 769 ret <4 x i16> %tmp4 770} 771 772define <8 x i16> @cmgez8xi16(<8 x i16> %A) { 773; CHECK-LABEL: cmgez8xi16: 774; CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} 775 %tmp3 = icmp sge <8 x i16> %A, zeroinitializer; 776 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 777 ret <8 x i16> %tmp4 778} 779 780define <2 x i32> @cmgez2xi32(<2 x i32> %A) { 781; CHECK-LABEL: cmgez2xi32: 782; CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} 783 %tmp3 = icmp sge <2 x i32> %A, zeroinitializer; 784 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 785 ret <2 x i32> %tmp4 786} 787 788define <4 x i32> @cmgez4xi32(<4 x i32> %A) { 789; CHECK-LABEL: cmgez4xi32: 790; CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} 791 %tmp3 = icmp sge <4 x i32> %A, zeroinitializer; 792 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 793 ret <4 x i32> %tmp4 794} 795 796define <2 x i64> @cmgez2xi64(<2 x i64> %A) { 797; CHECK-LABEL: cmgez2xi64: 798; CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} 799 %tmp3 = icmp sge <2 x i64> %A, zeroinitializer; 800 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 801 ret <2 x i64> %tmp4 802} 803 804 805define <8 x i8> @cmgez8xi8_alt(<8 x i8> %A) { 806; CHECK-LABEL: cmgez8xi8_alt: 807; CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} 808 %sign = ashr <8 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 809 %not = xor <8 x i8> %sign, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 810 ret <8 x i8> %not 811} 812 813define <16 x i8> @cmgez16xi8_alt(<16 x i8> %A) { 814; CHECK-LABEL: cmgez16xi8_alt: 815; CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} 816 %sign = ashr <16 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> 817 %not = xor <16 x i8> %sign, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 818 ret <16 x i8> %not 819} 820 821define <4 x i16> @cmgez4xi16_alt(<4 x i16> %A) { 822; CHECK-LABEL: cmgez4xi16_alt: 823; CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} 824 %sign = ashr <4 x i16> %A, <i16 15, i16 15, i16 15, i16 15> 825 %not = xor <4 x i16> %sign, <i16 -1, i16 -1, i16 -1, i16 -1> 826 ret <4 x i16> %not 827} 828 829define <8 x i16> @cmgez8xi16_alt(<8 x i16> %A) { 830; CHECK-LABEL: cmgez8xi16_alt: 831; CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} 832 %sign = ashr <8 x i16> %A, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 833 %not = xor <8 x i16> %sign, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 834 ret <8 x i16> %not 835} 836 837define <2 x i32> @cmgez2xi32_alt(<2 x i32> %A) { 838; CHECK-LABEL: cmgez2xi32_alt: 839; CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} 840 %sign = ashr <2 x i32> %A, <i32 31, i32 31> 841 %not = xor <2 x i32> %sign, <i32 -1, i32 -1> 842 ret <2 x i32> %not 843} 844 845define <4 x i32> @cmgez4xi32_alt(<4 x i32> %A) { 846; CHECK-LABEL: cmgez4xi32_alt: 847; CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} 848 %sign = ashr <4 x i32> %A, <i32 31, i32 31, i32 31, i32 31> 849 %not = xor <4 x i32> %sign, <i32 -1, i32 -1, i32 -1, i32 -1> 850 ret <4 x i32> %not 851} 852 853define <2 x i64> @cmgez2xi64_alt(<2 x i64> %A) { 854; CHECK-LABEL: cmgez2xi64_alt: 855; CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} 856 %sign = ashr <2 x i64> %A, <i64 63, i64 63> 857 %not = xor <2 x i64> %sign, <i64 -1, i64 -1> 858 ret <2 x i64> %not 859} 860 861 862define <8 x i8> @cmgtz8xi8(<8 x i8> %A) { 863; CHECK-LABEL: cmgtz8xi8: 864; CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} 865 %tmp3 = icmp sgt <8 x i8> %A, zeroinitializer; 866 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 867 ret <8 x i8> %tmp4 868} 869 870define <16 x i8> @cmgtz16xi8(<16 x i8> %A) { 871; CHECK-LABEL: cmgtz16xi8: 872; CHECK: cmgt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} 873 %tmp3 = icmp sgt <16 x i8> %A, zeroinitializer; 874 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 875 ret <16 x i8> %tmp4 876} 877 878define <4 x i16> @cmgtz4xi16(<4 x i16> %A) { 879; CHECK-LABEL: cmgtz4xi16: 880; CHECK: cmgt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} 881 %tmp3 = icmp sgt <4 x i16> %A, zeroinitializer; 882 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 883 ret <4 x i16> %tmp4 884} 885 886define <8 x i16> @cmgtz8xi16(<8 x i16> %A) { 887; CHECK-LABEL: cmgtz8xi16: 888; CHECK: cmgt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} 889 %tmp3 = icmp sgt <8 x i16> %A, zeroinitializer; 890 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 891 ret <8 x i16> %tmp4 892} 893 894define <2 x i32> @cmgtz2xi32(<2 x i32> %A) { 895; CHECK-LABEL: cmgtz2xi32: 896; CHECK: cmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} 897 %tmp3 = icmp sgt <2 x i32> %A, zeroinitializer; 898 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 899 ret <2 x i32> %tmp4 900} 901 902define <4 x i32> @cmgtz4xi32(<4 x i32> %A) { 903; CHECK-LABEL: cmgtz4xi32: 904; CHECK: cmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} 905 %tmp3 = icmp sgt <4 x i32> %A, zeroinitializer; 906 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 907 ret <4 x i32> %tmp4 908} 909 910define <2 x i64> @cmgtz2xi64(<2 x i64> %A) { 911; CHECK-LABEL: cmgtz2xi64: 912; CHECK: cmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} 913 %tmp3 = icmp sgt <2 x i64> %A, zeroinitializer; 914 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 915 ret <2 x i64> %tmp4 916} 917 918define <8 x i8> @cmlez8xi8(<8 x i8> %A) { 919; CHECK-LABEL: cmlez8xi8: 920; CHECK: cmle {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} 921 %tmp3 = icmp sle <8 x i8> %A, zeroinitializer; 922 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 923 ret <8 x i8> %tmp4 924} 925 926define <16 x i8> @cmlez16xi8(<16 x i8> %A) { 927; CHECK-LABEL: cmlez16xi8: 928; CHECK: cmle {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} 929 %tmp3 = icmp sle <16 x i8> %A, zeroinitializer; 930 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 931 ret <16 x i8> %tmp4 932} 933 934define <4 x i16> @cmlez4xi16(<4 x i16> %A) { 935; CHECK-LABEL: cmlez4xi16: 936; CHECK: cmle {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} 937 %tmp3 = icmp sle <4 x i16> %A, zeroinitializer; 938 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 939 ret <4 x i16> %tmp4 940} 941 942define <8 x i16> @cmlez8xi16(<8 x i16> %A) { 943; CHECK-LABEL: cmlez8xi16: 944; CHECK: cmle {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} 945 %tmp3 = icmp sle <8 x i16> %A, zeroinitializer; 946 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 947 ret <8 x i16> %tmp4 948} 949 950define <2 x i32> @cmlez2xi32(<2 x i32> %A) { 951; CHECK-LABEL: cmlez2xi32: 952; CHECK: cmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} 953 %tmp3 = icmp sle <2 x i32> %A, zeroinitializer; 954 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 955 ret <2 x i32> %tmp4 956} 957 958define <4 x i32> @cmlez4xi32(<4 x i32> %A) { 959; CHECK-LABEL: cmlez4xi32: 960; CHECK: cmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} 961 %tmp3 = icmp sle <4 x i32> %A, zeroinitializer; 962 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 963 ret <4 x i32> %tmp4 964} 965 966define <2 x i64> @cmlez2xi64(<2 x i64> %A) { 967; CHECK-LABEL: cmlez2xi64: 968; CHECK: cmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} 969 %tmp3 = icmp sle <2 x i64> %A, zeroinitializer; 970 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 971 ret <2 x i64> %tmp4 972} 973 974define <8 x i8> @cmltz8xi8(<8 x i8> %A) { 975; CHECK-LABEL: cmltz8xi8: 976; CHECK: cmlt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} 977 %tmp3 = icmp slt <8 x i8> %A, zeroinitializer; 978 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 979 ret <8 x i8> %tmp4 980} 981 982define <16 x i8> @cmltz16xi8(<16 x i8> %A) { 983; CHECK-LABEL: cmltz16xi8: 984; CHECK: cmlt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} 985 %tmp3 = icmp slt <16 x i8> %A, zeroinitializer; 986 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 987 ret <16 x i8> %tmp4 988} 989 990define <4 x i16> @cmltz4xi16(<4 x i16> %A) { 991; CHECK-LABEL: cmltz4xi16: 992; CHECK: cmlt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} 993 %tmp3 = icmp slt <4 x i16> %A, zeroinitializer; 994 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 995 ret <4 x i16> %tmp4 996} 997 998define <8 x i16> @cmltz8xi16(<8 x i16> %A) { 999; CHECK-LABEL: cmltz8xi16: 1000; CHECK: cmlt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} 1001 %tmp3 = icmp slt <8 x i16> %A, zeroinitializer; 1002 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1003 ret <8 x i16> %tmp4 1004} 1005 1006define <2 x i32> @cmltz2xi32(<2 x i32> %A) { 1007; CHECK-LABEL: cmltz2xi32: 1008; CHECK: cmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} 1009 %tmp3 = icmp slt <2 x i32> %A, zeroinitializer; 1010 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1011 ret <2 x i32> %tmp4 1012} 1013 1014define <4 x i32> @cmltz4xi32(<4 x i32> %A) { 1015; CHECK-LABEL: cmltz4xi32: 1016; CHECK: cmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} 1017 %tmp3 = icmp slt <4 x i32> %A, zeroinitializer; 1018 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1019 ret <4 x i32> %tmp4 1020} 1021 1022define <2 x i64> @cmltz2xi64(<2 x i64> %A) { 1023; CHECK-LABEL: cmltz2xi64: 1024; CHECK: cmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} 1025 %tmp3 = icmp slt <2 x i64> %A, zeroinitializer; 1026 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1027 ret <2 x i64> %tmp4 1028} 1029 1030define <8 x i8> @cmneqz8xi8(<8 x i8> %A) { 1031; CHECK-LABEL: cmneqz8xi8: 1032; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} 1033; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1034 %tmp3 = icmp ne <8 x i8> %A, zeroinitializer; 1035 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1036 ret <8 x i8> %tmp4 1037} 1038 1039define <16 x i8> @cmneqz16xi8(<16 x i8> %A) { 1040; CHECK-LABEL: cmneqz16xi8: 1041; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} 1042; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1043 %tmp3 = icmp ne <16 x i8> %A, zeroinitializer; 1044 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1045 ret <16 x i8> %tmp4 1046} 1047 1048define <4 x i16> @cmneqz4xi16(<4 x i16> %A) { 1049; CHECK-LABEL: cmneqz4xi16: 1050; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} 1051; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1052 %tmp3 = icmp ne <4 x i16> %A, zeroinitializer; 1053 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1054 ret <4 x i16> %tmp4 1055} 1056 1057define <8 x i16> @cmneqz8xi16(<8 x i16> %A) { 1058; CHECK-LABEL: cmneqz8xi16: 1059; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} 1060; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1061 %tmp3 = icmp ne <8 x i16> %A, zeroinitializer; 1062 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1063 ret <8 x i16> %tmp4 1064} 1065 1066define <2 x i32> @cmneqz2xi32(<2 x i32> %A) { 1067; CHECK-LABEL: cmneqz2xi32: 1068; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} 1069; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1070 %tmp3 = icmp ne <2 x i32> %A, zeroinitializer; 1071 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1072 ret <2 x i32> %tmp4 1073} 1074 1075define <4 x i32> @cmneqz4xi32(<4 x i32> %A) { 1076; CHECK-LABEL: cmneqz4xi32: 1077; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} 1078; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1079 %tmp3 = icmp ne <4 x i32> %A, zeroinitializer; 1080 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1081 ret <4 x i32> %tmp4 1082} 1083 1084define <2 x i64> @cmneqz2xi64(<2 x i64> %A) { 1085; CHECK-LABEL: cmneqz2xi64: 1086; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} 1087; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1088 %tmp3 = icmp ne <2 x i64> %A, zeroinitializer; 1089 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1090 ret <2 x i64> %tmp4 1091} 1092 1093define <8 x i8> @cmhsz8xi8(<8 x i8> %A) { 1094; CHECK-LABEL: cmhsz8xi8: 1095; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}} 1096; CHECK-NEXT: cmhs {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1097 %tmp3 = icmp uge <8 x i8> %A, zeroinitializer; 1098 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1099 ret <8 x i8> %tmp4 1100} 1101 1102define <16 x i8> @cmhsz16xi8(<16 x i8> %A) { 1103; CHECK-LABEL: cmhsz16xi8: 1104; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}} 1105; CHECK-NEXT: cmhs {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1106 %tmp3 = icmp uge <16 x i8> %A, zeroinitializer; 1107 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1108 ret <16 x i8> %tmp4 1109} 1110 1111define <4 x i16> @cmhsz4xi16(<4 x i16> %A) { 1112; CHECK-LABEL: cmhsz4xi16: 1113; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}} 1114; CHECK-NEXT: cmhs {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 1115 %tmp3 = icmp uge <4 x i16> %A, zeroinitializer; 1116 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1117 ret <4 x i16> %tmp4 1118} 1119 1120define <8 x i16> @cmhsz8xi16(<8 x i16> %A) { 1121; CHECK-LABEL: cmhsz8xi16: 1122; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}} 1123; CHECK-NEXT: cmhs {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 1124 %tmp3 = icmp uge <8 x i16> %A, zeroinitializer; 1125 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1126 ret <8 x i16> %tmp4 1127} 1128 1129define <2 x i32> @cmhsz2xi32(<2 x i32> %A) { 1130; CHECK-LABEL: cmhsz2xi32: 1131; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}} 1132; CHECK-NEXT: cmhs {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 1133 %tmp3 = icmp uge <2 x i32> %A, zeroinitializer; 1134 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1135 ret <2 x i32> %tmp4 1136} 1137 1138define <4 x i32> @cmhsz4xi32(<4 x i32> %A) { 1139; CHECK-LABEL: cmhsz4xi32: 1140; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}} 1141; CHECK-NEXT: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 1142 %tmp3 = icmp uge <4 x i32> %A, zeroinitializer; 1143 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1144 ret <4 x i32> %tmp4 1145} 1146 1147define <2 x i64> @cmhsz2xi64(<2 x i64> %A) { 1148; CHECK-LABEL: cmhsz2xi64: 1149; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}} 1150; CHECK-NEXT: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 1151 %tmp3 = icmp uge <2 x i64> %A, zeroinitializer; 1152 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1153 ret <2 x i64> %tmp4 1154} 1155 1156 1157define <8 x i8> @cmhiz8xi8(<8 x i8> %A) { 1158; CHECK-LABEL: cmhiz8xi8: 1159; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}} 1160; CHECK-NEXT: cmhi {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1161 %tmp3 = icmp ugt <8 x i8> %A, zeroinitializer; 1162 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1163 ret <8 x i8> %tmp4 1164} 1165 1166define <16 x i8> @cmhiz16xi8(<16 x i8> %A) { 1167; CHECK-LABEL: cmhiz16xi8: 1168; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}} 1169; CHECK-NEXT: cmhi {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1170 %tmp3 = icmp ugt <16 x i8> %A, zeroinitializer; 1171 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1172 ret <16 x i8> %tmp4 1173} 1174 1175define <4 x i16> @cmhiz4xi16(<4 x i16> %A) { 1176; CHECK-LABEL: cmhiz4xi16: 1177; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}} 1178; CHECK-NEXT: cmhi {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 1179 %tmp3 = icmp ugt <4 x i16> %A, zeroinitializer; 1180 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1181 ret <4 x i16> %tmp4 1182} 1183 1184define <8 x i16> @cmhiz8xi16(<8 x i16> %A) { 1185; CHECK-LABEL: cmhiz8xi16: 1186; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}} 1187; CHECK-NEXT: cmhi {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 1188 %tmp3 = icmp ugt <8 x i16> %A, zeroinitializer; 1189 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1190 ret <8 x i16> %tmp4 1191} 1192 1193define <2 x i32> @cmhiz2xi32(<2 x i32> %A) { 1194; CHECK-LABEL: cmhiz2xi32: 1195; CHECK: movi {{v[0-9]+.8b|d[0-9]+}}, #{{0x0|0}} 1196; CHECK-NEXT: cmhi {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 1197 %tmp3 = icmp ugt <2 x i32> %A, zeroinitializer; 1198 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1199 ret <2 x i32> %tmp4 1200} 1201 1202define <4 x i32> @cmhiz4xi32(<4 x i32> %A) { 1203; CHECK-LABEL: cmhiz4xi32: 1204; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}} 1205; CHECK-NEXT: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 1206 %tmp3 = icmp ugt <4 x i32> %A, zeroinitializer; 1207 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1208 ret <4 x i32> %tmp4 1209} 1210 1211define <2 x i64> @cmhiz2xi64(<2 x i64> %A) { 1212; CHECK-LABEL: cmhiz2xi64: 1213; CHECK: movi {{v[0-9]+.(16b|2d)}}, #{{0x0|0}} 1214; CHECK-NEXT: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 1215 %tmp3 = icmp ugt <2 x i64> %A, zeroinitializer; 1216 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1217 ret <2 x i64> %tmp4 1218} 1219 1220define <8 x i8> @cmlsz8xi8(<8 x i8> %A) { 1221; CHECK-LABEL: cmlsz8xi8: 1222; Using registers other than v0, v1 are possible, but would be odd. 1223; LS implemented as HS, so check reversed operands. 1224; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}} 1225; CHECK-NEXT: cmhs {{v[0-9]+}}.8b, v1.8b, v0.8b 1226 %tmp3 = icmp ule <8 x i8> %A, zeroinitializer; 1227 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1228 ret <8 x i8> %tmp4 1229} 1230 1231define <16 x i8> @cmlsz16xi8(<16 x i8> %A) { 1232; CHECK-LABEL: cmlsz16xi8: 1233; Using registers other than v0, v1 are possible, but would be odd. 1234; LS implemented as HS, so check reversed operands. 1235; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}} 1236; CHECK-NEXT: cmhs {{v[0-9]+}}.16b, v1.16b, v0.16b 1237 %tmp3 = icmp ule <16 x i8> %A, zeroinitializer; 1238 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1239 ret <16 x i8> %tmp4 1240} 1241 1242define <4 x i16> @cmlsz4xi16(<4 x i16> %A) { 1243; CHECK-LABEL: cmlsz4xi16: 1244; Using registers other than v0, v1 are possible, but would be odd. 1245; LS implemented as HS, so check reversed operands. 1246; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}} 1247; CHECK-NEXT: cmhs {{v[0-9]+}}.4h, v1.4h, v0.4h 1248 %tmp3 = icmp ule <4 x i16> %A, zeroinitializer; 1249 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1250 ret <4 x i16> %tmp4 1251} 1252 1253define <8 x i16> @cmlsz8xi16(<8 x i16> %A) { 1254; CHECK-LABEL: cmlsz8xi16: 1255; Using registers other than v0, v1 are possible, but would be odd. 1256; LS implemented as HS, so check reversed operands. 1257; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}} 1258; CHECK-NEXT: cmhs {{v[0-9]+}}.8h, v1.8h, v0.8h 1259 %tmp3 = icmp ule <8 x i16> %A, zeroinitializer; 1260 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1261 ret <8 x i16> %tmp4 1262} 1263 1264define <2 x i32> @cmlsz2xi32(<2 x i32> %A) { 1265; CHECK-LABEL: cmlsz2xi32: 1266; Using registers other than v0, v1 are possible, but would be odd. 1267; LS implemented as HS, so check reversed operands. 1268; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}} 1269; CHECK-NEXT: cmhs {{v[0-9]+}}.2s, v1.2s, v0.2s 1270 %tmp3 = icmp ule <2 x i32> %A, zeroinitializer; 1271 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1272 ret <2 x i32> %tmp4 1273} 1274 1275define <4 x i32> @cmlsz4xi32(<4 x i32> %A) { 1276; CHECK-LABEL: cmlsz4xi32: 1277; Using registers other than v0, v1 are possible, but would be odd. 1278; LS implemented as HS, so check reversed operands. 1279; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}} 1280; CHECK-NEXT: cmhs {{v[0-9]+}}.4s, v1.4s, v0.4s 1281 %tmp3 = icmp ule <4 x i32> %A, zeroinitializer; 1282 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1283 ret <4 x i32> %tmp4 1284} 1285 1286define <2 x i64> @cmlsz2xi64(<2 x i64> %A) { 1287; CHECK-LABEL: cmlsz2xi64: 1288; Using registers other than v0, v1 are possible, but would be odd. 1289; LS implemented as HS, so check reversed operands. 1290; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}} 1291; CHECK-NEXT: cmhs {{v[0-9]+}}.2d, v1.2d, v0.2d 1292 %tmp3 = icmp ule <2 x i64> %A, zeroinitializer; 1293 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1294 ret <2 x i64> %tmp4 1295} 1296 1297define <8 x i8> @cmloz8xi8(<8 x i8> %A) { 1298; CHECK-LABEL: cmloz8xi8: 1299; Using registers other than v0, v1 are possible, but would be odd. 1300; LO implemented as HI, so check reversed operands. 1301; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}} 1302; CHECK-NEXT: cmhi {{v[0-9]+}}.8b, v1.8b, {{v[0-9]+}}.8b 1303 %tmp3 = icmp ult <8 x i8> %A, zeroinitializer; 1304 %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> 1305 ret <8 x i8> %tmp4 1306} 1307 1308define <16 x i8> @cmloz16xi8(<16 x i8> %A) { 1309; CHECK-LABEL: cmloz16xi8: 1310; Using registers other than v0, v1 are possible, but would be odd. 1311; LO implemented as HI, so check reversed operands. 1312; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}} 1313; CHECK-NEXT: cmhi {{v[0-9]+}}.16b, v1.16b, v0.16b 1314 %tmp3 = icmp ult <16 x i8> %A, zeroinitializer; 1315 %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> 1316 ret <16 x i8> %tmp4 1317} 1318 1319define <4 x i16> @cmloz4xi16(<4 x i16> %A) { 1320; CHECK-LABEL: cmloz4xi16: 1321; Using registers other than v0, v1 are possible, but would be odd. 1322; LO implemented as HI, so check reversed operands. 1323; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}} 1324; CHECK-NEXT: cmhi {{v[0-9]+}}.4h, v1.4h, v0.4h 1325 %tmp3 = icmp ult <4 x i16> %A, zeroinitializer; 1326 %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> 1327 ret <4 x i16> %tmp4 1328} 1329 1330define <8 x i16> @cmloz8xi16(<8 x i16> %A) { 1331; CHECK-LABEL: cmloz8xi16: 1332; Using registers other than v0, v1 are possible, but would be odd. 1333; LO implemented as HI, so check reversed operands. 1334; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}} 1335; CHECK-NEXT: cmhi {{v[0-9]+}}.8h, v1.8h, v0.8h 1336 %tmp3 = icmp ult <8 x i16> %A, zeroinitializer; 1337 %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> 1338 ret <8 x i16> %tmp4 1339} 1340 1341define <2 x i32> @cmloz2xi32(<2 x i32> %A) { 1342; CHECK-LABEL: cmloz2xi32: 1343; Using registers other than v0, v1 are possible, but would be odd. 1344; LO implemented as HI, so check reversed operands. 1345; CHECK: movi {{v1.8b|d1}}, #{{0x0|0}} 1346; CHECK-NEXT: cmhi {{v[0-9]+}}.2s, v1.2s, v0.2s 1347 %tmp3 = icmp ult <2 x i32> %A, zeroinitializer; 1348 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1349 ret <2 x i32> %tmp4 1350} 1351 1352define <4 x i32> @cmloz4xi32(<4 x i32> %A) { 1353; CHECK-LABEL: cmloz4xi32: 1354; Using registers other than v0, v1 are possible, but would be odd. 1355; LO implemented as HI, so check reversed operands. 1356; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}} 1357; CHECK-NEXT: cmhi {{v[0-9]+}}.4s, v1.4s, v0.4s 1358 %tmp3 = icmp ult <4 x i32> %A, zeroinitializer; 1359 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1360 ret <4 x i32> %tmp4 1361} 1362 1363define <2 x i64> @cmloz2xi64(<2 x i64> %A) { 1364; CHECK-LABEL: cmloz2xi64: 1365; Using registers other than v0, v1 are possible, but would be odd. 1366; LO implemented as HI, so check reversed operands. 1367; CHECK: movi {{v1.16b|v1.2d}}, #{{0x0|0}} 1368; CHECK-NEXT: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d 1369 %tmp3 = icmp ult <2 x i64> %A, zeroinitializer; 1370 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1371 ret <2 x i64> %tmp4 1372} 1373 1374 1375define <2 x i32> @fcmoeq2xfloat(<2 x float> %A, <2 x float> %B) { 1376; CHECK-LABEL: fcmoeq2xfloat: 1377; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 1378 %tmp3 = fcmp oeq <2 x float> %A, %B 1379 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1380 ret <2 x i32> %tmp4 1381} 1382 1383define <4 x i32> @fcmoeq4xfloat(<4 x float> %A, <4 x float> %B) { 1384; CHECK-LABEL: fcmoeq4xfloat: 1385; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 1386 %tmp3 = fcmp oeq <4 x float> %A, %B 1387 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1388 ret <4 x i32> %tmp4 1389} 1390define <2 x i64> @fcmoeq2xdouble(<2 x double> %A, <2 x double> %B) { 1391; CHECK-LABEL: fcmoeq2xdouble: 1392; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 1393 %tmp3 = fcmp oeq <2 x double> %A, %B 1394 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1395 ret <2 x i64> %tmp4 1396} 1397 1398define <2 x i32> @fcmoge2xfloat(<2 x float> %A, <2 x float> %B) { 1399; CHECK-LABEL: fcmoge2xfloat: 1400; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 1401 %tmp3 = fcmp oge <2 x float> %A, %B 1402 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1403 ret <2 x i32> %tmp4 1404} 1405 1406define <4 x i32> @fcmoge4xfloat(<4 x float> %A, <4 x float> %B) { 1407; CHECK-LABEL: fcmoge4xfloat: 1408; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 1409 %tmp3 = fcmp oge <4 x float> %A, %B 1410 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1411 ret <4 x i32> %tmp4 1412} 1413define <2 x i64> @fcmoge2xdouble(<2 x double> %A, <2 x double> %B) { 1414; CHECK-LABEL: fcmoge2xdouble: 1415; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 1416 %tmp3 = fcmp oge <2 x double> %A, %B 1417 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1418 ret <2 x i64> %tmp4 1419} 1420 1421define <2 x i32> @fcmogt2xfloat(<2 x float> %A, <2 x float> %B) { 1422; CHECK-LABEL: fcmogt2xfloat: 1423; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 1424 %tmp3 = fcmp ogt <2 x float> %A, %B 1425 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1426 ret <2 x i32> %tmp4 1427} 1428 1429define <4 x i32> @fcmogt4xfloat(<4 x float> %A, <4 x float> %B) { 1430; CHECK-LABEL: fcmogt4xfloat: 1431; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 1432 %tmp3 = fcmp ogt <4 x float> %A, %B 1433 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1434 ret <4 x i32> %tmp4 1435} 1436define <2 x i64> @fcmogt2xdouble(<2 x double> %A, <2 x double> %B) { 1437; CHECK-LABEL: fcmogt2xdouble: 1438; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 1439 %tmp3 = fcmp ogt <2 x double> %A, %B 1440 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1441 ret <2 x i64> %tmp4 1442} 1443 1444define <2 x i32> @fcmole2xfloat(<2 x float> %A, <2 x float> %B) { 1445; CHECK-LABEL: fcmole2xfloat: 1446; Using registers other than v0, v1 are possible, but would be odd. 1447; OLE implemented as OGE, so check reversed operands. 1448; CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s 1449 %tmp3 = fcmp ole <2 x float> %A, %B 1450 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1451 ret <2 x i32> %tmp4 1452} 1453 1454define <4 x i32> @fcmole4xfloat(<4 x float> %A, <4 x float> %B) { 1455; CHECK-LABEL: fcmole4xfloat: 1456; Using registers other than v0, v1 are possible, but would be odd. 1457; OLE implemented as OGE, so check reversed operands. 1458; CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s 1459 %tmp3 = fcmp ole <4 x float> %A, %B 1460 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1461 ret <4 x i32> %tmp4 1462} 1463define <2 x i64> @fcmole2xdouble(<2 x double> %A, <2 x double> %B) { 1464; CHECK-LABEL: fcmole2xdouble: 1465; Using registers other than v0, v1 are possible, but would be odd. 1466; OLE implemented as OGE, so check reversed operands. 1467; CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d 1468 %tmp3 = fcmp ole <2 x double> %A, %B 1469 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1470 ret <2 x i64> %tmp4 1471} 1472 1473define <2 x i32> @fcmolt2xfloat(<2 x float> %A, <2 x float> %B) { 1474; CHECK-LABEL: fcmolt2xfloat: 1475; Using registers other than v0, v1 are possible, but would be odd. 1476; OLE implemented as OGE, so check reversed operands. 1477; CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s 1478 %tmp3 = fcmp olt <2 x float> %A, %B 1479 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1480 ret <2 x i32> %tmp4 1481} 1482 1483define <4 x i32> @fcmolt4xfloat(<4 x float> %A, <4 x float> %B) { 1484; CHECK-LABEL: fcmolt4xfloat: 1485; Using registers other than v0, v1 are possible, but would be odd. 1486; OLE implemented as OGE, so check reversed operands. 1487; CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s 1488 %tmp3 = fcmp olt <4 x float> %A, %B 1489 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1490 ret <4 x i32> %tmp4 1491} 1492define <2 x i64> @fcmolt2xdouble(<2 x double> %A, <2 x double> %B) { 1493; CHECK-LABEL: fcmolt2xdouble: 1494; Using registers other than v0, v1 are possible, but would be odd. 1495; OLE implemented as OGE, so check reversed operands. 1496; CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d 1497 %tmp3 = fcmp olt <2 x double> %A, %B 1498 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1499 ret <2 x i64> %tmp4 1500} 1501 1502define <2 x i32> @fcmone2xfloat(<2 x float> %A, <2 x float> %B) { 1503; CHECK-LABEL: fcmone2xfloat: 1504; Using registers other than v0, v1 are possible, but would be odd. 1505; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands 1506; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s 1507; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s 1508; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1509 %tmp3 = fcmp one <2 x float> %A, %B 1510 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1511 ret <2 x i32> %tmp4 1512} 1513 1514define <4 x i32> @fcmone4xfloat(<4 x float> %A, <4 x float> %B) { 1515; CHECK-LABEL: fcmone4xfloat: 1516; Using registers other than v0, v1 are possible, but would be odd. 1517; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands 1518; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s 1519; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s 1520; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1521 %tmp3 = fcmp one <4 x float> %A, %B 1522 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1523 ret <4 x i32> %tmp4 1524} 1525define <2 x i64> @fcmone2xdouble(<2 x double> %A, <2 x double> %B) { 1526; CHECK-LABEL: fcmone2xdouble: 1527; Using registers other than v0, v1 are possible, but would be odd. 1528; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands 1529; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d 1530; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d 1531; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1532; todo check reversed operands 1533 %tmp3 = fcmp one <2 x double> %A, %B 1534 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1535 ret <2 x i64> %tmp4 1536} 1537 1538 1539define <2 x i32> @fcmord2xfloat(<2 x float> %A, <2 x float> %B) { 1540; CHECK-LABEL: fcmord2xfloat: 1541; Using registers other than v0, v1 are possible, but would be odd. 1542; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands. 1543; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s 1544; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s 1545; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1546 %tmp3 = fcmp ord <2 x float> %A, %B 1547 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1548 ret <2 x i32> %tmp4 1549} 1550 1551 1552define <4 x i32> @fcmord4xfloat(<4 x float> %A, <4 x float> %B) { 1553; CHECK-LABEL: fcmord4xfloat: 1554; Using registers other than v0, v1 are possible, but would be odd. 1555; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands. 1556; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s 1557; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s 1558; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1559 %tmp3 = fcmp ord <4 x float> %A, %B 1560 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1561 ret <4 x i32> %tmp4 1562} 1563 1564define <2 x i64> @fcmord2xdouble(<2 x double> %A, <2 x double> %B) { 1565; CHECK-LABEL: fcmord2xdouble: 1566; Using registers other than v0, v1 are possible, but would be odd. 1567; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands. 1568; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d 1569; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d 1570; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1571 %tmp3 = fcmp ord <2 x double> %A, %B 1572 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1573 ret <2 x i64> %tmp4 1574} 1575 1576 1577define <2 x i32> @fcmuno2xfloat(<2 x float> %A, <2 x float> %B) { 1578; CHECK-LABEL: fcmuno2xfloat: 1579; Using registers other than v0, v1 are possible, but would be odd. 1580; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands. 1581; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s 1582; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s 1583; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1584; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1585 %tmp3 = fcmp uno <2 x float> %A, %B 1586 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1587 ret <2 x i32> %tmp4 1588} 1589 1590define <4 x i32> @fcmuno4xfloat(<4 x float> %A, <4 x float> %B) { 1591; CHECK-LABEL: fcmuno4xfloat: 1592; Using registers other than v0, v1 are possible, but would be odd. 1593; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands. 1594; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s 1595; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s 1596; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1597; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1598 %tmp3 = fcmp uno <4 x float> %A, %B 1599 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1600 ret <4 x i32> %tmp4 1601} 1602 1603define <2 x i64> @fcmuno2xdouble(<2 x double> %A, <2 x double> %B) { 1604; CHECK-LABEL: fcmuno2xdouble: 1605; Using registers other than v0, v1 are possible, but would be odd. 1606; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands. 1607; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d 1608; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d 1609; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1610; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1611 %tmp3 = fcmp uno <2 x double> %A, %B 1612 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1613 ret <2 x i64> %tmp4 1614} 1615 1616define <2 x i32> @fcmueq2xfloat(<2 x float> %A, <2 x float> %B) { 1617; CHECK-LABEL: fcmueq2xfloat: 1618; Using registers other than v0, v1 are possible, but would be odd. 1619; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands 1620; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s 1621; CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s 1622; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1623; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1624 %tmp3 = fcmp ueq <2 x float> %A, %B 1625 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1626 ret <2 x i32> %tmp4 1627} 1628 1629define <4 x i32> @fcmueq4xfloat(<4 x float> %A, <4 x float> %B) { 1630; CHECK-LABEL: fcmueq4xfloat: 1631; Using registers other than v0, v1 are possible, but would be odd. 1632; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands 1633; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s 1634; CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s 1635; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1636; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1637 %tmp3 = fcmp ueq <4 x float> %A, %B 1638 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1639 ret <4 x i32> %tmp4 1640} 1641 1642define <2 x i64> @fcmueq2xdouble(<2 x double> %A, <2 x double> %B) { 1643; CHECK-LABEL: fcmueq2xdouble: 1644; Using registers other than v0, v1 are possible, but would be odd. 1645; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands 1646; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d 1647; CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d 1648; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1649; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1650 %tmp3 = fcmp ueq <2 x double> %A, %B 1651 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1652 ret <2 x i64> %tmp4 1653} 1654 1655define <2 x i32> @fcmuge2xfloat(<2 x float> %A, <2 x float> %B) { 1656; CHECK-LABEL: fcmuge2xfloat: 1657; Using registers other than v0, v1 are possible, but would be odd. 1658; UGE = ULE with swapped operands, ULE implemented as !OGT. 1659; CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s 1660; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1661 %tmp3 = fcmp uge <2 x float> %A, %B 1662 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1663 ret <2 x i32> %tmp4 1664} 1665 1666define <4 x i32> @fcmuge4xfloat(<4 x float> %A, <4 x float> %B) { 1667; CHECK-LABEL: fcmuge4xfloat: 1668; Using registers other than v0, v1 are possible, but would be odd. 1669; UGE = ULE with swapped operands, ULE implemented as !OGT. 1670; CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s 1671; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1672 %tmp3 = fcmp uge <4 x float> %A, %B 1673 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1674 ret <4 x i32> %tmp4 1675} 1676 1677define <2 x i64> @fcmuge2xdouble(<2 x double> %A, <2 x double> %B) { 1678; CHECK-LABEL: fcmuge2xdouble: 1679; Using registers other than v0, v1 are possible, but would be odd. 1680; UGE = ULE with swapped operands, ULE implemented as !OGT. 1681; CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d 1682; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1683 %tmp3 = fcmp uge <2 x double> %A, %B 1684 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1685 ret <2 x i64> %tmp4 1686} 1687 1688define <2 x i32> @fcmugt2xfloat(<2 x float> %A, <2 x float> %B) { 1689; CHECK-LABEL: fcmugt2xfloat: 1690; Using registers other than v0, v1 are possible, but would be odd. 1691; UGT = ULT with swapped operands, ULT implemented as !OGE. 1692; CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s 1693; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1694 %tmp3 = fcmp ugt <2 x float> %A, %B 1695 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1696 ret <2 x i32> %tmp4 1697} 1698 1699define <4 x i32> @fcmugt4xfloat(<4 x float> %A, <4 x float> %B) { 1700; CHECK-LABEL: fcmugt4xfloat: 1701; Using registers other than v0, v1 are possible, but would be odd. 1702; UGT = ULT with swapped operands, ULT implemented as !OGE. 1703; CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s 1704; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1705 %tmp3 = fcmp ugt <4 x float> %A, %B 1706 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1707 ret <4 x i32> %tmp4 1708} 1709define <2 x i64> @fcmugt2xdouble(<2 x double> %A, <2 x double> %B) { 1710; CHECK-LABEL: fcmugt2xdouble: 1711; CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d 1712; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1713 %tmp3 = fcmp ugt <2 x double> %A, %B 1714 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1715 ret <2 x i64> %tmp4 1716} 1717 1718define <2 x i32> @fcmule2xfloat(<2 x float> %A, <2 x float> %B) { 1719; CHECK-LABEL: fcmule2xfloat: 1720; Using registers other than v0, v1 are possible, but would be odd. 1721; ULE implemented as !OGT. 1722; CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s 1723; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1724 %tmp3 = fcmp ule <2 x float> %A, %B 1725 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1726 ret <2 x i32> %tmp4 1727} 1728 1729define <4 x i32> @fcmule4xfloat(<4 x float> %A, <4 x float> %B) { 1730; CHECK-LABEL: fcmule4xfloat: 1731; Using registers other than v0, v1 are possible, but would be odd. 1732; ULE implemented as !OGT. 1733; CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s 1734; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1735 %tmp3 = fcmp ule <4 x float> %A, %B 1736 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1737 ret <4 x i32> %tmp4 1738} 1739define <2 x i64> @fcmule2xdouble(<2 x double> %A, <2 x double> %B) { 1740; CHECK-LABEL: fcmule2xdouble: 1741; Using registers other than v0, v1 are possible, but would be odd. 1742; ULE implemented as !OGT. 1743; CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d 1744; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1745 %tmp3 = fcmp ule <2 x double> %A, %B 1746 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1747 ret <2 x i64> %tmp4 1748} 1749 1750define <2 x i32> @fcmult2xfloat(<2 x float> %A, <2 x float> %B) { 1751; CHECK-LABEL: fcmult2xfloat: 1752; Using registers other than v0, v1 are possible, but would be odd. 1753; ULT implemented as !OGE. 1754; CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s 1755; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1756 %tmp3 = fcmp ult <2 x float> %A, %B 1757 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1758 ret <2 x i32> %tmp4 1759} 1760 1761define <4 x i32> @fcmult4xfloat(<4 x float> %A, <4 x float> %B) { 1762; CHECK-LABEL: fcmult4xfloat: 1763; Using registers other than v0, v1 are possible, but would be odd. 1764; ULT implemented as !OGE. 1765; CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s 1766; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1767 %tmp3 = fcmp ult <4 x float> %A, %B 1768 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1769 ret <4 x i32> %tmp4 1770} 1771define <2 x i64> @fcmult2xdouble(<2 x double> %A, <2 x double> %B) { 1772; CHECK-LABEL: fcmult2xdouble: 1773; Using registers other than v0, v1 are possible, but would be odd. 1774; ULT implemented as !OGE. 1775; CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d 1776; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1777 %tmp3 = fcmp ult <2 x double> %A, %B 1778 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1779 ret <2 x i64> %tmp4 1780} 1781 1782define <2 x i32> @fcmune2xfloat(<2 x float> %A, <2 x float> %B) { 1783; CHECK-LABEL: fcmune2xfloat: 1784; Using registers other than v0, v1 are possible, but would be odd. 1785; UNE = !OEQ. 1786; CHECK: fcmeq {{v[0-9]+}}.2s, v0.2s, v1.2s 1787; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1788 %tmp3 = fcmp une <2 x float> %A, %B 1789 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1790 ret <2 x i32> %tmp4 1791} 1792 1793define <4 x i32> @fcmune4xfloat(<4 x float> %A, <4 x float> %B) { 1794; CHECK-LABEL: fcmune4xfloat: 1795; Using registers other than v0, v1 are possible, but would be odd. 1796; UNE = !OEQ. 1797; CHECK: fcmeq {{v[0-9]+}}.4s, v0.4s, v1.4s 1798; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1799 %tmp3 = fcmp une <4 x float> %A, %B 1800 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1801 ret <4 x i32> %tmp4 1802} 1803define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x double> %B) { 1804; CHECK-LABEL: fcmune2xdouble: 1805; Using registers other than v0, v1 are possible, but would be odd. 1806; UNE = !OEQ. 1807; CHECK: fcmeq {{v[0-9]+}}.2d, v0.2d, v1.2d 1808; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1809 %tmp3 = fcmp une <2 x double> %A, %B 1810 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1811 ret <2 x i64> %tmp4 1812} 1813 1814define <2 x i32> @fcmoeqz2xfloat(<2 x float> %A) { 1815; CHECK-LABEL: fcmoeqz2xfloat: 1816; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1817 %tmp3 = fcmp oeq <2 x float> %A, zeroinitializer 1818 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1819 ret <2 x i32> %tmp4 1820} 1821 1822define <4 x i32> @fcmoeqz4xfloat(<4 x float> %A) { 1823; CHECK-LABEL: fcmoeqz4xfloat: 1824; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1825 %tmp3 = fcmp oeq <4 x float> %A, zeroinitializer 1826 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1827 ret <4 x i32> %tmp4 1828} 1829define <2 x i64> @fcmoeqz2xdouble(<2 x double> %A) { 1830; CHECK-LABEL: fcmoeqz2xdouble: 1831; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1832 %tmp3 = fcmp oeq <2 x double> %A, zeroinitializer 1833 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1834 ret <2 x i64> %tmp4 1835} 1836 1837 1838define <2 x i32> @fcmogez2xfloat(<2 x float> %A) { 1839; CHECK-LABEL: fcmogez2xfloat: 1840; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1841 %tmp3 = fcmp oge <2 x float> %A, zeroinitializer 1842 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1843 ret <2 x i32> %tmp4 1844} 1845 1846define <4 x i32> @fcmogez4xfloat(<4 x float> %A) { 1847; CHECK-LABEL: fcmogez4xfloat: 1848; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1849 %tmp3 = fcmp oge <4 x float> %A, zeroinitializer 1850 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1851 ret <4 x i32> %tmp4 1852} 1853define <2 x i64> @fcmogez2xdouble(<2 x double> %A) { 1854; CHECK-LABEL: fcmogez2xdouble: 1855; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1856 %tmp3 = fcmp oge <2 x double> %A, zeroinitializer 1857 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1858 ret <2 x i64> %tmp4 1859} 1860 1861define <2 x i32> @fcmogtz2xfloat(<2 x float> %A) { 1862; CHECK-LABEL: fcmogtz2xfloat: 1863; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1864 %tmp3 = fcmp ogt <2 x float> %A, zeroinitializer 1865 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1866 ret <2 x i32> %tmp4 1867} 1868 1869define <4 x i32> @fcmogtz4xfloat(<4 x float> %A) { 1870; CHECK-LABEL: fcmogtz4xfloat: 1871; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1872 %tmp3 = fcmp ogt <4 x float> %A, zeroinitializer 1873 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1874 ret <4 x i32> %tmp4 1875} 1876define <2 x i64> @fcmogtz2xdouble(<2 x double> %A) { 1877; CHECK-LABEL: fcmogtz2xdouble: 1878; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1879 %tmp3 = fcmp ogt <2 x double> %A, zeroinitializer 1880 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1881 ret <2 x i64> %tmp4 1882} 1883 1884define <2 x i32> @fcmoltz2xfloat(<2 x float> %A) { 1885; CHECK-LABEL: fcmoltz2xfloat: 1886; CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1887 %tmp3 = fcmp olt <2 x float> %A, zeroinitializer 1888 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1889 ret <2 x i32> %tmp4 1890} 1891 1892define <4 x i32> @fcmoltz4xfloat(<4 x float> %A) { 1893; CHECK-LABEL: fcmoltz4xfloat: 1894; CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1895 %tmp3 = fcmp olt <4 x float> %A, zeroinitializer 1896 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1897 ret <4 x i32> %tmp4 1898} 1899 1900define <2 x i64> @fcmoltz2xdouble(<2 x double> %A) { 1901; CHECK-LABEL: fcmoltz2xdouble: 1902; CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1903 %tmp3 = fcmp olt <2 x double> %A, zeroinitializer 1904 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1905 ret <2 x i64> %tmp4 1906} 1907 1908define <2 x i32> @fcmolez2xfloat(<2 x float> %A) { 1909; CHECK-LABEL: fcmolez2xfloat: 1910; CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1911 %tmp3 = fcmp ole <2 x float> %A, zeroinitializer 1912 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1913 ret <2 x i32> %tmp4 1914} 1915 1916define <4 x i32> @fcmolez4xfloat(<4 x float> %A) { 1917; CHECK-LABEL: fcmolez4xfloat: 1918; CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1919 %tmp3 = fcmp ole <4 x float> %A, zeroinitializer 1920 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1921 ret <4 x i32> %tmp4 1922} 1923 1924define <2 x i64> @fcmolez2xdouble(<2 x double> %A) { 1925; CHECK-LABEL: fcmolez2xdouble: 1926; CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1927 %tmp3 = fcmp ole <2 x double> %A, zeroinitializer 1928 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1929 ret <2 x i64> %tmp4 1930} 1931 1932define <2 x i32> @fcmonez2xfloat(<2 x float> %A) { 1933; CHECK-LABEL: fcmonez2xfloat: 1934; ONE with zero = OLT | OGT 1935; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1936; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1937; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1938 %tmp3 = fcmp one <2 x float> %A, zeroinitializer 1939 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1940 ret <2 x i32> %tmp4 1941} 1942 1943define <4 x i32> @fcmonez4xfloat(<4 x float> %A) { 1944; CHECK-LABEL: fcmonez4xfloat: 1945; ONE with zero = OLT | OGT 1946; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1947; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1948; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1949 %tmp3 = fcmp one <4 x float> %A, zeroinitializer 1950 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1951 ret <4 x i32> %tmp4 1952} 1953define <2 x i64> @fcmonez2xdouble(<2 x double> %A) { 1954; CHECK-LABEL: fcmonez2xdouble: 1955; ONE with zero = OLT | OGT 1956; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1957; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1958; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1959 %tmp3 = fcmp one <2 x double> %A, zeroinitializer 1960 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1961 ret <2 x i64> %tmp4 1962} 1963 1964define <2 x i32> @fcmordz2xfloat(<2 x float> %A) { 1965; CHECK-LABEL: fcmordz2xfloat: 1966; ORD with zero = OLT | OGE 1967; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1968; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 1969; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 1970 %tmp3 = fcmp ord <2 x float> %A, zeroinitializer 1971 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 1972 ret <2 x i32> %tmp4 1973} 1974 1975define <4 x i32> @fcmordz4xfloat(<4 x float> %A) { 1976; CHECK-LABEL: fcmordz4xfloat: 1977; ORD with zero = OLT | OGE 1978; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1979; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 1980; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1981 %tmp3 = fcmp ord <4 x float> %A, zeroinitializer 1982 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 1983 ret <4 x i32> %tmp4 1984} 1985define <2 x i64> @fcmordz2xdouble(<2 x double> %A) { 1986; CHECK-LABEL: fcmordz2xdouble: 1987; ORD with zero = OLT | OGE 1988; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1989; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 1990; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 1991 %tmp3 = fcmp ord <2 x double> %A, zeroinitializer 1992 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 1993 ret <2 x i64> %tmp4 1994} 1995 1996define <2 x i32> @fcmueqz2xfloat(<2 x float> %A) { 1997; CHECK-LABEL: fcmueqz2xfloat: 1998; UEQ with zero = !ONE = !(OLT |OGT) 1999; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2000; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2001; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2002; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2003 %tmp3 = fcmp ueq <2 x float> %A, zeroinitializer 2004 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2005 ret <2 x i32> %tmp4 2006} 2007 2008define <4 x i32> @fcmueqz4xfloat(<4 x float> %A) { 2009; CHECK-LABEL: fcmueqz4xfloat: 2010; UEQ with zero = !ONE = !(OLT |OGT) 2011; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2012; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2013; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2014; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2015 %tmp3 = fcmp ueq <4 x float> %A, zeroinitializer 2016 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2017 ret <4 x i32> %tmp4 2018} 2019 2020define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) { 2021; CHECK-LABEL: fcmueqz2xdouble: 2022; UEQ with zero = !ONE = !(OLT |OGT) 2023; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2024; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2025; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2026; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2027 %tmp3 = fcmp ueq <2 x double> %A, zeroinitializer 2028 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2029 ret <2 x i64> %tmp4 2030} 2031 2032define <2 x i32> @fcmugez2xfloat(<2 x float> %A) { 2033; CHECK-LABEL: fcmugez2xfloat: 2034; UGE with zero = !OLT 2035; CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2036; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2037 %tmp3 = fcmp uge <2 x float> %A, zeroinitializer 2038 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2039 ret <2 x i32> %tmp4 2040} 2041 2042define <4 x i32> @fcmugez4xfloat(<4 x float> %A) { 2043; CHECK-LABEL: fcmugez4xfloat: 2044; UGE with zero = !OLT 2045; CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2046; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2047 %tmp3 = fcmp uge <4 x float> %A, zeroinitializer 2048 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2049 ret <4 x i32> %tmp4 2050} 2051define <2 x i64> @fcmugez2xdouble(<2 x double> %A) { 2052; CHECK-LABEL: fcmugez2xdouble: 2053; UGE with zero = !OLT 2054; CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2055; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2056 %tmp3 = fcmp uge <2 x double> %A, zeroinitializer 2057 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2058 ret <2 x i64> %tmp4 2059} 2060 2061define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) { 2062; CHECK-LABEL: fcmugtz2xfloat: 2063; UGT with zero = !OLE 2064; CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2065; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2066 %tmp3 = fcmp ugt <2 x float> %A, zeroinitializer 2067 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2068 ret <2 x i32> %tmp4 2069} 2070 2071define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) { 2072; CHECK-LABEL: fcmugtz4xfloat: 2073; UGT with zero = !OLE 2074; CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2075; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2076 %tmp3 = fcmp ugt <4 x float> %A, zeroinitializer 2077 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2078 ret <4 x i32> %tmp4 2079} 2080define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) { 2081; CHECK-LABEL: fcmugtz2xdouble: 2082; UGT with zero = !OLE 2083; CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2084; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2085 %tmp3 = fcmp ugt <2 x double> %A, zeroinitializer 2086 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2087 ret <2 x i64> %tmp4 2088} 2089 2090define <2 x i32> @fcmultz2xfloat(<2 x float> %A) { 2091; CHECK-LABEL: fcmultz2xfloat: 2092; ULT with zero = !OGE 2093; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2094; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2095 %tmp3 = fcmp ult <2 x float> %A, zeroinitializer 2096 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2097 ret <2 x i32> %tmp4 2098} 2099 2100define <4 x i32> @fcmultz4xfloat(<4 x float> %A) { 2101; CHECK-LABEL: fcmultz4xfloat: 2102; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2103; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2104 %tmp3 = fcmp ult <4 x float> %A, zeroinitializer 2105 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2106 ret <4 x i32> %tmp4 2107} 2108 2109define <2 x i64> @fcmultz2xdouble(<2 x double> %A) { 2110; CHECK-LABEL: fcmultz2xdouble: 2111; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2112; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2113 %tmp3 = fcmp ult <2 x double> %A, zeroinitializer 2114 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2115 ret <2 x i64> %tmp4 2116} 2117 2118 2119define <2 x i32> @fcmulez2xfloat(<2 x float> %A) { 2120; CHECK-LABEL: fcmulez2xfloat: 2121; ULE with zero = !OGT 2122; CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2123; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2124 %tmp3 = fcmp ule <2 x float> %A, zeroinitializer 2125 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2126 ret <2 x i32> %tmp4 2127} 2128 2129define <4 x i32> @fcmulez4xfloat(<4 x float> %A) { 2130; CHECK-LABEL: fcmulez4xfloat: 2131; ULE with zero = !OGT 2132; CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2133; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2134 %tmp3 = fcmp ule <4 x float> %A, zeroinitializer 2135 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2136 ret <4 x i32> %tmp4 2137} 2138 2139define <2 x i64> @fcmulez2xdouble(<2 x double> %A) { 2140; CHECK-LABEL: fcmulez2xdouble: 2141; ULE with zero = !OGT 2142; CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2143; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2144 %tmp3 = fcmp ule <2 x double> %A, zeroinitializer 2145 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2146 ret <2 x i64> %tmp4 2147} 2148 2149define <2 x i32> @fcmunez2xfloat(<2 x float> %A) { 2150; CHECK-LABEL: fcmunez2xfloat: 2151; UNE with zero = !OEQ with zero 2152; CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2153; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2154 %tmp3 = fcmp une <2 x float> %A, zeroinitializer 2155 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2156 ret <2 x i32> %tmp4 2157} 2158 2159define <4 x i32> @fcmunez4xfloat(<4 x float> %A) { 2160; CHECK-LABEL: fcmunez4xfloat: 2161; UNE with zero = !OEQ with zero 2162; CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2163; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2164 %tmp3 = fcmp une <4 x float> %A, zeroinitializer 2165 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2166 ret <4 x i32> %tmp4 2167} 2168define <2 x i64> @fcmunez2xdouble(<2 x double> %A) { 2169; CHECK-LABEL: fcmunez2xdouble: 2170; UNE with zero = !OEQ with zero 2171; CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2172; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2173 %tmp3 = fcmp une <2 x double> %A, zeroinitializer 2174 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2175 ret <2 x i64> %tmp4 2176} 2177 2178 2179define <2 x i32> @fcmunoz2xfloat(<2 x float> %A) { 2180; CHECK-LABEL: fcmunoz2xfloat: 2181; UNO with zero = !ORD = !(OLT | OGE) 2182; CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2183; CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0.0|0}} 2184; CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2185; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 2186 %tmp3 = fcmp uno <2 x float> %A, zeroinitializer 2187 %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> 2188 ret <2 x i32> %tmp4 2189} 2190 2191define <4 x i32> @fcmunoz4xfloat(<4 x float> %A) { 2192; CHECK-LABEL: fcmunoz4xfloat: 2193; UNO with zero = !ORD = !(OLT | OGE) 2194; CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2195; CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0.0|0}} 2196; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2197; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2198 %tmp3 = fcmp uno <4 x float> %A, zeroinitializer 2199 %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> 2200 ret <4 x i32> %tmp4 2201} 2202 2203define <2 x i64> @fcmunoz2xdouble(<2 x double> %A) { 2204; CHECK-LABEL: fcmunoz2xdouble: 2205; UNO with zero = !ORD = !(OLT | OGE) 2206; CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2207; CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0.0|0}} 2208; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2209; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 2210 %tmp3 = fcmp uno <2 x double> %A, zeroinitializer 2211 %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> 2212 ret <2 x i64> %tmp4 2213 2214} 2215