1; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EL %s 2; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EB %s 3; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EL %s 4; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EB %s 5; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32R6,MIPS32R6-EL %s 6; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32R6,MIPS32R6-EB %s 7; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s 8; RUN: llc -march=mips64 -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s 9; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s 10; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s 11; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s 12; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s 13; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6,MIPS64R6-EL %s 14; RUN: llc -march=mips64 -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6,MIPS64R6-EB %s 15 16%struct.SLL = type { i64 } 17%struct.SI = type { i32 } 18%struct.SUI = type { i32 } 19 20@sll = common global %struct.SLL zeroinitializer, align 1 21@si = common global %struct.SI zeroinitializer, align 1 22@sui = common global %struct.SUI zeroinitializer, align 1 23 24define i32 @load_SI() nounwind readonly { 25entry: 26; ALL-LABEL: load_SI: 27 28; MIPS32-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 29; MIPS32-EL: lwr $[[R0]], 0($[[R1]]) 30 31; MIPS32-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 32; MIPS32-EB: lwr $[[R0]], 3($[[R1]]) 33 34; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)( 35; MIPS32R6: lw $2, 0($[[PTR]]) 36 37; MIPS64-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 38; MIPS64-EL: lwr $[[R0]], 0($[[R1]]) 39 40; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 41; MIPS64-EB: lwr $[[R0]], 3($[[R1]]) 42 43; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)( 44; MIPS64R6: lw $2, 0($[[PTR]]) 45 46 %0 = load i32, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i32 0, i32 0), align 1 47 ret i32 %0 48} 49 50define void @store_SI(i32 signext %a) nounwind { 51entry: 52; ALL-LABEL: store_SI: 53 54; MIPS32-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 55; MIPS32-EL: swr $[[R0]], 0($[[R1]]) 56 57; MIPS32-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 58; MIPS32-EB: swr $[[R0]], 3($[[R1]]) 59 60; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)( 61; MIPS32R6: sw $4, 0($[[PTR]]) 62 63; MIPS64-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 64; MIPS64-EL: swr $[[R0]], 0($[[R1]]) 65 66; MIPS64-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 67; MIPS64-EB: swr $[[R0]], 3($[[R1]]) 68 69; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)( 70; MIPS64R6: sw $4, 0($[[PTR]]) 71 72 store i32 %a, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i32 0, i32 0), align 1 73 ret void 74} 75 76define i64 @load_SLL() nounwind readonly { 77entry: 78; ALL-LABEL: load_SLL: 79 80; MIPS32-EL: lwl $2, 3($[[R1:[0-9]+]]) 81; MIPS32-EL: lwr $2, 0($[[R1]]) 82; MIPS32-EL: lwl $3, 7($[[R1:[0-9]+]]) 83; MIPS32-EL: lwr $3, 4($[[R1]]) 84 85; MIPS32-EB: lwl $2, 0($[[R1:[0-9]+]]) 86; MIPS32-EB: lwr $2, 3($[[R1]]) 87; MIPS32-EB: lwl $3, 4($[[R1:[0-9]+]]) 88; MIPS32-EB: lwr $3, 7($[[R1]]) 89 90; MIPS32R6: lw $[[PTR:[0-9]+]], %got(sll)( 91; MIPS32R6-DAG: lw $2, 0($[[PTR]]) 92; MIPS32R6-DAG: lw $3, 4($[[PTR]]) 93 94; MIPS64-EL: ldl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]]) 95; MIPS64-EL: ldr $[[R0]], 0($[[R1]]) 96 97; MIPS64-EB: ldl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 98; MIPS64-EB: ldr $[[R0]], 7($[[R1]]) 99 100; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(sll)( 101; MIPS64R6: ld $2, 0($[[PTR]]) 102 103 %0 = load i64, i64* getelementptr inbounds (%struct.SLL, %struct.SLL* @sll, i64 0, i32 0), align 1 104 ret i64 %0 105} 106 107define i64 @load_SI_sext_to_i64() nounwind readonly { 108entry: 109; ALL-LABEL: load_SI_sext_to_i64: 110 111; MIPS32-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 112; MIPS32-EL: lwr $[[R0]], 0($[[R1]]) 113 114; MIPS32-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 115; MIPS32-EB: lwr $[[R0]], 3($[[R1]]) 116 117; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)( 118; MIPS32R6-EL: lw $2, 0($[[PTR]]) 119; MIPS32R6-EL: sra $3, $2, 31 120; MIPS32R6-EB: lw $3, 0($[[PTR]]) 121; MIPS32R6-EB: sra $2, $3, 31 122 123; MIPS64-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 124; MIPS64-EL: lwr $[[R0]], 0($[[R1]]) 125 126; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 127; MIPS64-EB: lwr $[[R0]], 3($[[R1]]) 128 129; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)( 130; MIPS64R6: lw $2, 0($[[PTR]]) 131 132 %0 = load i32, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i64 0, i32 0), align 1 133 %conv = sext i32 %0 to i64 134 ret i64 %conv 135} 136 137define i64 @load_UI() nounwind readonly { 138entry: 139; ALL-LABEL: load_UI: 140 141; MIPS32-EL-DAG: lwl $[[R2:2]], 3($[[R1:[0-9]+]]) 142; MIPS32-EL-DAG: lwr $[[R2]], 0($[[R1]]) 143; MIPS32-EL-DAG: addiu $3, $zero, 0 144 145; MIPS32-EB-DAG: lwl $[[R2:3]], 0($[[R1:[0-9]+]]) 146; MIPS32-EB-DAG: lwr $[[R2]], 3($[[R1]]) 147; MIPS32-EB-DAG: addiu $2, $zero, 0 148 149; MIPS32R6: lw $[[PTR:[0-9]+]], %got(sui)( 150; MIPS32R6-EL-DAG: lw $2, 0($[[PTR]]) 151; MIPS32R6-EL-DAG: addiu $3, $zero, 0 152; MIPS32R6-EB-DAG: lw $3, 0($[[PTR]]) 153; MIPS32R6-EB-DAG: addiu $2, $zero, 0 154 155; MIPS64-EL-DAG: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 156; MIPS64-EL-DAG: lwr $[[R0]], 0($[[R1]]) 157; MIPS64-EL-DAG: daddiu $[[R2:[0-9]+]], $zero, 1 158; MIPS64-EL-DAG: dsll $[[R3:[0-9]+]], $[[R2]], 32 159; MIPS64-EL-DAG: daddiu $[[R4:[0-9]+]], $[[R3]], -1 160; MIPS64-EL-DAG: and ${{[0-9]+}}, $[[R0]], $[[R4]] 161 162; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 163; MIPS64-EB: lwr $[[R0]], 3($[[R1]]) 164 165; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(sui)( 166; MIPS64R6: lwu $2, 0($[[PTR]]) 167 168 %0 = load i32, i32* getelementptr inbounds (%struct.SUI, %struct.SUI* @sui, i64 0, i32 0), align 1 169 %conv = zext i32 %0 to i64 170 ret i64 %conv 171} 172 173define void @store_SLL(i64 %a) nounwind { 174entry: 175; ALL-LABEL: store_SLL: 176 177; MIPS32-EL-DAG: swl $[[A1:4]], 3($[[R1:[0-9]+]]) 178; MIPS32-EL-DAG: swr $[[A1]], 0($[[R1]]) 179; MIPS32-EL-DAG: swl $[[A2:5]], 7($[[R1:[0-9]+]]) 180; MIPS32-EL-DAG: swr $[[A2]], 4($[[R1]]) 181 182; MIPS32-EB-DAG: swl $[[A1:4]], 0($[[R1:[0-9]+]]) 183; MIPS32-EB-DAG: swr $[[A1]], 3($[[R1]]) 184; MIPS32-EB-DAG: swl $[[A1:5]], 4($[[R1:[0-9]+]]) 185; MIPS32-EB-DAG: swr $[[A1]], 7($[[R1]]) 186 187; MIPS32R6-DAG: lw $[[PTR:[0-9]+]], %got(sll)( 188; MIPS32R6-DAG: sw $4, 0($[[PTR]]) 189; MIPS32R6-DAG: sw $5, 4($[[PTR]]) 190 191; MIPS64-EL: sdl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]]) 192; MIPS64-EL: sdr $[[R0]], 0($[[R1]]) 193 194; MIPS64-EB: sdl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 195; MIPS64-EB: sdr $[[R0]], 7($[[R1]]) 196 197; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(sll)( 198; MIPS64R6: sd $4, 0($[[PTR]]) 199 200 store i64 %a, i64* getelementptr inbounds (%struct.SLL, %struct.SLL* @sll, i64 0, i32 0), align 1 201 ret void 202} 203 204define void @store_SI_trunc_from_i64(i32 signext %a) nounwind { 205entry: 206; ALL-LABEL: store_SI_trunc_from_i64: 207 208; MIPS32-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 209; MIPS32-EL: swr $[[R0]], 0($[[R1]]) 210 211; MIPS32-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 212; MIPS32-EB: swr $[[R0]], 3($[[R1]]) 213 214; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)( 215; MIPS32R6: sw $4, 0($[[PTR]]) 216 217; MIPS64-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 218; MIPS64-EL: swr $[[R0]], 0($[[R1]]) 219 220; MIPS64-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 221; MIPS64-EB: swr $[[R0]], 3($[[R1]]) 222 223; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)( 224; MIPS64R6: sw $4, 0($[[PTR]]) 225 226 store i32 %a, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i64 0, i32 0), align 1 227 ret void 228} 229 230; 231; Structures are simply concatenations of the members. They are unaffected by 232; endianness 233; 234 235%struct.S0 = type { i8, i8 } 236@struct_s0 = common global %struct.S0 zeroinitializer, align 1 237%struct.S1 = type { i16, i16 } 238@struct_s1 = common global %struct.S1 zeroinitializer, align 1 239%struct.S2 = type { i32, i32 } 240@struct_s2 = common global %struct.S2 zeroinitializer, align 1 241 242define void @copy_struct_S0() nounwind { 243entry: 244; ALL-LABEL: copy_struct_S0: 245 246; MIPS32-EL: lw $[[PTR:[0-9]+]], %got(struct_s0)( 247; MIPS32-EB: lw $[[PTR:[0-9]+]], %got(struct_s0)( 248; MIPS32R6: lw $[[PTR:[0-9]+]], %got(struct_s0)( 249; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)( 250; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)( 251; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)( 252 253; FIXME: We should be able to do better than this on MIPS32r6/MIPS64r6 since 254; we have unaligned halfword load/store available 255; ALL-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) 256; ALL-DAG: sb $[[R1]], 2($[[PTR]]) 257; ALL-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) 258; ALL-DAG: sb $[[R1]], 3($[[PTR]]) 259 260 %0 = load %struct.S0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 0), align 1 261 store %struct.S0 %0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 1), align 1 262 ret void 263} 264 265define void @copy_struct_S1() nounwind { 266entry: 267; ALL-LABEL: copy_struct_S1: 268 269; MIPS32-EL: lw $[[PTR:[0-9]+]], %got(struct_s1)( 270; MIPS32-EB: lw $[[PTR:[0-9]+]], %got(struct_s1)( 271; MIPS32-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) 272; MIPS32-DAG: sb $[[R1]], 4($[[PTR]]) 273; MIPS32-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) 274; MIPS32-DAG: sb $[[R1]], 5($[[PTR]]) 275; MIPS32-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]]) 276; MIPS32-DAG: sb $[[R1]], 6($[[PTR]]) 277; MIPS32-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]]) 278; MIPS32-DAG: sb $[[R1]], 7($[[PTR]]) 279 280; MIPS32R6: lw $[[PTR:[0-9]+]], %got(struct_s1)( 281; MIPS32R6-DAG: lhu $[[R1:[0-9]+]], 0($[[PTR]]) 282; MIPS32R6-DAG: sh $[[R1]], 4($[[PTR]]) 283; MIPS32R6-DAG: lhu $[[R1:[0-9]+]], 2($[[PTR]]) 284; MIPS32R6-DAG: sh $[[R1]], 6($[[PTR]]) 285 286; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)( 287; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)( 288; MIPS64-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) 289; MIPS64-DAG: sb $[[R1]], 4($[[PTR]]) 290; MIPS64-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) 291; MIPS64-DAG: sb $[[R1]], 5($[[PTR]]) 292; MIPS64-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]]) 293; MIPS64-DAG: sb $[[R1]], 6($[[PTR]]) 294; MIPS64-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]]) 295; MIPS64-DAG: sb $[[R1]], 7($[[PTR]]) 296 297; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)( 298; MIPS64R6-DAG: lhu $[[R1:[0-9]+]], 0($[[PTR]]) 299; MIPS64R6-DAG: sh $[[R1]], 4($[[PTR]]) 300; MIPS64R6-DAG: lhu $[[R1:[0-9]+]], 2($[[PTR]]) 301; MIPS64R6-DAG: sh $[[R1]], 6($[[PTR]]) 302 303 %0 = load %struct.S1, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 0), align 1 304 store %struct.S1 %0, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 1), align 1 305 ret void 306} 307 308define void @copy_struct_S2() nounwind { 309entry: 310; ALL-LABEL: copy_struct_S2: 311 312; MIPS32-EL: lw $[[PTR:[0-9]+]], %got(struct_s2)( 313; MIPS32-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) 314; MIPS32-EL-DAG: lwr $[[R1]], 0($[[PTR]]) 315; MIPS32-EL-DAG: swl $[[R1]], 11($[[PTR]]) 316; MIPS32-EL-DAG: swr $[[R1]], 8($[[PTR]]) 317; MIPS32-EL-DAG: lwl $[[R1:[0-9]+]], 7($[[PTR]]) 318; MIPS32-EL-DAG: lwr $[[R1]], 4($[[PTR]]) 319; MIPS32-EL-DAG: swl $[[R1]], 15($[[PTR]]) 320; MIPS32-EL-DAG: swr $[[R1]], 12($[[PTR]]) 321 322; MIPS32-EB: lw $[[PTR:[0-9]+]], %got(struct_s2)( 323; MIPS32-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]]) 324; MIPS32-EB-DAG: lwr $[[R1]], 3($[[PTR]]) 325; MIPS32-EB-DAG: swl $[[R1]], 8($[[PTR]]) 326; MIPS32-EB-DAG: swr $[[R1]], 11($[[PTR]]) 327; MIPS32-EB-DAG: lwl $[[R1:[0-9]+]], 4($[[PTR]]) 328; MIPS32-EB-DAG: lwr $[[R1]], 7($[[PTR]]) 329; MIPS32-EB-DAG: swl $[[R1]], 12($[[PTR]]) 330; MIPS32-EB-DAG: swr $[[R1]], 15($[[PTR]]) 331 332; MIPS32R6: lw $[[PTR:[0-9]+]], %got(struct_s2)( 333; MIPS32R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]]) 334; MIPS32R6-DAG: sw $[[R1]], 8($[[PTR]]) 335; MIPS32R6-DAG: lw $[[R1:[0-9]+]], 4($[[PTR]]) 336; MIPS32R6-DAG: sw $[[R1]], 12($[[PTR]]) 337 338; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)( 339; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) 340; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]]) 341; MIPS64-EL-DAG: swl $[[R1]], 11($[[PTR]]) 342; MIPS64-EL-DAG: swr $[[R1]], 8($[[PTR]]) 343; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 7($[[PTR]]) 344; MIPS64-EL-DAG: lwr $[[R1]], 4($[[PTR]]) 345; MIPS64-EL-DAG: swl $[[R1]], 15($[[PTR]]) 346; MIPS64-EL-DAG: swr $[[R1]], 12($[[PTR]]) 347 348; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)( 349; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]]) 350; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]]) 351; MIPS64-EB-DAG: swl $[[R1]], 8($[[PTR]]) 352; MIPS64-EB-DAG: swr $[[R1]], 11($[[PTR]]) 353; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 4($[[PTR]]) 354; MIPS64-EB-DAG: lwr $[[R1]], 7($[[PTR]]) 355; MIPS64-EB-DAG: swl $[[R1]], 12($[[PTR]]) 356; MIPS64-EB-DAG: swr $[[R1]], 15($[[PTR]]) 357 358; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)( 359; MIPS64R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]]) 360; MIPS64R6-DAG: sw $[[R1]], 8($[[PTR]]) 361; MIPS64R6-DAG: lw $[[R1:[0-9]+]], 4($[[PTR]]) 362; MIPS64R6-DAG: sw $[[R1]], 12($[[PTR]]) 363 364 %0 = load %struct.S2, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 0), align 1 365 store %struct.S2 %0, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 1), align 1 366 ret void 367} 368 369; 370; Arrays are simply concatenations of the members. They are unaffected by 371; endianness 372; 373 374@arr = common global [7 x i8] zeroinitializer, align 1 375 376define void @pass_array_byval() nounwind { 377entry: 378; ALL-LABEL: pass_array_byval: 379 380; MIPS32-EL: lw $[[SPTR:[0-9]+]], %got(arr)( 381; MIPS32-EL-DAG: lwl $[[R1:4]], 3($[[PTR]]) 382; MIPS32-EL-DAG: lwr $[[R1]], 0($[[PTR]]) 383; MIPS32-EL-DAG: lbu $[[R2:[0-9]+]], 4($[[PTR]]) 384; MIPS32-EL-DAG: lbu $[[R3:[0-9]+]], 5($[[PTR]]) 385; MIPS32-EL-DAG: sll $[[T0:[0-9]+]], $[[R3]], 8 386; MIPS32-EL-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[R2]] 387; MIPS32-EL-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]]) 388; MIPS32-EL-DAG: sll $[[T2:[0-9]+]], $[[R4]], 16 389; MIPS32-EL-DAG: or $5, $[[T1]], $[[T2]] 390 391; MIPS32-EB: lw $[[SPTR:[0-9]+]], %got(arr)( 392; MIPS32-EB-DAG: lwl $[[R1:4]], 0($[[PTR]]) 393; MIPS32-EB-DAG: lwr $[[R1]], 3($[[PTR]]) 394; MIPS32-EB-DAG: lbu $[[R2:[0-9]+]], 5($[[PTR]]) 395; MIPS32-EB-DAG: lbu $[[R3:[0-9]+]], 4($[[PTR]]) 396; MIPS32-EB-DAG: sll $[[T0:[0-9]+]], $[[R3]], 8 397; MIPS32-EB-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[R2]] 398; MIPS32-EB-DAG: sll $[[T1]], $[[T1]], 16 399; MIPS32-EB-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]]) 400; MIPS32-EB-DAG: sll $[[T2:[0-9]+]], $[[R4]], 8 401; MIPS32-EB-DAG: or $5, $[[T1]], $[[T2]] 402 403; MIPS32R6: lw $[[SPTR:[0-9]+]], %got(arr)( 404; MIPS32R6-DAG: lw $4, 0($[[PTR]]) 405; MIPS32R6-EL-DAG: lhu $[[R2:[0-9]+]], 4($[[PTR]]) 406; MIPS32R6-EL-DAG: lbu $[[R3:[0-9]+]], 6($[[PTR]]) 407; MIPS32R6-EL-DAG: sll $[[T0:[0-9]+]], $[[R3]], 16 408; MIPS32R6-EL-DAG: or $5, $[[R2]], $[[T0]] 409 410; MIPS32R6-EB-DAG: lhu $[[R2:[0-9]+]], 4($[[PTR]]) 411; MIPS32R6-EB-DAG: lbu $[[R3:[0-9]+]], 6($[[PTR]]) 412; MIPS32R6-EB-DAG: sll $[[T0:[0-9]+]], $[[R2]], 16 413; MIPS32R6-EB-DAG: or $5, $[[T0]], $[[R3]] 414 415; MIPS64-EL: ld $[[SPTR:[0-9]+]], %got_disp(arr)( 416; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) 417; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]]) 418 419; MIPS64-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)( 420; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]]) 421; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]]) 422; MIPS64-EB-DAG: dsll $[[R1]], $[[R1]], 32 423; MIPS64-EB-DAG: lbu $[[R2:[0-9]+]], 5($[[PTR]]) 424; MIPS64-EB-DAG: lbu $[[R3:[0-9]+]], 4($[[PTR]]) 425; MIPS64-EB-DAG: dsll $[[T0:[0-9]+]], $[[R3]], 8 426; MIPS64-EB-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[R2]] 427; MIPS64-EB-DAG: dsll $[[T1]], $[[T1]], 16 428; MIPS64-EB-DAG: or $[[T3:[0-9]+]], $[[R1]], $[[T1]] 429; MIPS64-EB-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]]) 430; MIPS64-EB-DAG: dsll $[[T4:[0-9]+]], $[[R4]], 8 431; MIPS64-EB-DAG: or $4, $[[T3]], $[[T4]] 432 433; MIPS64R6: ld $[[SPTR:[0-9]+]], %got_disp(arr)( 434 435 tail call void @extern_func([7 x i8]* byval @arr) nounwind 436 ret void 437} 438 439declare void @extern_func([7 x i8]* byval) 440