1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 * based on amdgpu winsys.
5 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27 #include "radv_amdgpu_winsys.h"
28 #include "radv_amdgpu_winsys_public.h"
29 #include "radv_amdgpu_surface.h"
30 #include "radv_debug.h"
31 #include "ac_surface.h"
32 #include "xf86drm.h"
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 #include "drm-uapi/amdgpu_drm.h"
37 #include <assert.h>
38 #include "radv_amdgpu_cs.h"
39 #include "radv_amdgpu_bo.h"
40 #include "radv_amdgpu_surface.h"
41
42 static bool
do_winsys_init(struct radv_amdgpu_winsys * ws,int fd)43 do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
44 {
45 if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
46 return false;
47
48 /* LLVM 11 is required for GFX10.3. */
49 if (ws->info.chip_class == GFX10_3 && ws->use_llvm && LLVM_VERSION_MAJOR < 11) {
50 fprintf(stderr, "radv: GFX 10.3 requires LLVM 11 or higher\n");
51 return false;
52 }
53
54 /* LLVM 9.0 is required for GFX10. */
55 if (ws->info.chip_class == GFX10 && ws->use_llvm && LLVM_VERSION_MAJOR < 9) {
56 fprintf(stderr, "radv: Navi family support requires LLVM 9 or higher\n");
57 return false;
58 }
59
60 /* temporary */
61 ws->info.use_display_dcc_unaligned = false;
62 ws->info.use_display_dcc_with_retile_blit = false;
63
64 ws->addrlib = ac_addrlib_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
65 if (!ws->addrlib) {
66 fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
67 return false;
68 }
69
70 ws->info.num_rings[RING_DMA] = MIN2(ws->info.num_rings[RING_DMA], MAX_RINGS_PER_TYPE);
71 ws->info.num_rings[RING_COMPUTE] = MIN2(ws->info.num_rings[RING_COMPUTE], MAX_RINGS_PER_TYPE);
72
73 ws->use_ib_bos = ws->info.chip_class >= GFX7;
74 return true;
75 }
76
radv_amdgpu_winsys_query_info(struct radeon_winsys * rws,struct radeon_info * info)77 static void radv_amdgpu_winsys_query_info(struct radeon_winsys *rws,
78 struct radeon_info *info)
79 {
80 *info = ((struct radv_amdgpu_winsys *)rws)->info;
81 }
82
radv_amdgpu_winsys_query_value(struct radeon_winsys * rws,enum radeon_value_id value)83 static uint64_t radv_amdgpu_winsys_query_value(struct radeon_winsys *rws,
84 enum radeon_value_id value)
85 {
86 struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
87 struct amdgpu_heap_info heap;
88 uint64_t retval = 0;
89
90 switch (value) {
91 case RADEON_ALLOCATED_VRAM:
92 return ws->allocated_vram;
93 case RADEON_ALLOCATED_VRAM_VIS:
94 return ws->allocated_vram_vis;
95 case RADEON_ALLOCATED_GTT:
96 return ws->allocated_gtt;
97 case RADEON_TIMESTAMP:
98 amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
99 return retval;
100 case RADEON_NUM_BYTES_MOVED:
101 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED,
102 8, &retval);
103 return retval;
104 case RADEON_NUM_EVICTIONS:
105 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS,
106 8, &retval);
107 return retval;
108 case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
109 amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS,
110 8, &retval);
111 return retval;
112 case RADEON_VRAM_USAGE:
113 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
114 0, &heap);
115 return heap.heap_usage;
116 case RADEON_VRAM_VIS_USAGE:
117 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
118 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
119 &heap);
120 return heap.heap_usage;
121 case RADEON_GTT_USAGE:
122 amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT,
123 0, &heap);
124 return heap.heap_usage;
125 case RADEON_GPU_TEMPERATURE:
126 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP,
127 4, &retval);
128 return retval;
129 case RADEON_CURRENT_SCLK:
130 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK,
131 4, &retval);
132 return retval;
133 case RADEON_CURRENT_MCLK:
134 amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK,
135 4, &retval);
136 return retval;
137 default:
138 unreachable("invalid query value");
139 }
140
141 return 0;
142 }
143
radv_amdgpu_winsys_read_registers(struct radeon_winsys * rws,unsigned reg_offset,unsigned num_registers,uint32_t * out)144 static bool radv_amdgpu_winsys_read_registers(struct radeon_winsys *rws,
145 unsigned reg_offset,
146 unsigned num_registers, uint32_t *out)
147 {
148 struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys*)rws;
149
150 return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
151 0xffffffff, 0, out) == 0;
152 }
153
radv_amdgpu_winsys_get_chip_name(struct radeon_winsys * rws)154 static const char *radv_amdgpu_winsys_get_chip_name(struct radeon_winsys *rws)
155 {
156 amdgpu_device_handle dev = ((struct radv_amdgpu_winsys *)rws)->dev;
157
158 return amdgpu_get_marketing_name(dev);
159 }
160
radv_amdgpu_winsys_destroy(struct radeon_winsys * rws)161 static void radv_amdgpu_winsys_destroy(struct radeon_winsys *rws)
162 {
163 struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys*)rws;
164
165 for (unsigned i = 0; i < ws->syncobj_count; ++i)
166 amdgpu_cs_destroy_syncobj(ws->dev, ws->syncobj[i]);
167 free(ws->syncobj);
168
169 pthread_mutex_destroy(&ws->syncobj_lock);
170 u_rwlock_destroy(&ws->global_bo_list_lock);
171 ac_addrlib_destroy(ws->addrlib);
172 amdgpu_device_deinitialize(ws->dev);
173 FREE(rws);
174 }
175
176 struct radeon_winsys *
radv_amdgpu_winsys_create(int fd,uint64_t debug_flags,uint64_t perftest_flags)177 radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, uint64_t perftest_flags)
178 {
179 uint32_t drm_major, drm_minor, r;
180 amdgpu_device_handle dev;
181 struct radv_amdgpu_winsys *ws;
182
183 r = amdgpu_device_initialize(fd, &drm_major, &drm_minor, &dev);
184 if (r)
185 return NULL;
186
187 ws = calloc(1, sizeof(struct radv_amdgpu_winsys));
188 if (!ws)
189 goto fail;
190
191 ws->dev = dev;
192 ws->info.drm_major = drm_major;
193 ws->info.drm_minor = drm_minor;
194 if (!do_winsys_init(ws, fd))
195 goto winsys_fail;
196
197 ws->debug_all_bos = !!(debug_flags & RADV_DEBUG_ALL_BOS);
198 if (debug_flags & RADV_DEBUG_NO_IBS)
199 ws->use_ib_bos = false;
200
201 ws->use_local_bos = perftest_flags & RADV_PERFTEST_LOCAL_BOS;
202 ws->zero_all_vram_allocs = debug_flags & RADV_DEBUG_ZERO_VRAM;
203 ws->use_llvm = debug_flags & RADV_DEBUG_LLVM;
204 list_inithead(&ws->global_bo_list);
205 u_rwlock_init(&ws->global_bo_list_lock);
206 pthread_mutex_init(&ws->syncobj_lock, NULL);
207 ws->base.query_info = radv_amdgpu_winsys_query_info;
208 ws->base.query_value = radv_amdgpu_winsys_query_value;
209 ws->base.read_registers = radv_amdgpu_winsys_read_registers;
210 ws->base.get_chip_name = radv_amdgpu_winsys_get_chip_name;
211 ws->base.destroy = radv_amdgpu_winsys_destroy;
212 radv_amdgpu_bo_init_functions(ws);
213 radv_amdgpu_cs_init_functions(ws);
214 radv_amdgpu_surface_init_functions(ws);
215
216 return &ws->base;
217
218 winsys_fail:
219 free(ws);
220 fail:
221 amdgpu_device_deinitialize(dev);
222 return NULL;
223 }
224