1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_prim.h"
31
32 #include "freedreno_state.h"
33 #include "freedreno_resource.h"
34
35 #include "fd5_draw.h"
36 #include "fd5_context.h"
37 #include "fd5_emit.h"
38 #include "fd5_program.h"
39 #include "fd5_format.h"
40 #include "fd5_zsa.h"
41
42
43 static void
draw_impl(struct fd_context * ctx,struct fd_ringbuffer * ring,struct fd5_emit * emit,unsigned index_offset)44 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
45 struct fd5_emit *emit, unsigned index_offset)
46 {
47 const struct pipe_draw_info *info = emit->info;
48 enum pc_di_primtype primtype = ctx->primtypes[info->mode];
49
50 fd5_emit_state(ctx, ring, emit);
51
52 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
53 fd5_emit_vertex_bufs(ring, emit);
54
55 OUT_PKT4(ring, REG_A5XX_VFD_INDEX_OFFSET, 2);
56 OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
57 OUT_RING(ring, info->start_instance); /* VFD_INSTANCE_START_OFFSET */
58
59 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
60 OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
61 info->restart_index : 0xffffffff);
62
63 fd5_emit_render_cntl(ctx, false, emit->binning_pass);
64 fd5_draw_emit(ctx->batch, ring, primtype,
65 emit->binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
66 info, index_offset);
67 }
68
69 /* fixup dirty shader state in case some "unrelated" (from the state-
70 * tracker's perspective) state change causes us to switch to a
71 * different variant.
72 */
73 static void
fixup_shader_state(struct fd_context * ctx,struct ir3_shader_key * key)74 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
75 {
76 struct fd5_context *fd5_ctx = fd5_context(ctx);
77 struct ir3_shader_key *last_key = &fd5_ctx->last_key;
78
79 if (!ir3_shader_key_equal(last_key, key)) {
80 if (ir3_shader_key_changes_fs(last_key, key)) {
81 ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
82 ctx->dirty |= FD_DIRTY_PROG;
83 }
84
85 if (ir3_shader_key_changes_vs(last_key, key)) {
86 ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
87 ctx->dirty |= FD_DIRTY_PROG;
88 }
89
90 fd5_ctx->last_key = *key;
91 }
92 }
93
94 static bool
fd5_draw_vbo(struct fd_context * ctx,const struct pipe_draw_info * info,unsigned index_offset)95 fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
96 unsigned index_offset)
97 {
98 struct fd5_context *fd5_ctx = fd5_context(ctx);
99 struct fd5_emit emit = {
100 .debug = &ctx->debug,
101 .vtx = &ctx->vtx,
102 .prog = &ctx->prog,
103 .info = info,
104 .key = {
105 .color_two_side = ctx->rasterizer->light_twoside,
106 .vclamp_color = ctx->rasterizer->clamp_vertex_color,
107 .fclamp_color = ctx->rasterizer->clamp_fragment_color,
108 .rasterflat = ctx->rasterizer->flatshade,
109 .ucp_enables = ctx->rasterizer->clip_plane_enable,
110 .has_per_samp = (fd5_ctx->fsaturate || fd5_ctx->vsaturate ||
111 fd5_ctx->fastc_srgb || fd5_ctx->vastc_srgb),
112 .vsaturate_s = fd5_ctx->vsaturate_s,
113 .vsaturate_t = fd5_ctx->vsaturate_t,
114 .vsaturate_r = fd5_ctx->vsaturate_r,
115 .fsaturate_s = fd5_ctx->fsaturate_s,
116 .fsaturate_t = fd5_ctx->fsaturate_t,
117 .fsaturate_r = fd5_ctx->fsaturate_r,
118 .vastc_srgb = fd5_ctx->vastc_srgb,
119 .fastc_srgb = fd5_ctx->fastc_srgb,
120 .vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples,
121 .fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples,
122 },
123 .rasterflat = ctx->rasterizer->flatshade,
124 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
125 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
126 };
127
128 fixup_shader_state(ctx, &emit.key);
129
130 unsigned dirty = ctx->dirty;
131 const struct ir3_shader_variant *vp = fd5_emit_get_vp(&emit);
132 const struct ir3_shader_variant *fp = fd5_emit_get_fp(&emit);
133
134 /* do regular pass first, since that is more likely to fail compiling: */
135
136 if (!vp || !fp)
137 return false;
138
139 ctx->stats.vs_regs += ir3_shader_halfregs(vp);
140 ctx->stats.fs_regs += ir3_shader_halfregs(fp);
141
142 /* figure out whether we need to disable LRZ write for binning
143 * pass using draw pass's fp:
144 */
145 emit.no_lrz_write = fp->writes_pos || fp->no_earlyz || fp->has_kill;
146
147 emit.binning_pass = false;
148 emit.dirty = dirty;
149
150 draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
151
152 /* and now binning pass: */
153 emit.binning_pass = true;
154 emit.dirty = dirty & ~(FD_DIRTY_BLEND);
155 emit.vs = NULL; /* we changed key so need to refetch vp */
156 emit.fs = NULL;
157 draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
158
159 if (emit.streamout_mask) {
160 struct fd_ringbuffer *ring = ctx->batch->draw;
161
162 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
163 if (emit.streamout_mask & (1 << i)) {
164 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
165 OUT_RING(ring, FLUSH_SO_0 + i);
166 }
167 }
168 }
169
170 fd_context_all_clean(ctx);
171
172 return true;
173 }
174
is_z32(enum pipe_format format)175 static bool is_z32(enum pipe_format format)
176 {
177 switch (format) {
178 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
179 case PIPE_FORMAT_Z32_UNORM:
180 case PIPE_FORMAT_Z32_FLOAT:
181 return true;
182 default:
183 return false;
184 }
185 }
186
187 static void
fd5_clear_lrz(struct fd_batch * batch,struct fd_resource * zsbuf,double depth)188 fd5_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
189 {
190 struct fd_ringbuffer *ring;
191 uint32_t clear = util_pack_z(PIPE_FORMAT_Z16_UNORM, depth);
192
193 ring = fd_batch_get_prologue(batch);
194
195 OUT_WFI5(ring);
196
197 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
198 OUT_RING(ring, 0x10000000);
199
200 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
201 OUT_RING(ring, 0x20fffff);
202
203 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
204 OUT_RING(ring, A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0) |
205 COND(zsbuf->base.nr_samples > 1, A5XX_GRAS_SU_CNTL_MSAA_ENABLE));
206
207 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
208 OUT_RING(ring, 0x00000000);
209
210 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
211 OUT_RING(ring, 0x00000181);
212
213 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
214 OUT_RING(ring, 0x00000000);
215
216 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
217 OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(RB5_R16_UNORM) |
218 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE5_LINEAR) |
219 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
220 OUT_RING(ring, A5XX_RB_MRT_PITCH(zsbuf->lrz_pitch * 2));
221 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf->lrz)));
222 OUT_RELOC(ring, zsbuf->lrz, 0x1000, 0, 0);
223
224 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
225 OUT_RING(ring, 0x00000000);
226
227 OUT_PKT4(ring, REG_A5XX_RB_DEST_MSAA_CNTL, 1);
228 OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE));
229
230 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
231 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0));
232
233 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
234 OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR |
235 A5XX_RB_CLEAR_CNTL_MASK(0xf));
236
237 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
238 OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */
239
240 OUT_PKT4(ring, REG_A5XX_VSC_RESOLVE_CNTL, 2);
241 OUT_RING(ring, A5XX_VSC_RESOLVE_CNTL_X(zsbuf->lrz_width) |
242 A5XX_VSC_RESOLVE_CNTL_Y(zsbuf->lrz_height));
243 OUT_RING(ring, 0x00000000); // XXX UNKNOWN_0CDE
244
245 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
246 OUT_RING(ring, A5XX_RB_CNTL_BYPASS);
247
248 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
249 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(0) |
250 A5XX_RB_RESOLVE_CNTL_1_Y(0));
251 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(zsbuf->lrz_width - 1) |
252 A5XX_RB_RESOLVE_CNTL_2_Y(zsbuf->lrz_height - 1));
253
254 fd5_emit_blit(batch->ctx, ring);
255 }
256
257 static bool
fd5_clear(struct fd_context * ctx,unsigned buffers,const union pipe_color_union * color,double depth,unsigned stencil)258 fd5_clear(struct fd_context *ctx, unsigned buffers,
259 const union pipe_color_union *color, double depth, unsigned stencil)
260 {
261 struct fd_ringbuffer *ring = ctx->batch->draw;
262 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
263
264 if ((buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) &&
265 is_z32(pfb->zsbuf->format))
266 return false;
267
268 fd5_emit_render_cntl(ctx, true, false);
269
270 if (buffers & PIPE_CLEAR_COLOR) {
271 for (int i = 0; i < pfb->nr_cbufs; i++) {
272 union util_color uc = {0};
273
274 if (!pfb->cbufs[i])
275 continue;
276
277 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
278 continue;
279
280 enum pipe_format pfmt = pfb->cbufs[i]->format;
281
282 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
283 union pipe_color_union swapped;
284 switch (fd5_pipe2swap(pfmt)) {
285 case WZYX:
286 swapped.ui[0] = color->ui[0];
287 swapped.ui[1] = color->ui[1];
288 swapped.ui[2] = color->ui[2];
289 swapped.ui[3] = color->ui[3];
290 break;
291 case WXYZ:
292 swapped.ui[2] = color->ui[0];
293 swapped.ui[1] = color->ui[1];
294 swapped.ui[0] = color->ui[2];
295 swapped.ui[3] = color->ui[3];
296 break;
297 case ZYXW:
298 swapped.ui[3] = color->ui[0];
299 swapped.ui[0] = color->ui[1];
300 swapped.ui[1] = color->ui[2];
301 swapped.ui[2] = color->ui[3];
302 break;
303 case XYZW:
304 swapped.ui[3] = color->ui[0];
305 swapped.ui[2] = color->ui[1];
306 swapped.ui[1] = color->ui[2];
307 swapped.ui[0] = color->ui[3];
308 break;
309 }
310
311 util_pack_color_union(pfmt, &uc, &swapped);
312
313 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
314 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0 + i));
315
316 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
317 OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR |
318 A5XX_RB_CLEAR_CNTL_MASK(0xf));
319
320 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 4);
321 OUT_RING(ring, uc.ui[0]); /* RB_CLEAR_COLOR_DW0 */
322 OUT_RING(ring, uc.ui[1]); /* RB_CLEAR_COLOR_DW1 */
323 OUT_RING(ring, uc.ui[2]); /* RB_CLEAR_COLOR_DW2 */
324 OUT_RING(ring, uc.ui[3]); /* RB_CLEAR_COLOR_DW3 */
325
326 fd5_emit_blit(ctx, ring);
327 }
328 }
329
330 if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) {
331 uint32_t clear =
332 util_pack_z_stencil(pfb->zsbuf->format, depth, stencil);
333 uint32_t mask = 0;
334
335 if (buffers & PIPE_CLEAR_DEPTH)
336 mask |= 0x1;
337
338 if (buffers & PIPE_CLEAR_STENCIL)
339 mask |= 0x2;
340
341 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
342 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_ZS));
343
344 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
345 OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR |
346 A5XX_RB_CLEAR_CNTL_MASK(mask));
347
348 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
349 OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */
350
351 fd5_emit_blit(ctx, ring);
352
353 if (pfb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {
354 struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
355 if (zsbuf->lrz) {
356 zsbuf->lrz_valid = true;
357 fd5_clear_lrz(ctx->batch, zsbuf, depth);
358 }
359 }
360 }
361
362 /* disable fast clear to not interfere w/ gmem->mem, etc.. */
363 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
364 OUT_RING(ring, 0x00000000); /* RB_CLEAR_CNTL */
365
366 return true;
367 }
368
369 void
fd5_draw_init(struct pipe_context * pctx)370 fd5_draw_init(struct pipe_context *pctx)
371 {
372 struct fd_context *ctx = fd_context(pctx);
373 ctx->draw_vbo = fd5_draw_vbo;
374 ctx->clear = fd5_clear;
375 }
376