1 /*
2 * Copyright (C) 2008 VMware, Inc.
3 * Copyright (C) 2014 Broadcom
4 * Copyright (C) 2018 Alyssa Rosenzweig
5 * Copyright (C) 2019 Collabora, Ltd.
6 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * SOFTWARE.
26 *
27 */
28
29 #include "util/u_debug.h"
30 #include "util/u_memory.h"
31 #include "util/format/u_format.h"
32 #include "util/format/u_format_s3tc.h"
33 #include "util/u_video.h"
34 #include "util/u_screen.h"
35 #include "util/os_time.h"
36 #include "util/u_process.h"
37 #include "pipe/p_defines.h"
38 #include "pipe/p_screen.h"
39 #include "draw/draw_context.h"
40
41 #include <fcntl.h>
42
43 #include "drm-uapi/drm_fourcc.h"
44 #include "drm-uapi/panfrost_drm.h"
45
46 #include "pan_bo.h"
47 #include "pan_screen.h"
48 #include "pan_resource.h"
49 #include "pan_public.h"
50 #include "pan_util.h"
51 #include "decode.h"
52
53 #include "pan_context.h"
54 #include "midgard/midgard_compile.h"
55 #include "bifrost/bifrost_compile.h"
56 #include "panfrost-quirks.h"
57
58 static const struct debug_named_value debug_options[] = {
59 {"msgs", PAN_DBG_MSGS, "Print debug messages"},
60 {"trace", PAN_DBG_TRACE, "Trace the command stream"},
61 {"deqp", PAN_DBG_DEQP, "Hacks for dEQP"},
62 {"afbc", PAN_DBG_AFBC, "Enable AFBC buffer sharing"},
63 {"sync", PAN_DBG_SYNC, "Wait for each job's completion and check for any GPU fault"},
64 {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
65 {"fp16", PAN_DBG_FP16, "Enable 16-bit support"},
66 {"nofp16", PAN_DBG_NOFP16, "Disable 16-bit support"},
67 {"gl3", PAN_DBG_GL3, "Enable experimental GL 3.x implementation, up to 3.3"},
68 {"noafbc", PAN_DBG_NO_AFBC, "Disable AFBC support"},
69 DEBUG_NAMED_VALUE_END
70 };
71
72 static const char *
panfrost_get_name(struct pipe_screen * screen)73 panfrost_get_name(struct pipe_screen *screen)
74 {
75 return panfrost_model_name(pan_device(screen)->gpu_id);
76 }
77
78 static const char *
panfrost_get_vendor(struct pipe_screen * screen)79 panfrost_get_vendor(struct pipe_screen *screen)
80 {
81 return "Panfrost";
82 }
83
84 static const char *
panfrost_get_device_vendor(struct pipe_screen * screen)85 panfrost_get_device_vendor(struct pipe_screen *screen)
86 {
87 return "Arm";
88 }
89
90 static int
panfrost_get_param(struct pipe_screen * screen,enum pipe_cap param)91 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
92 {
93 /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
94 struct panfrost_device *dev = pan_device(screen);
95 bool is_deqp = dev->debug & PAN_DBG_DEQP;
96
97 /* Our GL 3.x implementation is WIP */
98 bool is_gl3 = dev->debug & PAN_DBG_GL3;
99 is_gl3 |= is_deqp;
100
101 /* Don't expose MRT related CAPs on GPUs that don't implement them */
102 bool has_mrt = !(dev->quirks & MIDGARD_SFBD);
103
104 /* Bifrost is WIP. No MRT support yet. */
105 bool is_bifrost = (dev->quirks & IS_BIFROST);
106 has_mrt &= !is_bifrost || is_deqp;
107
108 switch (param) {
109 case PIPE_CAP_NPOT_TEXTURES:
110 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
111 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
112 case PIPE_CAP_VERTEX_SHADER_SATURATE:
113 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
114 case PIPE_CAP_POINT_SPRITE:
115 case PIPE_CAP_DEPTH_CLIP_DISABLE:
116 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
117 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
118 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
119 return 1;
120
121 case PIPE_CAP_MAX_RENDER_TARGETS:
122 case PIPE_CAP_FBFETCH:
123 case PIPE_CAP_FBFETCH_COHERENT:
124 return has_mrt ? 8 : 1;
125
126 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
127 return 1;
128
129 case PIPE_CAP_SAMPLE_SHADING:
130 /* WIP */
131 return is_gl3 ? 1 : 0;
132
133 case PIPE_CAP_OCCLUSION_QUERY:
134 case PIPE_CAP_PRIMITIVE_RESTART:
135 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
136 return true;
137
138 /* ES3 features unsupported on Bifrost */
139 case PIPE_CAP_TGSI_INSTANCEID:
140 case PIPE_CAP_TEXTURE_MULTISAMPLE:
141 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
142 return !is_bifrost || is_deqp;
143
144 case PIPE_CAP_SAMPLER_VIEW_TARGET:
145 case PIPE_CAP_TEXTURE_SWIZZLE:
146 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
147 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
148 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
149 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
150 case PIPE_CAP_INDEP_BLEND_ENABLE:
151 case PIPE_CAP_INDEP_BLEND_FUNC:
152 case PIPE_CAP_GENERATE_MIPMAP:
153 case PIPE_CAP_ACCELERATED:
154 case PIPE_CAP_UMA:
155 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
156 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
157 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
158 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
159 return 1;
160
161 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
162 return (is_bifrost && !is_deqp) ? 0 : 4;
163 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
164 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
165 return (is_bifrost && !is_deqp) ? 0 : 64;
166 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
167 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
168 return (is_bifrost && !is_deqp) ? 0 : 1;
169
170 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
171 return (is_bifrost && !is_deqp) ? 0 : 256;
172
173 case PIPE_CAP_GLSL_FEATURE_LEVEL:
174 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
175 return is_gl3 ? 330 : (is_bifrost && !is_deqp) ? 120 : 140;
176 case PIPE_CAP_ESSL_FEATURE_LEVEL:
177 return (is_bifrost && !is_deqp) ? 120 : 300;
178
179 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
180 return 16;
181
182 /* For faking GLES 3.1 for dEQP-GLES31 */
183 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
184 case PIPE_CAP_CUBE_MAP_ARRAY:
185 case PIPE_CAP_COMPUTE:
186 return is_deqp;
187 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
188 return is_deqp ? 65536 : 0;
189
190 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
191 case PIPE_CAP_QUERY_TIMESTAMP:
192 case PIPE_CAP_CONDITIONAL_RENDER:
193 return is_gl3;
194
195 /* TODO: Where does this req come from in practice? */
196 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
197 return 1;
198
199 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
200 return 4096;
201 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
202 return (is_bifrost && !is_deqp) ? 0 : 13;
203 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
204 return 13;
205
206 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
207 /* Hardware is natively upper left */
208 return 0;
209
210 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
211 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
212 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
213 case PIPE_CAP_TGSI_TEXCOORD:
214 return 1;
215
216 /* We would prefer varyings on Midgard, but proper sysvals on Bifrost */
217 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
218 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
219 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
220 return is_bifrost;
221
222 case PIPE_CAP_SEAMLESS_CUBE_MAP:
223 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
224 return !is_bifrost || is_deqp;
225
226 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
227 return 0xffff;
228
229 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
230 return 0;
231
232 case PIPE_CAP_ENDIANNESS:
233 return PIPE_ENDIAN_NATIVE;
234
235 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
236 return is_deqp ? 4 : 0;
237
238 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
239 return -8;
240
241 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
242 return 7;
243
244 case PIPE_CAP_VIDEO_MEMORY: {
245 uint64_t system_memory;
246
247 if (!os_get_total_physical_memory(&system_memory))
248 return 0;
249
250 return (int)(system_memory >> 20);
251 }
252
253 case PIPE_CAP_SHADER_STENCIL_EXPORT:
254 return !is_bifrost || is_deqp;
255
256 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
257 return 4;
258
259 case PIPE_CAP_MAX_VARYINGS:
260 return 16;
261
262 case PIPE_CAP_ALPHA_TEST:
263 case PIPE_CAP_FLATSHADE:
264 case PIPE_CAP_TWO_SIDED_COLOR:
265 case PIPE_CAP_CLIP_PLANES:
266 return 0;
267
268 case PIPE_CAP_PACKED_STREAM_OUTPUT:
269 return 0;
270
271 case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
272 case PIPE_CAP_PSIZ_CLAMPED:
273 return 1;
274
275 default:
276 return u_pipe_screen_get_param_defaults(screen, param);
277 }
278 }
279
280 static int
panfrost_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap param)281 panfrost_get_shader_param(struct pipe_screen *screen,
282 enum pipe_shader_type shader,
283 enum pipe_shader_cap param)
284 {
285 struct panfrost_device *dev = pan_device(screen);
286 bool is_deqp = dev->debug & PAN_DBG_DEQP;
287 bool is_fp16 = dev->debug & PAN_DBG_FP16;
288 bool is_nofp16 = dev->debug & PAN_DBG_NOFP16;
289 bool is_bifrost = dev->quirks & IS_BIFROST;
290
291 if (shader != PIPE_SHADER_VERTEX &&
292 shader != PIPE_SHADER_FRAGMENT &&
293 !(shader == PIPE_SHADER_COMPUTE && is_deqp))
294 return 0;
295
296 /* this is probably not totally correct.. but it's a start: */
297 switch (param) {
298 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
299 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
300 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
301 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
302 return 16384;
303
304 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
305 return 1024;
306
307 case PIPE_SHADER_CAP_MAX_INPUTS:
308 return 16;
309
310 case PIPE_SHADER_CAP_MAX_OUTPUTS:
311 return shader == PIPE_SHADER_FRAGMENT ? 8 : 16;
312
313 case PIPE_SHADER_CAP_MAX_TEMPS:
314 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
315
316 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
317 return 16 * 1024 * sizeof(float);
318
319 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
320 return PAN_MAX_CONST_BUFFERS;
321
322 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
323 return 0;
324
325 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
326 return (is_bifrost && !is_deqp) ? 0 : 1;
327 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
328 return 0;
329
330 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
331 return 0;
332
333 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
334 return (is_bifrost && !is_deqp) ? 0 : 1;
335
336 case PIPE_SHADER_CAP_SUBROUTINES:
337 return 0;
338
339 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
340 return 0;
341
342 case PIPE_SHADER_CAP_INTEGERS:
343 return 1;
344
345 case PIPE_SHADER_CAP_FP16:
346 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
347 return (!is_nofp16 && (!is_bifrost || is_deqp)) || is_fp16;
348
349 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
350 case PIPE_SHADER_CAP_INT16:
351 case PIPE_SHADER_CAP_INT64_ATOMICS:
352 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
353 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
354 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
355 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
356 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
357 return 0;
358
359 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
360 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
361 return 16; /* XXX: How many? */
362
363 case PIPE_SHADER_CAP_PREFERRED_IR:
364 return PIPE_SHADER_IR_NIR;
365
366 case PIPE_SHADER_CAP_SUPPORTED_IRS:
367 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
368
369 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
370 return 32;
371
372 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
373 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
374 return is_deqp ? 8 : 0;
375 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
376 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
377 return 0;
378
379 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
380 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
381 return 0;
382
383 default:
384 /* Other params are unknown */
385 return 0;
386 }
387
388 return 0;
389 }
390
391 static float
panfrost_get_paramf(struct pipe_screen * screen,enum pipe_capf param)392 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
393 {
394 switch (param) {
395 case PIPE_CAPF_MAX_LINE_WIDTH:
396
397 /* fall-through */
398 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
399 return 255.0; /* arbitrary */
400
401 case PIPE_CAPF_MAX_POINT_WIDTH:
402
403 /* fall-through */
404 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
405 return 1024.0;
406
407 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
408 return 16.0;
409
410 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
411 return 16.0; /* arbitrary */
412
413 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
414 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
415 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
416 return 0.0f;
417
418 default:
419 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
420 return 0.0;
421 }
422 }
423
424 /**
425 * Query format support for creating a texture, drawing surface, etc.
426 * \param format the format to test
427 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
428 */
429 static bool
panfrost_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bind)430 panfrost_is_format_supported( struct pipe_screen *screen,
431 enum pipe_format format,
432 enum pipe_texture_target target,
433 unsigned sample_count,
434 unsigned storage_sample_count,
435 unsigned bind)
436 {
437 struct panfrost_device *dev = pan_device(screen);
438 bool is_bifrost = (dev->quirks & IS_BIFROST);
439 const struct util_format_description *format_desc;
440
441 assert(target == PIPE_BUFFER ||
442 target == PIPE_TEXTURE_1D ||
443 target == PIPE_TEXTURE_1D_ARRAY ||
444 target == PIPE_TEXTURE_2D ||
445 target == PIPE_TEXTURE_2D_ARRAY ||
446 target == PIPE_TEXTURE_RECT ||
447 target == PIPE_TEXTURE_3D ||
448 target == PIPE_TEXTURE_CUBE ||
449 target == PIPE_TEXTURE_CUBE_ARRAY);
450
451 format_desc = util_format_description(format);
452
453 if (!format_desc)
454 return false;
455
456 /* MSAA 4x supported, but no more. Technically some revisions of the
457 * hardware can go up to 16x but we don't support higher modes yet.
458 * MSAA 2x is notably not supported and gets rounded up to MSAA 4x. */
459
460 if (!(sample_count == 0 || sample_count == 1 || sample_count == 4))
461 return false;
462
463 if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
464 return false;
465
466 /* Don't advertise multisampling on Bifrost yet */
467 if (is_bifrost && sample_count > 1)
468 return false;
469
470 /* Z16 causes dEQP failures on t720 */
471 if (format == PIPE_FORMAT_Z16_UNORM && dev->quirks & MIDGARD_SFBD)
472 return false;
473
474 /* Don't confuse poorly written apps (workaround dEQP bug) that expect
475 * more alpha than they ask for */
476
477 bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
478 bool renderable = bind & PIPE_BIND_RENDER_TARGET;
479
480 if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
481 return false;
482
483 /* Check we support the format with the given bind */
484
485 unsigned relevant_bind = bind &
486 ( PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET
487 | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_SAMPLER_VIEW);
488
489 struct panfrost_format fmt = dev->formats[format];
490 enum mali_format indexed = MALI_EXTRACT_INDEX(fmt.hw);
491
492 /* Also check that compressed texture formats are supported on this
493 * particular chip. They may not be depending on system integration
494 * differences. RGTC can be emulated so is always supported. */
495
496 bool is_rgtc = format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC;
497 bool supported = panfrost_supports_compressed_format(dev, indexed);
498
499 if (!is_rgtc && !supported)
500 return false;
501
502 return indexed && ((relevant_bind & ~fmt.bind) == 0);
503 }
504
505 /* We always support linear and tiled operations, both external and internal.
506 * We support AFBC for a subset of formats, and colourspace transform for a
507 * subset of those. */
508
509 static void
panfrost_query_dmabuf_modifiers(struct pipe_screen * screen,enum pipe_format format,int max,uint64_t * modifiers,unsigned int * external_only,int * out_count)510 panfrost_query_dmabuf_modifiers(struct pipe_screen *screen,
511 enum pipe_format format, int max, uint64_t *modifiers, unsigned
512 int *external_only, int *out_count)
513 {
514 /* Query AFBC status */
515 bool afbc = panfrost_format_supports_afbc(format);
516 bool ytr = panfrost_afbc_can_ytr(format);
517
518 /* Don't advertise AFBC before T760 */
519 struct panfrost_device *dev = pan_device(screen);
520 afbc &= !(dev->quirks & MIDGARD_NO_AFBC);
521
522 /* XXX: AFBC scanout is broken on mainline RK3399 with older kernels */
523 afbc &= (dev->debug & PAN_DBG_AFBC);
524
525 unsigned count = 0;
526
527 for (unsigned i = 0; i < PAN_MODIFIER_COUNT; ++i) {
528 if (drm_is_afbc(pan_best_modifiers[i]) && !afbc)
529 continue;
530
531 if ((pan_best_modifiers[i] & AFBC_FORMAT_MOD_YTR) && !ytr)
532 continue;
533
534 count++;
535
536 if (max > (int) count) {
537 modifiers[count] = pan_best_modifiers[i];
538
539 if (external_only)
540 external_only[count] = false;
541 }
542 }
543
544 *out_count = count;
545 }
546
547 static int
panfrost_get_compute_param(struct pipe_screen * pscreen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)548 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
549 enum pipe_compute_cap param, void *ret)
550 {
551 struct panfrost_device *dev = pan_device(pscreen);
552 const char * const ir = "panfrost";
553
554 if (!(dev->debug & PAN_DBG_DEQP))
555 return 0;
556
557 #define RET(x) do { \
558 if (ret) \
559 memcpy(ret, x, sizeof(x)); \
560 return sizeof(x); \
561 } while (0)
562
563 switch (param) {
564 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
565 RET((uint32_t []){ 64 });
566
567 case PIPE_COMPUTE_CAP_IR_TARGET:
568 if (ret)
569 sprintf(ret, "%s", ir);
570 return strlen(ir) * sizeof(char);
571
572 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
573 RET((uint64_t []) { 3 });
574
575 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
576 RET(((uint64_t []) { 65535, 65535, 65535 }));
577
578 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
579 RET(((uint64_t []) { 1024, 1024, 64 }));
580
581 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
582 RET((uint64_t []) { 1024 });
583
584 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
585 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
586
587 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
588 RET((uint64_t []) { 32768 });
589
590 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
591 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
592 RET((uint64_t []) { 4096 });
593
594 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
595 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
596
597 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
598 RET((uint32_t []) { 800 /* MHz -- TODO */ });
599
600 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
601 RET((uint32_t []) { 9999 }); // TODO
602
603 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
604 RET((uint32_t []) { 1 }); // TODO
605
606 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
607 RET((uint32_t []) { 32 }); // TODO
608
609 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
610 RET((uint64_t []) { 1024 }); // TODO
611 }
612
613 return 0;
614 }
615
616 static void
panfrost_destroy_screen(struct pipe_screen * pscreen)617 panfrost_destroy_screen(struct pipe_screen *pscreen)
618 {
619 panfrost_close_device(pan_device(pscreen));
620 ralloc_free(pscreen);
621 }
622
623 static uint64_t
panfrost_get_timestamp(struct pipe_screen * _screen)624 panfrost_get_timestamp(struct pipe_screen *_screen)
625 {
626 return os_time_get_nano();
627 }
628
629 static void
panfrost_fence_reference(struct pipe_screen * pscreen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * fence)630 panfrost_fence_reference(struct pipe_screen *pscreen,
631 struct pipe_fence_handle **ptr,
632 struct pipe_fence_handle *fence)
633 {
634 struct panfrost_device *dev = pan_device(pscreen);
635 struct panfrost_fence **p = (struct panfrost_fence **)ptr;
636 struct panfrost_fence *f = (struct panfrost_fence *)fence;
637 struct panfrost_fence *old = *p;
638
639 if (pipe_reference(&(*p)->reference, &f->reference)) {
640 drmSyncobjDestroy(dev->fd, old->syncobj);
641 free(old);
642 }
643 *p = f;
644 }
645
646 static bool
panfrost_fence_finish(struct pipe_screen * pscreen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)647 panfrost_fence_finish(struct pipe_screen *pscreen,
648 struct pipe_context *ctx,
649 struct pipe_fence_handle *fence,
650 uint64_t timeout)
651 {
652 struct panfrost_device *dev = pan_device(pscreen);
653 struct panfrost_fence *f = (struct panfrost_fence *)fence;
654 int ret;
655
656 if (f->signaled)
657 return true;
658
659 uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
660 if (abs_timeout == OS_TIMEOUT_INFINITE)
661 abs_timeout = INT64_MAX;
662
663 ret = drmSyncobjWait(dev->fd, &f->syncobj,
664 1,
665 abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
666 NULL);
667
668 f->signaled = (ret >= 0);
669 return f->signaled;
670 }
671
672 struct panfrost_fence *
panfrost_fence_create(struct panfrost_context * ctx)673 panfrost_fence_create(struct panfrost_context *ctx)
674 {
675 struct panfrost_fence *f = calloc(1, sizeof(*f));
676 if (!f)
677 return NULL;
678
679 struct panfrost_device *dev = pan_device(ctx->base.screen);
680 int fd = -1, ret;
681
682 /* Snapshot the last rendering out fence. We'd rather have another
683 * syncobj instead of a sync file, but this is all we get.
684 * (HandleToFD/FDToHandle just gives you another syncobj ID for the
685 * same syncobj).
686 */
687 ret = drmSyncobjExportSyncFile(dev->fd, ctx->syncobj, &fd);
688 if (ret || fd == -1) {
689 fprintf(stderr, "export failed\n");
690 goto err_free_fence;
691 }
692
693 ret = drmSyncobjCreate(dev->fd, 0, &f->syncobj);
694 if (ret) {
695 fprintf(stderr, "create syncobj failed\n");
696 goto err_close_fd;
697 }
698
699 ret = drmSyncobjImportSyncFile(dev->fd, f->syncobj, fd);
700 if (ret) {
701 fprintf(stderr, "create syncobj failed\n");
702 goto err_destroy_syncobj;
703 }
704
705 assert(f->syncobj != ctx->syncobj);
706 close(fd);
707 pipe_reference_init(&f->reference, 1);
708
709 return f;
710
711 err_destroy_syncobj:
712 drmSyncobjDestroy(dev->fd, f->syncobj);
713 err_close_fd:
714 close(fd);
715 err_free_fence:
716 free(f);
717 return NULL;
718 }
719
720 static const void *
panfrost_screen_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)721 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
722 enum pipe_shader_ir ir,
723 enum pipe_shader_type shader)
724 {
725 if (pan_device(pscreen)->quirks & IS_BIFROST)
726 return &bifrost_nir_options;
727 else
728 return &midgard_nir_options;
729 }
730
731 struct pipe_screen *
panfrost_create_screen(int fd,struct renderonly * ro)732 panfrost_create_screen(int fd, struct renderonly *ro)
733 {
734 /* Create the screen */
735 struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
736
737 if (!screen)
738 return NULL;
739
740 struct panfrost_device *dev = pan_device(&screen->base);
741 panfrost_open_device(screen, fd, dev);
742
743 dev->debug = debug_get_flags_option("PAN_MESA_DEBUG", debug_options, 0);
744
745 if (dev->debug & PAN_DBG_NO_AFBC)
746 dev->quirks |= MIDGARD_NO_AFBC;
747
748 if (ro) {
749 dev->ro = renderonly_dup(ro);
750 if (!dev->ro) {
751 if (dev->debug & PAN_DBG_MSGS)
752 fprintf(stderr, "Failed to dup renderonly object\n");
753
754 free(screen);
755 return NULL;
756 }
757 }
758
759 /* Check if we're loading against a supported GPU model. */
760
761 switch (dev->gpu_id) {
762 case 0x720: /* T720 */
763 case 0x750: /* T760 */
764 case 0x820: /* T820 */
765 case 0x860: /* T860 */
766 case 0x6221: /* G72 */
767 case 0x7093: /* G31 */
768 case 0x7212: /* G52 */
769 break;
770 default:
771 /* Fail to load against untested models */
772 debug_printf("panfrost: Unsupported model %X", dev->gpu_id);
773 panfrost_destroy_screen(&(screen->base));
774 return NULL;
775 }
776
777 if (dev->debug & (PAN_DBG_TRACE | PAN_DBG_SYNC))
778 pandecode_initialize(!(dev->debug & PAN_DBG_TRACE));
779
780 screen->base.destroy = panfrost_destroy_screen;
781
782 screen->base.get_name = panfrost_get_name;
783 screen->base.get_vendor = panfrost_get_vendor;
784 screen->base.get_device_vendor = panfrost_get_device_vendor;
785 screen->base.get_param = panfrost_get_param;
786 screen->base.get_shader_param = panfrost_get_shader_param;
787 screen->base.get_compute_param = panfrost_get_compute_param;
788 screen->base.get_paramf = panfrost_get_paramf;
789 screen->base.get_timestamp = panfrost_get_timestamp;
790 screen->base.is_format_supported = panfrost_is_format_supported;
791 screen->base.query_dmabuf_modifiers = panfrost_query_dmabuf_modifiers;
792 screen->base.context_create = panfrost_create_context;
793 screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
794 screen->base.fence_reference = panfrost_fence_reference;
795 screen->base.fence_finish = panfrost_fence_finish;
796 screen->base.set_damage_region = panfrost_resource_set_damage_region;
797
798 panfrost_resource_screen_init(&screen->base);
799 panfrost_init_blit_shaders(dev);
800
801 return &screen->base;
802 }
803