1# Copyright (C) 2016 Intel Corporation. All Rights Reserved. 2# 3# Permission is hereby granted, free of charge, to any person obtaining a 4# copy of this software and associated documentation files (the "Software"), 5# to deal in the Software without restriction, including without limitation 6# the rights to use, copy, modify, merge, publish, distribute, sublicense, 7# and/or sell copies of the Software, and to permit persons to whom the 8# Software is furnished to do so, subject to the following conditions: 9# 10# The above copyright notice and this permission notice (including the next 11# paragraph) shall be included in all copies or substantial portions of the 12# Software. 13# 14# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 20# IN THE SOFTWARE. 21# 22# Provides definitions for events. 23 24enum AR_DRAW_TYPE 25{ 26 Instanced = 0, 27 IndexedInstanced = 1, 28 InstancedSplit = 2, 29 IndexedInstancedSplit = 3 30}; 31 32event Framework::ThreadStartApiEvent 33{ 34}; 35 36event Framework::ThreadStartWorkerEvent 37{ 38}; 39 40///@brief Used as a helper event to indicate end of frame. Does not gaurantee to capture end of frame on all APIs 41event ApiSwr::FrameEndEvent 42{ 43 uint32_t frameId; // current frame id 44 uint32_t nextDrawId; // next draw id (always incremental - does not reset) 45}; 46 47///@brief Synchonization event. 48event ApiSwr::SwrSyncEvent 49{ 50 uint32_t drawId; 51}; 52 53///@brief Invalidate hot tiles (i.e. tile cache) 54event ApiSwr::SwrInvalidateTilesEvent 55{ 56 uint32_t drawId; 57}; 58 59///@brief Invalidate and discard hot tiles within pixel region 60event ApiSwr::SwrDiscardRectEvent 61{ 62 uint32_t drawId; 63}; 64 65///@brief Flush tiles out to memory that is typically owned by driver (e.g. Flush RT cache) 66event ApiSwr::SwrStoreTilesEvent 67{ 68 uint32_t drawId; 69}; 70 71event PipelineStats::DrawInfoEvent 72{ 73 uint32_t drawId; 74 AR_DRAW_TYPE type; // type of draw (indexed, instanced, etc) 75 uint32_t topology; // topology of draw 76 uint32_t numVertices; // number of vertices for draw 77 uint32_t numIndices; // number of indices for draw 78 int32_t indexOffset; // offset into index buffer 79 int32_t baseVertex; // which vertex to start with 80 uint32_t numInstances; // number of instances to draw 81 uint32_t startInstance; // which instance to start fetching 82 uint32_t tsEnable; // tesselation enabled 83 uint32_t gsEnable; // geometry shader enabled 84 uint32_t soEnable; // stream-out enabled 85 uint32_t soTopology; // topology of stream-out 86 uint32_t splitId; // split draw count or id 87}; 88 89event PipelineStats::DispatchEvent 90{ 91 uint32_t drawId; 92 uint32_t threadGroupCountX; // num thread groups in X dimension 93 uint32_t threadGroupCountY; // num thread groups in Y dimension 94 uint32_t threadGroupCountZ; // num thread groups in Z dimension 95}; 96 97event PipelineStats::FrontendStatsEvent 98{ 99 uint32_t drawId; 100 uint64_t IaVertices; 101 uint64_t IaPrimitives; 102 uint64_t VsInvocations; 103 uint64_t HsInvocations; 104 uint64_t DsInvocations; 105 uint64_t GsInvocations; 106 uint64_t GsPrimitives; 107 uint64_t CInvocations; 108 uint64_t CPrimitives; 109 uint64_t SoPrimStorageNeeded0; 110 uint64_t SoPrimStorageNeeded1; 111 uint64_t SoPrimStorageNeeded2; 112 uint64_t SoPrimStorageNeeded3; 113 uint64_t SoNumPrimsWritten0; 114 uint64_t SoNumPrimsWritten1; 115 uint64_t SoNumPrimsWritten2; 116 uint64_t SoNumPrimsWritten3; 117}; 118 119event PipelineStats::BackendStatsEvent 120{ 121 uint32_t drawId; 122 uint64_t DepthPassCount; 123 uint64_t PsInvocations; 124 uint64_t CsInvocations; 125 126}; 127 128event PipelineStats::EarlyZSingleSample 129{ 130 uint32_t drawId; 131 uint64_t passCount; 132 uint64_t failCount; 133}; 134 135event PipelineStats::LateZSingleSample 136{ 137 uint32_t drawId; 138 uint64_t passCount; 139 uint64_t failCount; 140}; 141 142event PipelineStats::EarlyStencilSingleSample 143{ 144 uint32_t drawId; 145 uint64_t passCount; 146 uint64_t failCount; 147}; 148 149event PipelineStats::LateStencilSingleSample 150{ 151 uint32_t drawId; 152 uint64_t passCount; 153 uint64_t failCount; 154}; 155 156event PipelineStats::EarlyZSampleRate 157{ 158 uint32_t drawId; 159 uint64_t passCount; 160 uint64_t failCount; 161}; 162 163event PipelineStats::LateZSampleRate 164{ 165 uint32_t drawId; 166 uint64_t passCount; 167 uint64_t failCount; 168}; 169 170event PipelineStats::EarlyStencilSampleRate 171{ 172 uint32_t drawId; 173 uint64_t passCount; 174 uint64_t failCount; 175}; 176 177event PipelineStats::LateStencilSampleRate 178{ 179 uint32_t drawId; 180 uint64_t passCount; 181 uint64_t failCount; 182}; 183 184// Total Early-Z counts, SingleSample and SampleRate 185event PipelineStats::EarlyZ 186{ 187 uint32_t drawId; 188 uint64_t passCount; 189 uint64_t failCount; 190}; 191 192// Total LateZ counts, SingleSample and SampleRate 193event PipelineStats::LateZ 194{ 195 uint32_t drawId; 196 uint64_t passCount; 197 uint64_t failCount; 198}; 199 200// Total EarlyStencil counts, SingleSample and SampleRate 201event PipelineStats::EarlyStencil 202{ 203 uint32_t drawId; 204 uint64_t passCount; 205 uint64_t failCount; 206}; 207 208// Total LateStencil counts, SingleSample and SampleRate 209event PipelineStats::LateStencil 210{ 211 uint32_t drawId; 212 uint64_t passCount; 213 uint64_t failCount; 214}; 215 216event PipelineStats::EarlyZNullPS 217{ 218 uint32_t drawId; 219 uint64_t passCount; 220 uint64_t failCount; 221}; 222 223event PipelineStats::EarlyStencilNullPS 224{ 225 uint32_t drawId; 226 uint64_t passCount; 227 uint64_t failCount; 228}; 229 230event PipelineStats::EarlyZPixelRate 231{ 232 uint32_t drawId; 233 uint64_t passCount; 234 uint64_t failCount; 235}; 236 237event PipelineStats::LateZPixelRate 238{ 239 uint32_t drawId; 240 uint64_t passCount; 241 uint64_t failCount; 242}; 243 244 245event PipelineStats::EarlyOmZ 246{ 247 uint32_t drawId; 248 uint64_t passCount; 249 uint64_t failCount; 250}; 251 252event PipelineStats::EarlyOmStencil 253{ 254 uint32_t drawId; 255 uint64_t passCount; 256 uint64_t failCount; 257}; 258 259event PipelineStats::LateOmZ 260{ 261 uint32_t drawId; 262 uint64_t passCount; 263 uint64_t failCount; 264}; 265 266event PipelineStats::LateOmStencil 267{ 268 uint32_t drawId; 269 uint64_t passCount; 270 uint64_t failCount; 271}; 272 273event PipelineStats::GSInputPrims 274{ 275 uint32_t drawId; 276 uint64_t inputPrimCount; 277}; 278 279event PipelineStats::GSPrimsGen 280{ 281 uint32_t drawId; 282 uint64_t primGeneratedCount; 283}; 284 285event PipelineStats::GSVertsInput 286{ 287 uint32_t drawId; 288 uint64_t vertsInput; 289}; 290 291event PipelineStats::TessPrims 292{ 293 uint32_t drawId; 294 uint64_t primCount; 295}; 296 297event PipelineStats::RasterTiles 298{ 299 uint32_t drawId; 300 uint32_t rastTileCount; 301}; 302 303event PipelineStats::ClipperEvent 304{ 305 uint32_t drawId; 306 uint32_t trivialRejectCount; 307 uint32_t trivialAcceptCount; 308 uint32_t mustClipCount; 309}; 310 311event PipelineStats::CullEvent 312{ 313 uint32_t drawId; 314 uint64_t backfacePrimCount; 315 uint64_t degeneratePrimCount; 316}; 317 318event PipelineStats::AlphaEvent 319{ 320 uint32_t drawId; 321 uint32_t alphaTestCount; 322 uint32_t alphaBlendCount; 323}; 324 325event ShaderStats::VSInfo 326{ 327 uint32_t drawId; 328 uint32_t numInstExecuted; 329 uint32_t numSampleExecuted; 330 uint32_t numSampleLExecuted; 331 uint32_t numSampleBExecuted; 332 uint32_t numSampleCExecuted; 333 uint32_t numSampleCLZExecuted; 334 uint32_t numSampleCDExecuted; 335 uint32_t numGather4Executed; 336 uint32_t numGather4CExecuted; 337 uint32_t numGather4CPOExecuted; 338 uint32_t numGather4CPOCExecuted; 339 uint32_t numLodExecuted; 340}; 341 342event ShaderStats::HSInfo 343{ 344 uint32_t drawId; 345 uint32_t numInstExecuted; 346 uint32_t numSampleExecuted; 347 uint32_t numSampleLExecuted; 348 uint32_t numSampleBExecuted; 349 uint32_t numSampleCExecuted; 350 uint32_t numSampleCLZExecuted; 351 uint32_t numSampleCDExecuted; 352 uint32_t numGather4Executed; 353 uint32_t numGather4CExecuted; 354 uint32_t numGather4CPOExecuted; 355 uint32_t numGather4CPOCExecuted; 356 uint32_t numLodExecuted; 357}; 358 359event ShaderStats::DSInfo 360{ 361 uint32_t drawId; 362 uint32_t numInstExecuted; 363 uint32_t numSampleExecuted; 364 uint32_t numSampleLExecuted; 365 uint32_t numSampleBExecuted; 366 uint32_t numSampleCExecuted; 367 uint32_t numSampleCLZExecuted; 368 uint32_t numSampleCDExecuted; 369 uint32_t numGather4Executed; 370 uint32_t numGather4CExecuted; 371 uint32_t numGather4CPOExecuted; 372 uint32_t numGather4CPOCExecuted; 373 uint32_t numLodExecuted; 374}; 375 376event ShaderStats::GSInfo 377{ 378 uint32_t drawId; 379 uint32_t numInstExecuted; 380 uint32_t numSampleExecuted; 381 uint32_t numSampleLExecuted; 382 uint32_t numSampleBExecuted; 383 uint32_t numSampleCExecuted; 384 uint32_t numSampleCLZExecuted; 385 uint32_t numSampleCDExecuted; 386 uint32_t numGather4Executed; 387 uint32_t numGather4CExecuted; 388 uint32_t numGather4CPOExecuted; 389 uint32_t numGather4CPOCExecuted; 390 uint32_t numLodExecuted; 391 392}; 393 394event ShaderStats::PSInfo 395{ 396 uint32_t drawId; 397 uint32_t numInstExecuted; 398 uint32_t numSampleExecuted; 399 uint32_t numSampleLExecuted; 400 uint32_t numSampleBExecuted; 401 uint32_t numSampleCExecuted; 402 uint32_t numSampleCLZExecuted; 403 uint32_t numSampleCDExecuted; 404 uint32_t numGather4Executed; 405 uint32_t numGather4CExecuted; 406 uint32_t numGather4CPOExecuted; 407 uint32_t numGather4CPOCExecuted; 408 uint32_t numLodExecuted; 409}; 410 411event ShaderStats::CSInfo 412{ 413 uint32_t drawId; 414 uint32_t numInstExecuted; 415 uint32_t numSampleExecuted; 416 uint32_t numSampleLExecuted; 417 uint32_t numSampleBExecuted; 418 uint32_t numSampleCExecuted; 419 uint32_t numSampleCLZExecuted; 420 uint32_t numSampleCDExecuted; 421 uint32_t numGather4Executed; 422 uint32_t numGather4CExecuted; 423 uint32_t numGather4CPOExecuted; 424 uint32_t numGather4CPOCExecuted; 425 uint32_t numLodExecuted; 426}; 427 428