• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Target Register Enum Values                                                *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass MipsMCRegisterClasses[];
17
18namespace Mips {
19enum {
20  NoRegister,
21  AT = 1,
22  DSPCCond = 2,
23  DSPCarry = 3,
24  DSPEFI = 4,
25  DSPOutFlag = 5,
26  DSPPos = 6,
27  DSPSCount = 7,
28  FP = 8,
29  GP = 9,
30  MSAAccess = 10,
31  MSACSR = 11,
32  MSAIR = 12,
33  MSAMap = 13,
34  MSAModify = 14,
35  MSARequest = 15,
36  MSASave = 16,
37  MSAUnmap = 17,
38  PC = 18,
39  RA = 19,
40  SP = 20,
41  ZERO = 21,
42  A0 = 22,
43  A1 = 23,
44  A2 = 24,
45  A3 = 25,
46  AC0 = 26,
47  AC1 = 27,
48  AC2 = 28,
49  AC3 = 29,
50  AT_64 = 30,
51  COP00 = 31,
52  COP01 = 32,
53  COP02 = 33,
54  COP03 = 34,
55  COP04 = 35,
56  COP05 = 36,
57  COP06 = 37,
58  COP07 = 38,
59  COP08 = 39,
60  COP09 = 40,
61  COP20 = 41,
62  COP21 = 42,
63  COP22 = 43,
64  COP23 = 44,
65  COP24 = 45,
66  COP25 = 46,
67  COP26 = 47,
68  COP27 = 48,
69  COP28 = 49,
70  COP29 = 50,
71  COP30 = 51,
72  COP31 = 52,
73  COP32 = 53,
74  COP33 = 54,
75  COP34 = 55,
76  COP35 = 56,
77  COP36 = 57,
78  COP37 = 58,
79  COP38 = 59,
80  COP39 = 60,
81  COP010 = 61,
82  COP011 = 62,
83  COP012 = 63,
84  COP013 = 64,
85  COP014 = 65,
86  COP015 = 66,
87  COP016 = 67,
88  COP017 = 68,
89  COP018 = 69,
90  COP019 = 70,
91  COP020 = 71,
92  COP021 = 72,
93  COP022 = 73,
94  COP023 = 74,
95  COP024 = 75,
96  COP025 = 76,
97  COP026 = 77,
98  COP027 = 78,
99  COP028 = 79,
100  COP029 = 80,
101  COP030 = 81,
102  COP031 = 82,
103  COP210 = 83,
104  COP211 = 84,
105  COP212 = 85,
106  COP213 = 86,
107  COP214 = 87,
108  COP215 = 88,
109  COP216 = 89,
110  COP217 = 90,
111  COP218 = 91,
112  COP219 = 92,
113  COP220 = 93,
114  COP221 = 94,
115  COP222 = 95,
116  COP223 = 96,
117  COP224 = 97,
118  COP225 = 98,
119  COP226 = 99,
120  COP227 = 100,
121  COP228 = 101,
122  COP229 = 102,
123  COP230 = 103,
124  COP231 = 104,
125  COP310 = 105,
126  COP311 = 106,
127  COP312 = 107,
128  COP313 = 108,
129  COP314 = 109,
130  COP315 = 110,
131  COP316 = 111,
132  COP317 = 112,
133  COP318 = 113,
134  COP319 = 114,
135  COP320 = 115,
136  COP321 = 116,
137  COP322 = 117,
138  COP323 = 118,
139  COP324 = 119,
140  COP325 = 120,
141  COP326 = 121,
142  COP327 = 122,
143  COP328 = 123,
144  COP329 = 124,
145  COP330 = 125,
146  COP331 = 126,
147  D0 = 127,
148  D1 = 128,
149  D2 = 129,
150  D3 = 130,
151  D4 = 131,
152  D5 = 132,
153  D6 = 133,
154  D7 = 134,
155  D8 = 135,
156  D9 = 136,
157  D10 = 137,
158  D11 = 138,
159  D12 = 139,
160  D13 = 140,
161  D14 = 141,
162  D15 = 142,
163  DSPOutFlag20 = 143,
164  DSPOutFlag21 = 144,
165  DSPOutFlag22 = 145,
166  DSPOutFlag23 = 146,
167  F0 = 147,
168  F1 = 148,
169  F2 = 149,
170  F3 = 150,
171  F4 = 151,
172  F5 = 152,
173  F6 = 153,
174  F7 = 154,
175  F8 = 155,
176  F9 = 156,
177  F10 = 157,
178  F11 = 158,
179  F12 = 159,
180  F13 = 160,
181  F14 = 161,
182  F15 = 162,
183  F16 = 163,
184  F17 = 164,
185  F18 = 165,
186  F19 = 166,
187  F20 = 167,
188  F21 = 168,
189  F22 = 169,
190  F23 = 170,
191  F24 = 171,
192  F25 = 172,
193  F26 = 173,
194  F27 = 174,
195  F28 = 175,
196  F29 = 176,
197  F30 = 177,
198  F31 = 178,
199  FCC0 = 179,
200  FCC1 = 180,
201  FCC2 = 181,
202  FCC3 = 182,
203  FCC4 = 183,
204  FCC5 = 184,
205  FCC6 = 185,
206  FCC7 = 186,
207  FCR0 = 187,
208  FCR1 = 188,
209  FCR2 = 189,
210  FCR3 = 190,
211  FCR4 = 191,
212  FCR5 = 192,
213  FCR6 = 193,
214  FCR7 = 194,
215  FCR8 = 195,
216  FCR9 = 196,
217  FCR10 = 197,
218  FCR11 = 198,
219  FCR12 = 199,
220  FCR13 = 200,
221  FCR14 = 201,
222  FCR15 = 202,
223  FCR16 = 203,
224  FCR17 = 204,
225  FCR18 = 205,
226  FCR19 = 206,
227  FCR20 = 207,
228  FCR21 = 208,
229  FCR22 = 209,
230  FCR23 = 210,
231  FCR24 = 211,
232  FCR25 = 212,
233  FCR26 = 213,
234  FCR27 = 214,
235  FCR28 = 215,
236  FCR29 = 216,
237  FCR30 = 217,
238  FCR31 = 218,
239  FP_64 = 219,
240  F_HI0 = 220,
241  F_HI1 = 221,
242  F_HI2 = 222,
243  F_HI3 = 223,
244  F_HI4 = 224,
245  F_HI5 = 225,
246  F_HI6 = 226,
247  F_HI7 = 227,
248  F_HI8 = 228,
249  F_HI9 = 229,
250  F_HI10 = 230,
251  F_HI11 = 231,
252  F_HI12 = 232,
253  F_HI13 = 233,
254  F_HI14 = 234,
255  F_HI15 = 235,
256  F_HI16 = 236,
257  F_HI17 = 237,
258  F_HI18 = 238,
259  F_HI19 = 239,
260  F_HI20 = 240,
261  F_HI21 = 241,
262  F_HI22 = 242,
263  F_HI23 = 243,
264  F_HI24 = 244,
265  F_HI25 = 245,
266  F_HI26 = 246,
267  F_HI27 = 247,
268  F_HI28 = 248,
269  F_HI29 = 249,
270  F_HI30 = 250,
271  F_HI31 = 251,
272  GP_64 = 252,
273  HI0 = 253,
274  HI1 = 254,
275  HI2 = 255,
276  HI3 = 256,
277  HWR0 = 257,
278  HWR1 = 258,
279  HWR2 = 259,
280  HWR3 = 260,
281  HWR4 = 261,
282  HWR5 = 262,
283  HWR6 = 263,
284  HWR7 = 264,
285  HWR8 = 265,
286  HWR9 = 266,
287  HWR10 = 267,
288  HWR11 = 268,
289  HWR12 = 269,
290  HWR13 = 270,
291  HWR14 = 271,
292  HWR15 = 272,
293  HWR16 = 273,
294  HWR17 = 274,
295  HWR18 = 275,
296  HWR19 = 276,
297  HWR20 = 277,
298  HWR21 = 278,
299  HWR22 = 279,
300  HWR23 = 280,
301  HWR24 = 281,
302  HWR25 = 282,
303  HWR26 = 283,
304  HWR27 = 284,
305  HWR28 = 285,
306  HWR29 = 286,
307  HWR30 = 287,
308  HWR31 = 288,
309  K0 = 289,
310  K1 = 290,
311  LO0 = 291,
312  LO1 = 292,
313  LO2 = 293,
314  LO3 = 294,
315  MPL0 = 295,
316  MPL1 = 296,
317  MPL2 = 297,
318  MSA8 = 298,
319  MSA9 = 299,
320  MSA10 = 300,
321  MSA11 = 301,
322  MSA12 = 302,
323  MSA13 = 303,
324  MSA14 = 304,
325  MSA15 = 305,
326  MSA16 = 306,
327  MSA17 = 307,
328  MSA18 = 308,
329  MSA19 = 309,
330  MSA20 = 310,
331  MSA21 = 311,
332  MSA22 = 312,
333  MSA23 = 313,
334  MSA24 = 314,
335  MSA25 = 315,
336  MSA26 = 316,
337  MSA27 = 317,
338  MSA28 = 318,
339  MSA29 = 319,
340  MSA30 = 320,
341  MSA31 = 321,
342  P0 = 322,
343  P1 = 323,
344  P2 = 324,
345  RA_64 = 325,
346  S0 = 326,
347  S1 = 327,
348  S2 = 328,
349  S3 = 329,
350  S4 = 330,
351  S5 = 331,
352  S6 = 332,
353  S7 = 333,
354  SP_64 = 334,
355  T0 = 335,
356  T1 = 336,
357  T2 = 337,
358  T3 = 338,
359  T4 = 339,
360  T5 = 340,
361  T6 = 341,
362  T7 = 342,
363  T8 = 343,
364  T9 = 344,
365  V0 = 345,
366  V1 = 346,
367  W0 = 347,
368  W1 = 348,
369  W2 = 349,
370  W3 = 350,
371  W4 = 351,
372  W5 = 352,
373  W6 = 353,
374  W7 = 354,
375  W8 = 355,
376  W9 = 356,
377  W10 = 357,
378  W11 = 358,
379  W12 = 359,
380  W13 = 360,
381  W14 = 361,
382  W15 = 362,
383  W16 = 363,
384  W17 = 364,
385  W18 = 365,
386  W19 = 366,
387  W20 = 367,
388  W21 = 368,
389  W22 = 369,
390  W23 = 370,
391  W24 = 371,
392  W25 = 372,
393  W26 = 373,
394  W27 = 374,
395  W28 = 375,
396  W29 = 376,
397  W30 = 377,
398  W31 = 378,
399  ZERO_64 = 379,
400  A0_64 = 380,
401  A1_64 = 381,
402  A2_64 = 382,
403  A3_64 = 383,
404  AC0_64 = 384,
405  D0_64 = 385,
406  D1_64 = 386,
407  D2_64 = 387,
408  D3_64 = 388,
409  D4_64 = 389,
410  D5_64 = 390,
411  D6_64 = 391,
412  D7_64 = 392,
413  D8_64 = 393,
414  D9_64 = 394,
415  D10_64 = 395,
416  D11_64 = 396,
417  D12_64 = 397,
418  D13_64 = 398,
419  D14_64 = 399,
420  D15_64 = 400,
421  D16_64 = 401,
422  D17_64 = 402,
423  D18_64 = 403,
424  D19_64 = 404,
425  D20_64 = 405,
426  D21_64 = 406,
427  D22_64 = 407,
428  D23_64 = 408,
429  D24_64 = 409,
430  D25_64 = 410,
431  D26_64 = 411,
432  D27_64 = 412,
433  D28_64 = 413,
434  D29_64 = 414,
435  D30_64 = 415,
436  D31_64 = 416,
437  DSPOutFlag16_19 = 417,
438  HI0_64 = 418,
439  K0_64 = 419,
440  K1_64 = 420,
441  LO0_64 = 421,
442  S0_64 = 422,
443  S1_64 = 423,
444  S2_64 = 424,
445  S3_64 = 425,
446  S4_64 = 426,
447  S5_64 = 427,
448  S6_64 = 428,
449  S7_64 = 429,
450  T0_64 = 430,
451  T1_64 = 431,
452  T2_64 = 432,
453  T3_64 = 433,
454  T4_64 = 434,
455  T5_64 = 435,
456  T6_64 = 436,
457  T7_64 = 437,
458  T8_64 = 438,
459  T9_64 = 439,
460  V0_64 = 440,
461  V1_64 = 441,
462  NUM_TARGET_REGS 	// 442
463};
464} // end namespace Mips
465
466// Register classes
467
468namespace Mips {
469enum {
470  MSA128F16RegClassID = 0,
471  CCRRegClassID = 1,
472  COP0RegClassID = 2,
473  COP2RegClassID = 3,
474  COP3RegClassID = 4,
475  DSPRRegClassID = 5,
476  FGR32RegClassID = 6,
477  FGRCCRegClassID = 7,
478  GPR32RegClassID = 8,
479  HWRegsRegClassID = 9,
480  MSACtrlRegClassID = 10,
481  GPR32NONZERORegClassID = 11,
482  CPU16RegsPlusSPRegClassID = 12,
483  CPU16RegsRegClassID = 13,
484  FCCRegClassID = 14,
485  GPRMM16RegClassID = 15,
486  GPRMM16MovePRegClassID = 16,
487  GPRMM16ZeroRegClassID = 17,
488  CPU16Regs_and_GPRMM16ZeroRegClassID = 18,
489  GPR32NONZERO_and_GPRMM16MovePRegClassID = 19,
490  GPRMM16MovePPairSecondRegClassID = 20,
491  CPU16Regs_and_GPRMM16MovePRegClassID = 21,
492  GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 22,
493  HI32DSPRegClassID = 23,
494  LO32DSPRegClassID = 24,
495  CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 25,
496  GPRMM16MovePPairFirstRegClassID = 26,
497  GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 27,
498  GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 28,
499  CPURARegRegClassID = 29,
500  CPUSPRegRegClassID = 30,
501  DSPCCRegClassID = 31,
502  GP32RegClassID = 32,
503  GPR32ZERORegClassID = 33,
504  HI32RegClassID = 34,
505  LO32RegClassID = 35,
506  SP32RegClassID = 36,
507  FGR64RegClassID = 37,
508  GPR64RegClassID = 38,
509  GPR64_with_sub_32_in_GPR32NONZERORegClassID = 39,
510  AFGR64RegClassID = 40,
511  GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 41,
512  GPR64_with_sub_32_in_CPU16RegsRegClassID = 42,
513  GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 43,
514  GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 44,
515  GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 45,
516  GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 46,
517  GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 47,
518  ACC64DSPRegClassID = 48,
519  GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 49,
520  GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 50,
521  GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 51,
522  GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 52,
523  GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 53,
524  OCTEON_MPLRegClassID = 54,
525  OCTEON_PRegClassID = 55,
526  GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 56,
527  ACC64RegClassID = 57,
528  GP64RegClassID = 58,
529  GPR64_with_sub_32_in_CPURARegRegClassID = 59,
530  GPR64_with_sub_32_in_GPR32ZERORegClassID = 60,
531  HI64RegClassID = 61,
532  LO64RegClassID = 62,
533  SP64RegClassID = 63,
534  MSA128BRegClassID = 64,
535  MSA128DRegClassID = 65,
536  MSA128HRegClassID = 66,
537  MSA128WRegClassID = 67,
538  MSA128WEvensRegClassID = 68,
539  ACC128RegClassID = 69,
540
541  };
542} // end namespace Mips
543
544
545// Subregister indices
546
547namespace Mips {
548enum {
549  NoSubRegister,
550  sub_32,	// 1
551  sub_64,	// 2
552  sub_dsp16_19,	// 3
553  sub_dsp20,	// 4
554  sub_dsp21,	// 5
555  sub_dsp22,	// 6
556  sub_dsp23,	// 7
557  sub_hi,	// 8
558  sub_lo,	// 9
559  sub_hi_then_sub_32,	// 10
560  sub_32_sub_hi_then_sub_32,	// 11
561  NUM_TARGET_SUBREGS
562};
563} // end namespace Mips
564
565} // end namespace llvm
566
567#endif // GET_REGINFO_ENUM
568
569/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
570|*                                                                            *|
571|* MC Register Information                                                    *|
572|*                                                                            *|
573|* Automatically generated file, do not edit!                                 *|
574|*                                                                            *|
575\*===----------------------------------------------------------------------===*/
576
577
578#ifdef GET_REGINFO_MC_DESC
579#undef GET_REGINFO_MC_DESC
580
581namespace llvm {
582
583extern const MCPhysReg MipsRegDiffLists[] = {
584  /* 0 */ 0, 0,
585  /* 2 */ 4, 1, 1, 1, 1, 0,
586  /* 8 */ 412, 65262, 1, 1, 1, 0,
587  /* 14 */ 20, 1, 0,
588  /* 17 */ 21, 1, 0,
589  /* 20 */ 22, 1, 0,
590  /* 23 */ 23, 1, 0,
591  /* 26 */ 24, 1, 0,
592  /* 29 */ 25, 1, 0,
593  /* 32 */ 26, 1, 0,
594  /* 35 */ 27, 1, 0,
595  /* 38 */ 28, 1, 0,
596  /* 41 */ 29, 1, 0,
597  /* 44 */ 30, 1, 0,
598  /* 47 */ 31, 1, 0,
599  /* 50 */ 32, 1, 0,
600  /* 53 */ 33, 1, 0,
601  /* 56 */ 34, 1, 0,
602  /* 59 */ 35, 1, 0,
603  /* 62 */ 65415, 1, 0,
604  /* 65 */ 65513, 1, 0,
605  /* 68 */ 3, 0,
606  /* 70 */ 4, 0,
607  /* 72 */ 6, 0,
608  /* 74 */ 11, 0,
609  /* 76 */ 12, 0,
610  /* 78 */ 22, 0,
611  /* 80 */ 23, 0,
612  /* 82 */ 29, 0,
613  /* 84 */ 30, 0,
614  /* 86 */ 65284, 72, 0,
615  /* 89 */ 65322, 72, 0,
616  /* 92 */ 38, 65298, 73, 0,
617  /* 96 */ 95, 0,
618  /* 98 */ 96, 0,
619  /* 100 */ 130, 0,
620  /* 102 */ 211, 0,
621  /* 104 */ 243, 0,
622  /* 106 */ 306, 0,
623  /* 108 */ 314, 0,
624  /* 110 */ 358, 0,
625  /* 112 */ 64983, 0,
626  /* 114 */ 65060, 0,
627  /* 116 */ 65124, 0,
628  /* 118 */ 65178, 0,
629  /* 120 */ 65181, 0,
630  /* 122 */ 65222, 0,
631  /* 124 */ 65230, 0,
632  /* 126 */ 65271, 0,
633  /* 128 */ 65293, 0,
634  /* 130 */ 37, 65406, 127, 65371, 65309, 0,
635  /* 136 */ 65325, 0,
636  /* 138 */ 65371, 0,
637  /* 140 */ 65386, 0,
638  /* 142 */ 65395, 0,
639  /* 144 */ 65396, 0,
640  /* 146 */ 65397, 0,
641  /* 148 */ 65398, 0,
642  /* 150 */ 65406, 0,
643  /* 152 */ 65415, 0,
644  /* 154 */ 65440, 0,
645  /* 156 */ 65441, 0,
646  /* 158 */ 165, 65498, 0,
647  /* 161 */ 65516, 258, 65498, 0,
648  /* 165 */ 65515, 259, 65498, 0,
649  /* 169 */ 65514, 260, 65498, 0,
650  /* 173 */ 65513, 261, 65498, 0,
651  /* 177 */ 65512, 262, 65498, 0,
652  /* 181 */ 65511, 263, 65498, 0,
653  /* 185 */ 65510, 264, 65498, 0,
654  /* 189 */ 65509, 265, 65498, 0,
655  /* 193 */ 65508, 266, 65498, 0,
656  /* 197 */ 65507, 267, 65498, 0,
657  /* 201 */ 65506, 268, 65498, 0,
658  /* 205 */ 65505, 269, 65498, 0,
659  /* 209 */ 65504, 270, 65498, 0,
660  /* 213 */ 65503, 271, 65498, 0,
661  /* 217 */ 65502, 272, 65498, 0,
662  /* 221 */ 65501, 273, 65498, 0,
663  /* 225 */ 65500, 274, 65498, 0,
664  /* 229 */ 65271, 395, 65499, 0,
665  /* 233 */ 65309, 392, 65502, 0,
666  /* 237 */ 65507, 0,
667  /* 239 */ 65510, 0,
668  /* 241 */ 65511, 0,
669  /* 243 */ 65512, 0,
670  /* 245 */ 65516, 0,
671  /* 247 */ 65521, 0,
672  /* 249 */ 65522, 0,
673  /* 251 */ 65535, 0,
674};
675
676extern const LaneBitmask MipsLaneMaskLists[] = {
677  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
678  /* 2 */ LaneBitmask(0x00000001), LaneBitmask::getAll(),
679  /* 4 */ LaneBitmask(0x00000002), LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
680  /* 10 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(),
681};
682
683extern const uint16_t MipsSubRegIdxLists[] = {
684  /* 0 */ 1, 0,
685  /* 2 */ 3, 4, 5, 6, 7, 0,
686  /* 8 */ 2, 9, 8, 0,
687  /* 12 */ 9, 1, 8, 10, 11, 0,
688};
689
690extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = {
691  { 65535, 65535 },
692  { 0, 32 },	// sub_32
693  { 0, 64 },	// sub_64
694  { 16, 4 },	// sub_dsp16_19
695  { 20, 1 },	// sub_dsp20
696  { 21, 1 },	// sub_dsp21
697  { 22, 1 },	// sub_dsp22
698  { 23, 1 },	// sub_dsp23
699  { 32, 32 },	// sub_hi
700  { 0, 32 },	// sub_lo
701  { 32, 32 },	// sub_hi_then_sub_32
702  { 0, 64 },	// sub_32_sub_hi_then_sub_32
703};
704
705extern const char MipsRegStrings[] = {
706  /* 0 */ 'C', 'O', 'P', '0', '0', 0,
707  /* 6 */ 'C', 'O', 'P', '0', '1', '0', 0,
708  /* 13 */ 'C', 'O', 'P', '2', '1', '0', 0,
709  /* 20 */ 'C', 'O', 'P', '3', '1', '0', 0,
710  /* 27 */ 'M', 'S', 'A', '1', '0', 0,
711  /* 33 */ 'D', '1', '0', 0,
712  /* 37 */ 'F', '1', '0', 0,
713  /* 41 */ 'F', '_', 'H', 'I', '1', '0', 0,
714  /* 48 */ 'F', 'C', 'R', '1', '0', 0,
715  /* 54 */ 'H', 'W', 'R', '1', '0', 0,
716  /* 60 */ 'W', '1', '0', 0,
717  /* 64 */ 'C', 'O', 'P', '0', '2', '0', 0,
718  /* 71 */ 'C', 'O', 'P', '2', '2', '0', 0,
719  /* 78 */ 'C', 'O', 'P', '3', '2', '0', 0,
720  /* 85 */ 'M', 'S', 'A', '2', '0', 0,
721  /* 91 */ 'F', '2', '0', 0,
722  /* 95 */ 'F', '_', 'H', 'I', '2', '0', 0,
723  /* 102 */ 'C', 'O', 'P', '2', '0', 0,
724  /* 108 */ 'F', 'C', 'R', '2', '0', 0,
725  /* 114 */ 'H', 'W', 'R', '2', '0', 0,
726  /* 120 */ 'W', '2', '0', 0,
727  /* 124 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0,
728  /* 137 */ 'C', 'O', 'P', '0', '3', '0', 0,
729  /* 144 */ 'C', 'O', 'P', '2', '3', '0', 0,
730  /* 151 */ 'C', 'O', 'P', '3', '3', '0', 0,
731  /* 158 */ 'M', 'S', 'A', '3', '0', 0,
732  /* 164 */ 'F', '3', '0', 0,
733  /* 168 */ 'F', '_', 'H', 'I', '3', '0', 0,
734  /* 175 */ 'C', 'O', 'P', '3', '0', 0,
735  /* 181 */ 'F', 'C', 'R', '3', '0', 0,
736  /* 187 */ 'H', 'W', 'R', '3', '0', 0,
737  /* 193 */ 'W', '3', '0', 0,
738  /* 197 */ 'A', '0', 0,
739  /* 200 */ 'A', 'C', '0', 0,
740  /* 204 */ 'F', 'C', 'C', '0', 0,
741  /* 209 */ 'D', '0', 0,
742  /* 212 */ 'F', '0', 0,
743  /* 215 */ 'F', '_', 'H', 'I', '0', 0,
744  /* 221 */ 'K', '0', 0,
745  /* 224 */ 'M', 'P', 'L', '0', 0,
746  /* 229 */ 'L', 'O', '0', 0,
747  /* 233 */ 'P', '0', 0,
748  /* 236 */ 'F', 'C', 'R', '0', 0,
749  /* 241 */ 'H', 'W', 'R', '0', 0,
750  /* 246 */ 'S', '0', 0,
751  /* 249 */ 'T', '0', 0,
752  /* 252 */ 'V', '0', 0,
753  /* 255 */ 'W', '0', 0,
754  /* 258 */ 'C', 'O', 'P', '0', '1', 0,
755  /* 264 */ 'C', 'O', 'P', '0', '1', '1', 0,
756  /* 271 */ 'C', 'O', 'P', '2', '1', '1', 0,
757  /* 278 */ 'C', 'O', 'P', '3', '1', '1', 0,
758  /* 285 */ 'M', 'S', 'A', '1', '1', 0,
759  /* 291 */ 'D', '1', '1', 0,
760  /* 295 */ 'F', '1', '1', 0,
761  /* 299 */ 'F', '_', 'H', 'I', '1', '1', 0,
762  /* 306 */ 'F', 'C', 'R', '1', '1', 0,
763  /* 312 */ 'H', 'W', 'R', '1', '1', 0,
764  /* 318 */ 'W', '1', '1', 0,
765  /* 322 */ 'C', 'O', 'P', '0', '2', '1', 0,
766  /* 329 */ 'C', 'O', 'P', '2', '2', '1', 0,
767  /* 336 */ 'C', 'O', 'P', '3', '2', '1', 0,
768  /* 343 */ 'M', 'S', 'A', '2', '1', 0,
769  /* 349 */ 'F', '2', '1', 0,
770  /* 353 */ 'F', '_', 'H', 'I', '2', '1', 0,
771  /* 360 */ 'C', 'O', 'P', '2', '1', 0,
772  /* 366 */ 'F', 'C', 'R', '2', '1', 0,
773  /* 372 */ 'H', 'W', 'R', '2', '1', 0,
774  /* 378 */ 'W', '2', '1', 0,
775  /* 382 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0,
776  /* 395 */ 'C', 'O', 'P', '0', '3', '1', 0,
777  /* 402 */ 'C', 'O', 'P', '2', '3', '1', 0,
778  /* 409 */ 'C', 'O', 'P', '3', '3', '1', 0,
779  /* 416 */ 'M', 'S', 'A', '3', '1', 0,
780  /* 422 */ 'F', '3', '1', 0,
781  /* 426 */ 'F', '_', 'H', 'I', '3', '1', 0,
782  /* 433 */ 'C', 'O', 'P', '3', '1', 0,
783  /* 439 */ 'F', 'C', 'R', '3', '1', 0,
784  /* 445 */ 'H', 'W', 'R', '3', '1', 0,
785  /* 451 */ 'W', '3', '1', 0,
786  /* 455 */ 'A', '1', 0,
787  /* 458 */ 'A', 'C', '1', 0,
788  /* 462 */ 'F', 'C', 'C', '1', 0,
789  /* 467 */ 'D', '1', 0,
790  /* 470 */ 'F', '1', 0,
791  /* 473 */ 'F', '_', 'H', 'I', '1', 0,
792  /* 479 */ 'K', '1', 0,
793  /* 482 */ 'M', 'P', 'L', '1', 0,
794  /* 487 */ 'L', 'O', '1', 0,
795  /* 491 */ 'P', '1', 0,
796  /* 494 */ 'F', 'C', 'R', '1', 0,
797  /* 499 */ 'H', 'W', 'R', '1', 0,
798  /* 504 */ 'S', '1', 0,
799  /* 507 */ 'T', '1', 0,
800  /* 510 */ 'V', '1', 0,
801  /* 513 */ 'W', '1', 0,
802  /* 516 */ 'C', 'O', 'P', '0', '2', 0,
803  /* 522 */ 'C', 'O', 'P', '0', '1', '2', 0,
804  /* 529 */ 'C', 'O', 'P', '2', '1', '2', 0,
805  /* 536 */ 'C', 'O', 'P', '3', '1', '2', 0,
806  /* 543 */ 'M', 'S', 'A', '1', '2', 0,
807  /* 549 */ 'D', '1', '2', 0,
808  /* 553 */ 'F', '1', '2', 0,
809  /* 557 */ 'F', '_', 'H', 'I', '1', '2', 0,
810  /* 564 */ 'F', 'C', 'R', '1', '2', 0,
811  /* 570 */ 'H', 'W', 'R', '1', '2', 0,
812  /* 576 */ 'W', '1', '2', 0,
813  /* 580 */ 'C', 'O', 'P', '0', '2', '2', 0,
814  /* 587 */ 'C', 'O', 'P', '2', '2', '2', 0,
815  /* 594 */ 'C', 'O', 'P', '3', '2', '2', 0,
816  /* 601 */ 'M', 'S', 'A', '2', '2', 0,
817  /* 607 */ 'F', '2', '2', 0,
818  /* 611 */ 'F', '_', 'H', 'I', '2', '2', 0,
819  /* 618 */ 'C', 'O', 'P', '2', '2', 0,
820  /* 624 */ 'F', 'C', 'R', '2', '2', 0,
821  /* 630 */ 'H', 'W', 'R', '2', '2', 0,
822  /* 636 */ 'W', '2', '2', 0,
823  /* 640 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0,
824  /* 653 */ 'C', 'O', 'P', '3', '2', 0,
825  /* 659 */ 'A', '2', 0,
826  /* 662 */ 'A', 'C', '2', 0,
827  /* 666 */ 'F', 'C', 'C', '2', 0,
828  /* 671 */ 'D', '2', 0,
829  /* 674 */ 'F', '2', 0,
830  /* 677 */ 'F', '_', 'H', 'I', '2', 0,
831  /* 683 */ 'M', 'P', 'L', '2', 0,
832  /* 688 */ 'L', 'O', '2', 0,
833  /* 692 */ 'P', '2', 0,
834  /* 695 */ 'F', 'C', 'R', '2', 0,
835  /* 700 */ 'H', 'W', 'R', '2', 0,
836  /* 705 */ 'S', '2', 0,
837  /* 708 */ 'T', '2', 0,
838  /* 711 */ 'W', '2', 0,
839  /* 714 */ 'C', 'O', 'P', '0', '3', 0,
840  /* 720 */ 'C', 'O', 'P', '0', '1', '3', 0,
841  /* 727 */ 'C', 'O', 'P', '2', '1', '3', 0,
842  /* 734 */ 'C', 'O', 'P', '3', '1', '3', 0,
843  /* 741 */ 'M', 'S', 'A', '1', '3', 0,
844  /* 747 */ 'D', '1', '3', 0,
845  /* 751 */ 'F', '1', '3', 0,
846  /* 755 */ 'F', '_', 'H', 'I', '1', '3', 0,
847  /* 762 */ 'F', 'C', 'R', '1', '3', 0,
848  /* 768 */ 'H', 'W', 'R', '1', '3', 0,
849  /* 774 */ 'W', '1', '3', 0,
850  /* 778 */ 'C', 'O', 'P', '0', '2', '3', 0,
851  /* 785 */ 'C', 'O', 'P', '2', '2', '3', 0,
852  /* 792 */ 'C', 'O', 'P', '3', '2', '3', 0,
853  /* 799 */ 'M', 'S', 'A', '2', '3', 0,
854  /* 805 */ 'F', '2', '3', 0,
855  /* 809 */ 'F', '_', 'H', 'I', '2', '3', 0,
856  /* 816 */ 'C', 'O', 'P', '2', '3', 0,
857  /* 822 */ 'F', 'C', 'R', '2', '3', 0,
858  /* 828 */ 'H', 'W', 'R', '2', '3', 0,
859  /* 834 */ 'W', '2', '3', 0,
860  /* 838 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0,
861  /* 851 */ 'C', 'O', 'P', '3', '3', 0,
862  /* 857 */ 'A', '3', 0,
863  /* 860 */ 'A', 'C', '3', 0,
864  /* 864 */ 'F', 'C', 'C', '3', 0,
865  /* 869 */ 'D', '3', 0,
866  /* 872 */ 'F', '3', 0,
867  /* 875 */ 'F', '_', 'H', 'I', '3', 0,
868  /* 881 */ 'L', 'O', '3', 0,
869  /* 885 */ 'F', 'C', 'R', '3', 0,
870  /* 890 */ 'H', 'W', 'R', '3', 0,
871  /* 895 */ 'S', '3', 0,
872  /* 898 */ 'T', '3', 0,
873  /* 901 */ 'W', '3', 0,
874  /* 904 */ 'C', 'O', 'P', '0', '4', 0,
875  /* 910 */ 'C', 'O', 'P', '0', '1', '4', 0,
876  /* 917 */ 'C', 'O', 'P', '2', '1', '4', 0,
877  /* 924 */ 'C', 'O', 'P', '3', '1', '4', 0,
878  /* 931 */ 'M', 'S', 'A', '1', '4', 0,
879  /* 937 */ 'D', '1', '4', 0,
880  /* 941 */ 'F', '1', '4', 0,
881  /* 945 */ 'F', '_', 'H', 'I', '1', '4', 0,
882  /* 952 */ 'F', 'C', 'R', '1', '4', 0,
883  /* 958 */ 'H', 'W', 'R', '1', '4', 0,
884  /* 964 */ 'W', '1', '4', 0,
885  /* 968 */ 'C', 'O', 'P', '0', '2', '4', 0,
886  /* 975 */ 'C', 'O', 'P', '2', '2', '4', 0,
887  /* 982 */ 'C', 'O', 'P', '3', '2', '4', 0,
888  /* 989 */ 'M', 'S', 'A', '2', '4', 0,
889  /* 995 */ 'F', '2', '4', 0,
890  /* 999 */ 'F', '_', 'H', 'I', '2', '4', 0,
891  /* 1006 */ 'C', 'O', 'P', '2', '4', 0,
892  /* 1012 */ 'F', 'C', 'R', '2', '4', 0,
893  /* 1018 */ 'H', 'W', 'R', '2', '4', 0,
894  /* 1024 */ 'W', '2', '4', 0,
895  /* 1028 */ 'C', 'O', 'P', '3', '4', 0,
896  /* 1034 */ 'D', '1', '0', '_', '6', '4', 0,
897  /* 1041 */ 'D', '2', '0', '_', '6', '4', 0,
898  /* 1048 */ 'D', '3', '0', '_', '6', '4', 0,
899  /* 1055 */ 'A', '0', '_', '6', '4', 0,
900  /* 1061 */ 'A', 'C', '0', '_', '6', '4', 0,
901  /* 1068 */ 'D', '0', '_', '6', '4', 0,
902  /* 1074 */ 'H', 'I', '0', '_', '6', '4', 0,
903  /* 1081 */ 'K', '0', '_', '6', '4', 0,
904  /* 1087 */ 'L', 'O', '0', '_', '6', '4', 0,
905  /* 1094 */ 'S', '0', '_', '6', '4', 0,
906  /* 1100 */ 'T', '0', '_', '6', '4', 0,
907  /* 1106 */ 'V', '0', '_', '6', '4', 0,
908  /* 1112 */ 'D', '1', '1', '_', '6', '4', 0,
909  /* 1119 */ 'D', '2', '1', '_', '6', '4', 0,
910  /* 1126 */ 'D', '3', '1', '_', '6', '4', 0,
911  /* 1133 */ 'A', '1', '_', '6', '4', 0,
912  /* 1139 */ 'D', '1', '_', '6', '4', 0,
913  /* 1145 */ 'K', '1', '_', '6', '4', 0,
914  /* 1151 */ 'S', '1', '_', '6', '4', 0,
915  /* 1157 */ 'T', '1', '_', '6', '4', 0,
916  /* 1163 */ 'V', '1', '_', '6', '4', 0,
917  /* 1169 */ 'D', '1', '2', '_', '6', '4', 0,
918  /* 1176 */ 'D', '2', '2', '_', '6', '4', 0,
919  /* 1183 */ 'A', '2', '_', '6', '4', 0,
920  /* 1189 */ 'D', '2', '_', '6', '4', 0,
921  /* 1195 */ 'S', '2', '_', '6', '4', 0,
922  /* 1201 */ 'T', '2', '_', '6', '4', 0,
923  /* 1207 */ 'D', '1', '3', '_', '6', '4', 0,
924  /* 1214 */ 'D', '2', '3', '_', '6', '4', 0,
925  /* 1221 */ 'A', '3', '_', '6', '4', 0,
926  /* 1227 */ 'D', '3', '_', '6', '4', 0,
927  /* 1233 */ 'S', '3', '_', '6', '4', 0,
928  /* 1239 */ 'T', '3', '_', '6', '4', 0,
929  /* 1245 */ 'D', '1', '4', '_', '6', '4', 0,
930  /* 1252 */ 'D', '2', '4', '_', '6', '4', 0,
931  /* 1259 */ 'D', '4', '_', '6', '4', 0,
932  /* 1265 */ 'S', '4', '_', '6', '4', 0,
933  /* 1271 */ 'T', '4', '_', '6', '4', 0,
934  /* 1277 */ 'D', '1', '5', '_', '6', '4', 0,
935  /* 1284 */ 'D', '2', '5', '_', '6', '4', 0,
936  /* 1291 */ 'D', '5', '_', '6', '4', 0,
937  /* 1297 */ 'S', '5', '_', '6', '4', 0,
938  /* 1303 */ 'T', '5', '_', '6', '4', 0,
939  /* 1309 */ 'D', '1', '6', '_', '6', '4', 0,
940  /* 1316 */ 'D', '2', '6', '_', '6', '4', 0,
941  /* 1323 */ 'D', '6', '_', '6', '4', 0,
942  /* 1329 */ 'S', '6', '_', '6', '4', 0,
943  /* 1335 */ 'T', '6', '_', '6', '4', 0,
944  /* 1341 */ 'D', '1', '7', '_', '6', '4', 0,
945  /* 1348 */ 'D', '2', '7', '_', '6', '4', 0,
946  /* 1355 */ 'D', '7', '_', '6', '4', 0,
947  /* 1361 */ 'S', '7', '_', '6', '4', 0,
948  /* 1367 */ 'T', '7', '_', '6', '4', 0,
949  /* 1373 */ 'D', '1', '8', '_', '6', '4', 0,
950  /* 1380 */ 'D', '2', '8', '_', '6', '4', 0,
951  /* 1387 */ 'D', '8', '_', '6', '4', 0,
952  /* 1393 */ 'T', '8', '_', '6', '4', 0,
953  /* 1399 */ 'D', '1', '9', '_', '6', '4', 0,
954  /* 1406 */ 'D', '2', '9', '_', '6', '4', 0,
955  /* 1413 */ 'D', '9', '_', '6', '4', 0,
956  /* 1419 */ 'T', '9', '_', '6', '4', 0,
957  /* 1425 */ 'R', 'A', '_', '6', '4', 0,
958  /* 1431 */ 'Z', 'E', 'R', 'O', '_', '6', '4', 0,
959  /* 1439 */ 'F', 'P', '_', '6', '4', 0,
960  /* 1445 */ 'G', 'P', '_', '6', '4', 0,
961  /* 1451 */ 'S', 'P', '_', '6', '4', 0,
962  /* 1457 */ 'A', 'T', '_', '6', '4', 0,
963  /* 1463 */ 'F', 'C', 'C', '4', 0,
964  /* 1468 */ 'D', '4', 0,
965  /* 1471 */ 'F', '4', 0,
966  /* 1474 */ 'F', '_', 'H', 'I', '4', 0,
967  /* 1480 */ 'F', 'C', 'R', '4', 0,
968  /* 1485 */ 'H', 'W', 'R', '4', 0,
969  /* 1490 */ 'S', '4', 0,
970  /* 1493 */ 'T', '4', 0,
971  /* 1496 */ 'W', '4', 0,
972  /* 1499 */ 'C', 'O', 'P', '0', '5', 0,
973  /* 1505 */ 'C', 'O', 'P', '0', '1', '5', 0,
974  /* 1512 */ 'C', 'O', 'P', '2', '1', '5', 0,
975  /* 1519 */ 'C', 'O', 'P', '3', '1', '5', 0,
976  /* 1526 */ 'M', 'S', 'A', '1', '5', 0,
977  /* 1532 */ 'D', '1', '5', 0,
978  /* 1536 */ 'F', '1', '5', 0,
979  /* 1540 */ 'F', '_', 'H', 'I', '1', '5', 0,
980  /* 1547 */ 'F', 'C', 'R', '1', '5', 0,
981  /* 1553 */ 'H', 'W', 'R', '1', '5', 0,
982  /* 1559 */ 'W', '1', '5', 0,
983  /* 1563 */ 'C', 'O', 'P', '0', '2', '5', 0,
984  /* 1570 */ 'C', 'O', 'P', '2', '2', '5', 0,
985  /* 1577 */ 'C', 'O', 'P', '3', '2', '5', 0,
986  /* 1584 */ 'M', 'S', 'A', '2', '5', 0,
987  /* 1590 */ 'F', '2', '5', 0,
988  /* 1594 */ 'F', '_', 'H', 'I', '2', '5', 0,
989  /* 1601 */ 'C', 'O', 'P', '2', '5', 0,
990  /* 1607 */ 'F', 'C', 'R', '2', '5', 0,
991  /* 1613 */ 'H', 'W', 'R', '2', '5', 0,
992  /* 1619 */ 'W', '2', '5', 0,
993  /* 1623 */ 'C', 'O', 'P', '3', '5', 0,
994  /* 1629 */ 'F', 'C', 'C', '5', 0,
995  /* 1634 */ 'D', '5', 0,
996  /* 1637 */ 'F', '5', 0,
997  /* 1640 */ 'F', '_', 'H', 'I', '5', 0,
998  /* 1646 */ 'F', 'C', 'R', '5', 0,
999  /* 1651 */ 'H', 'W', 'R', '5', 0,
1000  /* 1656 */ 'S', '5', 0,
1001  /* 1659 */ 'T', '5', 0,
1002  /* 1662 */ 'W', '5', 0,
1003  /* 1665 */ 'C', 'O', 'P', '0', '6', 0,
1004  /* 1671 */ 'C', 'O', 'P', '0', '1', '6', 0,
1005  /* 1678 */ 'C', 'O', 'P', '2', '1', '6', 0,
1006  /* 1685 */ 'C', 'O', 'P', '3', '1', '6', 0,
1007  /* 1692 */ 'M', 'S', 'A', '1', '6', 0,
1008  /* 1698 */ 'F', '1', '6', 0,
1009  /* 1702 */ 'F', '_', 'H', 'I', '1', '6', 0,
1010  /* 1709 */ 'F', 'C', 'R', '1', '6', 0,
1011  /* 1715 */ 'H', 'W', 'R', '1', '6', 0,
1012  /* 1721 */ 'W', '1', '6', 0,
1013  /* 1725 */ 'C', 'O', 'P', '0', '2', '6', 0,
1014  /* 1732 */ 'C', 'O', 'P', '2', '2', '6', 0,
1015  /* 1739 */ 'C', 'O', 'P', '3', '2', '6', 0,
1016  /* 1746 */ 'M', 'S', 'A', '2', '6', 0,
1017  /* 1752 */ 'F', '2', '6', 0,
1018  /* 1756 */ 'F', '_', 'H', 'I', '2', '6', 0,
1019  /* 1763 */ 'C', 'O', 'P', '2', '6', 0,
1020  /* 1769 */ 'F', 'C', 'R', '2', '6', 0,
1021  /* 1775 */ 'H', 'W', 'R', '2', '6', 0,
1022  /* 1781 */ 'W', '2', '6', 0,
1023  /* 1785 */ 'C', 'O', 'P', '3', '6', 0,
1024  /* 1791 */ 'F', 'C', 'C', '6', 0,
1025  /* 1796 */ 'D', '6', 0,
1026  /* 1799 */ 'F', '6', 0,
1027  /* 1802 */ 'F', '_', 'H', 'I', '6', 0,
1028  /* 1808 */ 'F', 'C', 'R', '6', 0,
1029  /* 1813 */ 'H', 'W', 'R', '6', 0,
1030  /* 1818 */ 'S', '6', 0,
1031  /* 1821 */ 'T', '6', 0,
1032  /* 1824 */ 'W', '6', 0,
1033  /* 1827 */ 'C', 'O', 'P', '0', '7', 0,
1034  /* 1833 */ 'C', 'O', 'P', '0', '1', '7', 0,
1035  /* 1840 */ 'C', 'O', 'P', '2', '1', '7', 0,
1036  /* 1847 */ 'C', 'O', 'P', '3', '1', '7', 0,
1037  /* 1854 */ 'M', 'S', 'A', '1', '7', 0,
1038  /* 1860 */ 'F', '1', '7', 0,
1039  /* 1864 */ 'F', '_', 'H', 'I', '1', '7', 0,
1040  /* 1871 */ 'F', 'C', 'R', '1', '7', 0,
1041  /* 1877 */ 'H', 'W', 'R', '1', '7', 0,
1042  /* 1883 */ 'W', '1', '7', 0,
1043  /* 1887 */ 'C', 'O', 'P', '0', '2', '7', 0,
1044  /* 1894 */ 'C', 'O', 'P', '2', '2', '7', 0,
1045  /* 1901 */ 'C', 'O', 'P', '3', '2', '7', 0,
1046  /* 1908 */ 'M', 'S', 'A', '2', '7', 0,
1047  /* 1914 */ 'F', '2', '7', 0,
1048  /* 1918 */ 'F', '_', 'H', 'I', '2', '7', 0,
1049  /* 1925 */ 'C', 'O', 'P', '2', '7', 0,
1050  /* 1931 */ 'F', 'C', 'R', '2', '7', 0,
1051  /* 1937 */ 'H', 'W', 'R', '2', '7', 0,
1052  /* 1943 */ 'W', '2', '7', 0,
1053  /* 1947 */ 'C', 'O', 'P', '3', '7', 0,
1054  /* 1953 */ 'F', 'C', 'C', '7', 0,
1055  /* 1958 */ 'D', '7', 0,
1056  /* 1961 */ 'F', '7', 0,
1057  /* 1964 */ 'F', '_', 'H', 'I', '7', 0,
1058  /* 1970 */ 'F', 'C', 'R', '7', 0,
1059  /* 1975 */ 'H', 'W', 'R', '7', 0,
1060  /* 1980 */ 'S', '7', 0,
1061  /* 1983 */ 'T', '7', 0,
1062  /* 1986 */ 'W', '7', 0,
1063  /* 1989 */ 'C', 'O', 'P', '0', '8', 0,
1064  /* 1995 */ 'C', 'O', 'P', '0', '1', '8', 0,
1065  /* 2002 */ 'C', 'O', 'P', '2', '1', '8', 0,
1066  /* 2009 */ 'C', 'O', 'P', '3', '1', '8', 0,
1067  /* 2016 */ 'M', 'S', 'A', '1', '8', 0,
1068  /* 2022 */ 'F', '1', '8', 0,
1069  /* 2026 */ 'F', '_', 'H', 'I', '1', '8', 0,
1070  /* 2033 */ 'F', 'C', 'R', '1', '8', 0,
1071  /* 2039 */ 'H', 'W', 'R', '1', '8', 0,
1072  /* 2045 */ 'W', '1', '8', 0,
1073  /* 2049 */ 'C', 'O', 'P', '0', '2', '8', 0,
1074  /* 2056 */ 'C', 'O', 'P', '2', '2', '8', 0,
1075  /* 2063 */ 'C', 'O', 'P', '3', '2', '8', 0,
1076  /* 2070 */ 'M', 'S', 'A', '2', '8', 0,
1077  /* 2076 */ 'F', '2', '8', 0,
1078  /* 2080 */ 'F', '_', 'H', 'I', '2', '8', 0,
1079  /* 2087 */ 'C', 'O', 'P', '2', '8', 0,
1080  /* 2093 */ 'F', 'C', 'R', '2', '8', 0,
1081  /* 2099 */ 'H', 'W', 'R', '2', '8', 0,
1082  /* 2105 */ 'W', '2', '8', 0,
1083  /* 2109 */ 'C', 'O', 'P', '3', '8', 0,
1084  /* 2115 */ 'M', 'S', 'A', '8', 0,
1085  /* 2120 */ 'D', '8', 0,
1086  /* 2123 */ 'F', '8', 0,
1087  /* 2126 */ 'F', '_', 'H', 'I', '8', 0,
1088  /* 2132 */ 'F', 'C', 'R', '8', 0,
1089  /* 2137 */ 'H', 'W', 'R', '8', 0,
1090  /* 2142 */ 'T', '8', 0,
1091  /* 2145 */ 'W', '8', 0,
1092  /* 2148 */ 'C', 'O', 'P', '0', '9', 0,
1093  /* 2154 */ 'C', 'O', 'P', '0', '1', '9', 0,
1094  /* 2161 */ 'C', 'O', 'P', '2', '1', '9', 0,
1095  /* 2168 */ 'C', 'O', 'P', '3', '1', '9', 0,
1096  /* 2175 */ 'M', 'S', 'A', '1', '9', 0,
1097  /* 2181 */ 'F', '1', '9', 0,
1098  /* 2185 */ 'F', '_', 'H', 'I', '1', '9', 0,
1099  /* 2192 */ 'F', 'C', 'R', '1', '9', 0,
1100  /* 2198 */ 'H', 'W', 'R', '1', '9', 0,
1101  /* 2204 */ 'W', '1', '9', 0,
1102  /* 2208 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0,
1103  /* 2224 */ 'C', 'O', 'P', '0', '2', '9', 0,
1104  /* 2231 */ 'C', 'O', 'P', '2', '2', '9', 0,
1105  /* 2238 */ 'C', 'O', 'P', '3', '2', '9', 0,
1106  /* 2245 */ 'M', 'S', 'A', '2', '9', 0,
1107  /* 2251 */ 'F', '2', '9', 0,
1108  /* 2255 */ 'F', '_', 'H', 'I', '2', '9', 0,
1109  /* 2262 */ 'C', 'O', 'P', '2', '9', 0,
1110  /* 2268 */ 'F', 'C', 'R', '2', '9', 0,
1111  /* 2274 */ 'H', 'W', 'R', '2', '9', 0,
1112  /* 2280 */ 'W', '2', '9', 0,
1113  /* 2284 */ 'C', 'O', 'P', '3', '9', 0,
1114  /* 2290 */ 'M', 'S', 'A', '9', 0,
1115  /* 2295 */ 'D', '9', 0,
1116  /* 2298 */ 'F', '9', 0,
1117  /* 2301 */ 'F', '_', 'H', 'I', '9', 0,
1118  /* 2307 */ 'F', 'C', 'R', '9', 0,
1119  /* 2312 */ 'H', 'W', 'R', '9', 0,
1120  /* 2317 */ 'T', '9', 0,
1121  /* 2320 */ 'W', '9', 0,
1122  /* 2323 */ 'R', 'A', 0,
1123  /* 2326 */ 'P', 'C', 0,
1124  /* 2329 */ 'D', 'S', 'P', 'E', 'F', 'I', 0,
1125  /* 2336 */ 'Z', 'E', 'R', 'O', 0,
1126  /* 2341 */ 'F', 'P', 0,
1127  /* 2344 */ 'G', 'P', 0,
1128  /* 2347 */ 'S', 'P', 0,
1129  /* 2350 */ 'M', 'S', 'A', 'I', 'R', 0,
1130  /* 2356 */ 'M', 'S', 'A', 'C', 'S', 'R', 0,
1131  /* 2363 */ 'A', 'T', 0,
1132  /* 2366 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0,
1133  /* 2375 */ 'M', 'S', 'A', 'S', 'a', 'v', 'e', 0,
1134  /* 2383 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0,
1135  /* 2394 */ 'M', 'S', 'A', 'M', 'a', 'p', 0,
1136  /* 2401 */ 'M', 'S', 'A', 'U', 'n', 'm', 'a', 'p', 0,
1137  /* 2410 */ 'D', 'S', 'P', 'P', 'o', 's', 0,
1138  /* 2417 */ 'M', 'S', 'A', 'A', 'c', 'c', 'e', 's', 's', 0,
1139  /* 2427 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0,
1140  /* 2437 */ 'M', 'S', 'A', 'R', 'e', 'q', 'u', 'e', 's', 't', 0,
1141  /* 2448 */ 'M', 'S', 'A', 'M', 'o', 'd', 'i', 'f', 'y', 0,
1142  /* 2458 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0,
1143};
1144
1145extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors
1146  { 5, 0, 0, 0, 0, 0 },
1147  { 2363, 1, 82, 1, 4017, 0 },
1148  { 2366, 1, 1, 1, 4017, 0 },
1149  { 2458, 1, 1, 1, 4017, 0 },
1150  { 2329, 1, 1, 1, 4017, 0 },
1151  { 2383, 8, 1, 2, 32, 4 },
1152  { 2410, 1, 1, 1, 1089, 0 },
1153  { 2427, 1, 1, 1, 1089, 0 },
1154  { 2341, 1, 102, 1, 1089, 0 },
1155  { 2344, 1, 104, 1, 1089, 0 },
1156  { 2417, 1, 1, 1, 1089, 0 },
1157  { 2356, 1, 1, 1, 1089, 0 },
1158  { 2350, 1, 1, 1, 1089, 0 },
1159  { 2394, 1, 1, 1, 1089, 0 },
1160  { 2448, 1, 1, 1, 1089, 0 },
1161  { 2437, 1, 1, 1, 1089, 0 },
1162  { 2375, 1, 1, 1, 1089, 0 },
1163  { 2401, 1, 1, 1, 1089, 0 },
1164  { 2326, 1, 1, 1, 1089, 0 },
1165  { 2323, 1, 106, 1, 1089, 0 },
1166  { 2347, 1, 108, 1, 1089, 0 },
1167  { 2336, 1, 110, 1, 1089, 0 },
1168  { 197, 1, 110, 1, 1089, 0 },
1169  { 455, 1, 110, 1, 1089, 0 },
1170  { 659, 1, 110, 1, 1089, 0 },
1171  { 857, 1, 110, 1, 1089, 0 },
1172  { 200, 190, 110, 9, 1042, 10 },
1173  { 458, 190, 1, 9, 1042, 10 },
1174  { 662, 190, 1, 9, 1042, 10 },
1175  { 860, 190, 1, 9, 1042, 10 },
1176  { 1457, 237, 1, 0, 0, 2 },
1177  { 0, 1, 1, 1, 1153, 0 },
1178  { 258, 1, 1, 1, 1153, 0 },
1179  { 516, 1, 1, 1, 1153, 0 },
1180  { 714, 1, 1, 1, 1153, 0 },
1181  { 904, 1, 1, 1, 1153, 0 },
1182  { 1499, 1, 1, 1, 1153, 0 },
1183  { 1665, 1, 1, 1, 1153, 0 },
1184  { 1827, 1, 1, 1, 1153, 0 },
1185  { 1989, 1, 1, 1, 1153, 0 },
1186  { 2148, 1, 1, 1, 1153, 0 },
1187  { 102, 1, 1, 1, 1153, 0 },
1188  { 360, 1, 1, 1, 1153, 0 },
1189  { 618, 1, 1, 1, 1153, 0 },
1190  { 816, 1, 1, 1, 1153, 0 },
1191  { 1006, 1, 1, 1, 1153, 0 },
1192  { 1601, 1, 1, 1, 1153, 0 },
1193  { 1763, 1, 1, 1, 1153, 0 },
1194  { 1925, 1, 1, 1, 1153, 0 },
1195  { 2087, 1, 1, 1, 1153, 0 },
1196  { 2262, 1, 1, 1, 1153, 0 },
1197  { 175, 1, 1, 1, 1153, 0 },
1198  { 433, 1, 1, 1, 1153, 0 },
1199  { 653, 1, 1, 1, 1153, 0 },
1200  { 851, 1, 1, 1, 1153, 0 },
1201  { 1028, 1, 1, 1, 1153, 0 },
1202  { 1623, 1, 1, 1, 1153, 0 },
1203  { 1785, 1, 1, 1, 1153, 0 },
1204  { 1947, 1, 1, 1, 1153, 0 },
1205  { 2109, 1, 1, 1, 1153, 0 },
1206  { 2284, 1, 1, 1, 1153, 0 },
1207  { 6, 1, 1, 1, 1153, 0 },
1208  { 264, 1, 1, 1, 1153, 0 },
1209  { 522, 1, 1, 1, 1153, 0 },
1210  { 720, 1, 1, 1, 1153, 0 },
1211  { 910, 1, 1, 1, 1153, 0 },
1212  { 1505, 1, 1, 1, 1153, 0 },
1213  { 1671, 1, 1, 1, 1153, 0 },
1214  { 1833, 1, 1, 1, 1153, 0 },
1215  { 1995, 1, 1, 1, 1153, 0 },
1216  { 2154, 1, 1, 1, 1153, 0 },
1217  { 64, 1, 1, 1, 1153, 0 },
1218  { 322, 1, 1, 1, 1153, 0 },
1219  { 580, 1, 1, 1, 1153, 0 },
1220  { 778, 1, 1, 1, 1153, 0 },
1221  { 968, 1, 1, 1, 1153, 0 },
1222  { 1563, 1, 1, 1, 1153, 0 },
1223  { 1725, 1, 1, 1, 1153, 0 },
1224  { 1887, 1, 1, 1, 1153, 0 },
1225  { 2049, 1, 1, 1, 1153, 0 },
1226  { 2224, 1, 1, 1, 1153, 0 },
1227  { 137, 1, 1, 1, 1153, 0 },
1228  { 395, 1, 1, 1, 1153, 0 },
1229  { 13, 1, 1, 1, 1153, 0 },
1230  { 271, 1, 1, 1, 1153, 0 },
1231  { 529, 1, 1, 1, 1153, 0 },
1232  { 727, 1, 1, 1, 1153, 0 },
1233  { 917, 1, 1, 1, 1153, 0 },
1234  { 1512, 1, 1, 1, 1153, 0 },
1235  { 1678, 1, 1, 1, 1153, 0 },
1236  { 1840, 1, 1, 1, 1153, 0 },
1237  { 2002, 1, 1, 1, 1153, 0 },
1238  { 2161, 1, 1, 1, 1153, 0 },
1239  { 71, 1, 1, 1, 1153, 0 },
1240  { 329, 1, 1, 1, 1153, 0 },
1241  { 587, 1, 1, 1, 1153, 0 },
1242  { 785, 1, 1, 1, 1153, 0 },
1243  { 975, 1, 1, 1, 1153, 0 },
1244  { 1570, 1, 1, 1, 1153, 0 },
1245  { 1732, 1, 1, 1, 1153, 0 },
1246  { 1894, 1, 1, 1, 1153, 0 },
1247  { 2056, 1, 1, 1, 1153, 0 },
1248  { 2231, 1, 1, 1, 1153, 0 },
1249  { 144, 1, 1, 1, 1153, 0 },
1250  { 402, 1, 1, 1, 1153, 0 },
1251  { 20, 1, 1, 1, 1153, 0 },
1252  { 278, 1, 1, 1, 1153, 0 },
1253  { 536, 1, 1, 1, 1153, 0 },
1254  { 734, 1, 1, 1, 1153, 0 },
1255  { 924, 1, 1, 1, 1153, 0 },
1256  { 1519, 1, 1, 1, 1153, 0 },
1257  { 1685, 1, 1, 1, 1153, 0 },
1258  { 1847, 1, 1, 1, 1153, 0 },
1259  { 2009, 1, 1, 1, 1153, 0 },
1260  { 2168, 1, 1, 1, 1153, 0 },
1261  { 78, 1, 1, 1, 1153, 0 },
1262  { 336, 1, 1, 1, 1153, 0 },
1263  { 594, 1, 1, 1, 1153, 0 },
1264  { 792, 1, 1, 1, 1153, 0 },
1265  { 982, 1, 1, 1, 1153, 0 },
1266  { 1577, 1, 1, 1, 1153, 0 },
1267  { 1739, 1, 1, 1, 1153, 0 },
1268  { 1901, 1, 1, 1, 1153, 0 },
1269  { 2063, 1, 1, 1, 1153, 0 },
1270  { 2238, 1, 1, 1, 1153, 0 },
1271  { 151, 1, 1, 1, 1153, 0 },
1272  { 409, 1, 1, 1, 1153, 0 },
1273  { 209, 14, 1, 9, 994, 10 },
1274  { 467, 17, 1, 9, 994, 10 },
1275  { 671, 20, 1, 9, 994, 10 },
1276  { 869, 23, 1, 9, 994, 10 },
1277  { 1468, 26, 1, 9, 994, 10 },
1278  { 1634, 29, 1, 9, 994, 10 },
1279  { 1796, 32, 1, 9, 994, 10 },
1280  { 1958, 35, 1, 9, 994, 10 },
1281  { 2120, 38, 1, 9, 994, 10 },
1282  { 2295, 41, 1, 9, 994, 10 },
1283  { 33, 44, 1, 9, 994, 10 },
1284  { 291, 47, 1, 9, 994, 10 },
1285  { 549, 50, 1, 9, 994, 10 },
1286  { 747, 53, 1, 9, 994, 10 },
1287  { 937, 56, 1, 9, 994, 10 },
1288  { 1532, 59, 1, 9, 994, 10 },
1289  { 124, 1, 148, 1, 2369, 0 },
1290  { 382, 1, 146, 1, 2369, 0 },
1291  { 640, 1, 144, 1, 2369, 0 },
1292  { 838, 1, 142, 1, 2369, 0 },
1293  { 212, 1, 161, 1, 3985, 0 },
1294  { 470, 1, 165, 1, 3985, 0 },
1295  { 674, 1, 165, 1, 3985, 0 },
1296  { 872, 1, 169, 1, 3985, 0 },
1297  { 1471, 1, 169, 1, 3985, 0 },
1298  { 1637, 1, 173, 1, 3985, 0 },
1299  { 1799, 1, 173, 1, 3985, 0 },
1300  { 1961, 1, 177, 1, 3985, 0 },
1301  { 2123, 1, 177, 1, 3985, 0 },
1302  { 2298, 1, 181, 1, 3985, 0 },
1303  { 37, 1, 181, 1, 3985, 0 },
1304  { 295, 1, 185, 1, 3985, 0 },
1305  { 553, 1, 185, 1, 3985, 0 },
1306  { 751, 1, 189, 1, 3985, 0 },
1307  { 941, 1, 189, 1, 3985, 0 },
1308  { 1536, 1, 193, 1, 3985, 0 },
1309  { 1698, 1, 193, 1, 3985, 0 },
1310  { 1860, 1, 197, 1, 3985, 0 },
1311  { 2022, 1, 197, 1, 3985, 0 },
1312  { 2181, 1, 201, 1, 3985, 0 },
1313  { 91, 1, 201, 1, 3985, 0 },
1314  { 349, 1, 205, 1, 3985, 0 },
1315  { 607, 1, 205, 1, 3985, 0 },
1316  { 805, 1, 209, 1, 3985, 0 },
1317  { 995, 1, 209, 1, 3985, 0 },
1318  { 1590, 1, 213, 1, 3985, 0 },
1319  { 1752, 1, 213, 1, 3985, 0 },
1320  { 1914, 1, 217, 1, 3985, 0 },
1321  { 2076, 1, 217, 1, 3985, 0 },
1322  { 2251, 1, 221, 1, 3985, 0 },
1323  { 164, 1, 221, 1, 3985, 0 },
1324  { 422, 1, 225, 1, 3985, 0 },
1325  { 204, 1, 1, 1, 3985, 0 },
1326  { 462, 1, 1, 1, 3985, 0 },
1327  { 666, 1, 1, 1, 3985, 0 },
1328  { 864, 1, 1, 1, 3985, 0 },
1329  { 1463, 1, 1, 1, 3985, 0 },
1330  { 1629, 1, 1, 1, 3985, 0 },
1331  { 1791, 1, 1, 1, 3985, 0 },
1332  { 1953, 1, 1, 1, 3985, 0 },
1333  { 236, 1, 1, 1, 3985, 0 },
1334  { 494, 1, 1, 1, 3985, 0 },
1335  { 695, 1, 1, 1, 3985, 0 },
1336  { 885, 1, 1, 1, 3985, 0 },
1337  { 1480, 1, 1, 1, 3985, 0 },
1338  { 1646, 1, 1, 1, 3985, 0 },
1339  { 1808, 1, 1, 1, 3985, 0 },
1340  { 1970, 1, 1, 1, 3985, 0 },
1341  { 2132, 1, 1, 1, 3985, 0 },
1342  { 2307, 1, 1, 1, 3985, 0 },
1343  { 48, 1, 1, 1, 3985, 0 },
1344  { 306, 1, 1, 1, 3985, 0 },
1345  { 564, 1, 1, 1, 3985, 0 },
1346  { 762, 1, 1, 1, 3985, 0 },
1347  { 952, 1, 1, 1, 3985, 0 },
1348  { 1547, 1, 1, 1, 3985, 0 },
1349  { 1709, 1, 1, 1, 3985, 0 },
1350  { 1871, 1, 1, 1, 3985, 0 },
1351  { 2033, 1, 1, 1, 3985, 0 },
1352  { 2192, 1, 1, 1, 3985, 0 },
1353  { 108, 1, 1, 1, 3985, 0 },
1354  { 366, 1, 1, 1, 3985, 0 },
1355  { 624, 1, 1, 1, 3985, 0 },
1356  { 822, 1, 1, 1, 3985, 0 },
1357  { 1012, 1, 1, 1, 3985, 0 },
1358  { 1607, 1, 1, 1, 3985, 0 },
1359  { 1769, 1, 1, 1, 3985, 0 },
1360  { 1931, 1, 1, 1, 3985, 0 },
1361  { 2093, 1, 1, 1, 3985, 0 },
1362  { 2268, 1, 1, 1, 3985, 0 },
1363  { 181, 1, 1, 1, 3985, 0 },
1364  { 439, 1, 1, 1, 3985, 0 },
1365  { 1439, 136, 1, 0, 1184, 2 },
1366  { 215, 1, 158, 1, 3953, 0 },
1367  { 473, 1, 158, 1, 3953, 0 },
1368  { 677, 1, 158, 1, 3953, 0 },
1369  { 875, 1, 158, 1, 3953, 0 },
1370  { 1474, 1, 158, 1, 3953, 0 },
1371  { 1640, 1, 158, 1, 3953, 0 },
1372  { 1802, 1, 158, 1, 3953, 0 },
1373  { 1964, 1, 158, 1, 3953, 0 },
1374  { 2126, 1, 158, 1, 3953, 0 },
1375  { 2301, 1, 158, 1, 3953, 0 },
1376  { 41, 1, 158, 1, 3953, 0 },
1377  { 299, 1, 158, 1, 3953, 0 },
1378  { 557, 1, 158, 1, 3953, 0 },
1379  { 755, 1, 158, 1, 3953, 0 },
1380  { 945, 1, 158, 1, 3953, 0 },
1381  { 1540, 1, 158, 1, 3953, 0 },
1382  { 1702, 1, 158, 1, 3953, 0 },
1383  { 1864, 1, 158, 1, 3953, 0 },
1384  { 2026, 1, 158, 1, 3953, 0 },
1385  { 2185, 1, 158, 1, 3953, 0 },
1386  { 95, 1, 158, 1, 3953, 0 },
1387  { 353, 1, 158, 1, 3953, 0 },
1388  { 611, 1, 158, 1, 3953, 0 },
1389  { 809, 1, 158, 1, 3953, 0 },
1390  { 999, 1, 158, 1, 3953, 0 },
1391  { 1594, 1, 158, 1, 3953, 0 },
1392  { 1756, 1, 158, 1, 3953, 0 },
1393  { 1918, 1, 158, 1, 3953, 0 },
1394  { 2080, 1, 158, 1, 3953, 0 },
1395  { 2255, 1, 158, 1, 3953, 0 },
1396  { 168, 1, 158, 1, 3953, 0 },
1397  { 426, 1, 158, 1, 3953, 0 },
1398  { 1445, 128, 1, 0, 1216, 2 },
1399  { 217, 1, 233, 1, 1826, 0 },
1400  { 475, 1, 134, 1, 1826, 0 },
1401  { 679, 1, 134, 1, 1826, 0 },
1402  { 877, 1, 134, 1, 1826, 0 },
1403  { 241, 1, 1, 1, 3921, 0 },
1404  { 499, 1, 1, 1, 3921, 0 },
1405  { 700, 1, 1, 1, 3921, 0 },
1406  { 890, 1, 1, 1, 3921, 0 },
1407  { 1485, 1, 1, 1, 3921, 0 },
1408  { 1651, 1, 1, 1, 3921, 0 },
1409  { 1813, 1, 1, 1, 3921, 0 },
1410  { 1975, 1, 1, 1, 3921, 0 },
1411  { 2137, 1, 1, 1, 3921, 0 },
1412  { 2312, 1, 1, 1, 3921, 0 },
1413  { 54, 1, 1, 1, 3921, 0 },
1414  { 312, 1, 1, 1, 3921, 0 },
1415  { 570, 1, 1, 1, 3921, 0 },
1416  { 768, 1, 1, 1, 3921, 0 },
1417  { 958, 1, 1, 1, 3921, 0 },
1418  { 1553, 1, 1, 1, 3921, 0 },
1419  { 1715, 1, 1, 1, 3921, 0 },
1420  { 1877, 1, 1, 1, 3921, 0 },
1421  { 2039, 1, 1, 1, 3921, 0 },
1422  { 2198, 1, 1, 1, 3921, 0 },
1423  { 114, 1, 1, 1, 3921, 0 },
1424  { 372, 1, 1, 1, 3921, 0 },
1425  { 630, 1, 1, 1, 3921, 0 },
1426  { 828, 1, 1, 1, 3921, 0 },
1427  { 1018, 1, 1, 1, 3921, 0 },
1428  { 1613, 1, 1, 1, 3921, 0 },
1429  { 1775, 1, 1, 1, 3921, 0 },
1430  { 1937, 1, 1, 1, 3921, 0 },
1431  { 2099, 1, 1, 1, 3921, 0 },
1432  { 2274, 1, 1, 1, 3921, 0 },
1433  { 187, 1, 1, 1, 3921, 0 },
1434  { 445, 1, 1, 1, 3921, 0 },
1435  { 221, 1, 100, 1, 3921, 0 },
1436  { 479, 1, 100, 1, 3921, 0 },
1437  { 229, 1, 229, 1, 1794, 0 },
1438  { 487, 1, 126, 1, 1794, 0 },
1439  { 688, 1, 126, 1, 1794, 0 },
1440  { 881, 1, 126, 1, 1794, 0 },
1441  { 224, 1, 1, 1, 3889, 0 },
1442  { 482, 1, 1, 1, 3889, 0 },
1443  { 683, 1, 1, 1, 3889, 0 },
1444  { 2115, 1, 1, 1, 3889, 0 },
1445  { 2290, 1, 1, 1, 3889, 0 },
1446  { 27, 1, 1, 1, 3889, 0 },
1447  { 285, 1, 1, 1, 3889, 0 },
1448  { 543, 1, 1, 1, 3889, 0 },
1449  { 741, 1, 1, 1, 3889, 0 },
1450  { 931, 1, 1, 1, 3889, 0 },
1451  { 1526, 1, 1, 1, 3889, 0 },
1452  { 1692, 1, 1, 1, 3889, 0 },
1453  { 1854, 1, 1, 1, 3889, 0 },
1454  { 2016, 1, 1, 1, 3889, 0 },
1455  { 2175, 1, 1, 1, 3889, 0 },
1456  { 85, 1, 1, 1, 3889, 0 },
1457  { 343, 1, 1, 1, 3889, 0 },
1458  { 601, 1, 1, 1, 3889, 0 },
1459  { 799, 1, 1, 1, 3889, 0 },
1460  { 989, 1, 1, 1, 3889, 0 },
1461  { 1584, 1, 1, 1, 3889, 0 },
1462  { 1746, 1, 1, 1, 3889, 0 },
1463  { 1908, 1, 1, 1, 3889, 0 },
1464  { 2070, 1, 1, 1, 3889, 0 },
1465  { 2245, 1, 1, 1, 3889, 0 },
1466  { 158, 1, 1, 1, 3889, 0 },
1467  { 416, 1, 1, 1, 3889, 0 },
1468  { 233, 1, 1, 1, 3889, 0 },
1469  { 491, 1, 1, 1, 3889, 0 },
1470  { 692, 1, 1, 1, 3889, 0 },
1471  { 1425, 124, 1, 0, 1248, 2 },
1472  { 246, 1, 98, 1, 3857, 0 },
1473  { 504, 1, 98, 1, 3857, 0 },
1474  { 705, 1, 98, 1, 3857, 0 },
1475  { 895, 1, 98, 1, 3857, 0 },
1476  { 1490, 1, 98, 1, 3857, 0 },
1477  { 1656, 1, 98, 1, 3857, 0 },
1478  { 1818, 1, 98, 1, 3857, 0 },
1479  { 1980, 1, 98, 1, 3857, 0 },
1480  { 1451, 122, 1, 0, 1280, 2 },
1481  { 249, 1, 96, 1, 3825, 0 },
1482  { 507, 1, 96, 1, 3825, 0 },
1483  { 708, 1, 96, 1, 3825, 0 },
1484  { 898, 1, 96, 1, 3825, 0 },
1485  { 1493, 1, 96, 1, 3825, 0 },
1486  { 1659, 1, 96, 1, 3825, 0 },
1487  { 1821, 1, 96, 1, 3825, 0 },
1488  { 1983, 1, 96, 1, 3825, 0 },
1489  { 2142, 1, 96, 1, 3825, 0 },
1490  { 2317, 1, 96, 1, 3825, 0 },
1491  { 252, 1, 96, 1, 3825, 0 },
1492  { 510, 1, 96, 1, 3825, 0 },
1493  { 255, 92, 1, 8, 1425, 10 },
1494  { 513, 92, 1, 8, 1425, 10 },
1495  { 711, 92, 1, 8, 1425, 10 },
1496  { 901, 92, 1, 8, 1425, 10 },
1497  { 1496, 92, 1, 8, 1425, 10 },
1498  { 1662, 92, 1, 8, 1425, 10 },
1499  { 1824, 92, 1, 8, 1425, 10 },
1500  { 1986, 92, 1, 8, 1425, 10 },
1501  { 2145, 92, 1, 8, 1425, 10 },
1502  { 2320, 92, 1, 8, 1425, 10 },
1503  { 60, 92, 1, 8, 1425, 10 },
1504  { 318, 92, 1, 8, 1425, 10 },
1505  { 576, 92, 1, 8, 1425, 10 },
1506  { 774, 92, 1, 8, 1425, 10 },
1507  { 964, 92, 1, 8, 1425, 10 },
1508  { 1559, 92, 1, 8, 1425, 10 },
1509  { 1721, 92, 1, 8, 1425, 10 },
1510  { 1883, 92, 1, 8, 1425, 10 },
1511  { 2045, 92, 1, 8, 1425, 10 },
1512  { 2204, 92, 1, 8, 1425, 10 },
1513  { 120, 92, 1, 8, 1425, 10 },
1514  { 378, 92, 1, 8, 1425, 10 },
1515  { 636, 92, 1, 8, 1425, 10 },
1516  { 834, 92, 1, 8, 1425, 10 },
1517  { 1024, 92, 1, 8, 1425, 10 },
1518  { 1619, 92, 1, 8, 1425, 10 },
1519  { 1781, 92, 1, 8, 1425, 10 },
1520  { 1943, 92, 1, 8, 1425, 10 },
1521  { 2105, 92, 1, 8, 1425, 10 },
1522  { 2280, 92, 1, 8, 1425, 10 },
1523  { 193, 92, 1, 8, 1425, 10 },
1524  { 451, 92, 1, 8, 1425, 10 },
1525  { 1431, 118, 1, 0, 1921, 2 },
1526  { 1055, 118, 1, 0, 1921, 2 },
1527  { 1133, 118, 1, 0, 1921, 2 },
1528  { 1183, 118, 1, 0, 1921, 2 },
1529  { 1221, 118, 1, 0, 1921, 2 },
1530  { 1061, 130, 1, 12, 656, 10 },
1531  { 1068, 93, 159, 9, 1377, 10 },
1532  { 1139, 93, 159, 9, 1377, 10 },
1533  { 1189, 93, 159, 9, 1377, 10 },
1534  { 1227, 93, 159, 9, 1377, 10 },
1535  { 1259, 93, 159, 9, 1377, 10 },
1536  { 1291, 93, 159, 9, 1377, 10 },
1537  { 1323, 93, 159, 9, 1377, 10 },
1538  { 1355, 93, 159, 9, 1377, 10 },
1539  { 1387, 93, 159, 9, 1377, 10 },
1540  { 1413, 93, 159, 9, 1377, 10 },
1541  { 1034, 93, 159, 9, 1377, 10 },
1542  { 1112, 93, 159, 9, 1377, 10 },
1543  { 1169, 93, 159, 9, 1377, 10 },
1544  { 1207, 93, 159, 9, 1377, 10 },
1545  { 1245, 93, 159, 9, 1377, 10 },
1546  { 1277, 93, 159, 9, 1377, 10 },
1547  { 1309, 93, 159, 9, 1377, 10 },
1548  { 1341, 93, 159, 9, 1377, 10 },
1549  { 1373, 93, 159, 9, 1377, 10 },
1550  { 1399, 93, 159, 9, 1377, 10 },
1551  { 1041, 93, 159, 9, 1377, 10 },
1552  { 1119, 93, 159, 9, 1377, 10 },
1553  { 1176, 93, 159, 9, 1377, 10 },
1554  { 1214, 93, 159, 9, 1377, 10 },
1555  { 1252, 93, 159, 9, 1377, 10 },
1556  { 1284, 93, 159, 9, 1377, 10 },
1557  { 1316, 93, 159, 9, 1377, 10 },
1558  { 1348, 93, 159, 9, 1377, 10 },
1559  { 1380, 93, 159, 9, 1377, 10 },
1560  { 1406, 93, 159, 9, 1377, 10 },
1561  { 1048, 93, 159, 9, 1377, 10 },
1562  { 1126, 93, 159, 9, 1377, 10 },
1563  { 2208, 1, 116, 1, 1120, 0 },
1564  { 1074, 138, 235, 0, 1344, 2 },
1565  { 1081, 150, 1, 0, 2241, 2 },
1566  { 1145, 150, 1, 0, 2241, 2 },
1567  { 1087, 150, 231, 0, 1312, 2 },
1568  { 1094, 154, 1, 0, 2433, 2 },
1569  { 1151, 154, 1, 0, 2433, 2 },
1570  { 1195, 154, 1, 0, 2433, 2 },
1571  { 1233, 154, 1, 0, 2433, 2 },
1572  { 1265, 154, 1, 0, 2433, 2 },
1573  { 1297, 154, 1, 0, 2433, 2 },
1574  { 1329, 154, 1, 0, 2433, 2 },
1575  { 1361, 154, 1, 0, 2433, 2 },
1576  { 1100, 156, 1, 0, 2433, 2 },
1577  { 1157, 156, 1, 0, 2433, 2 },
1578  { 1201, 156, 1, 0, 2433, 2 },
1579  { 1239, 156, 1, 0, 2433, 2 },
1580  { 1271, 156, 1, 0, 2433, 2 },
1581  { 1303, 156, 1, 0, 2433, 2 },
1582  { 1335, 156, 1, 0, 2433, 2 },
1583  { 1367, 156, 1, 0, 2433, 2 },
1584  { 1393, 156, 1, 0, 2433, 2 },
1585  { 1419, 156, 1, 0, 2433, 2 },
1586  { 1106, 156, 1, 0, 2433, 2 },
1587  { 1163, 156, 1, 0, 2433, 2 },
1588};
1589
1590extern const MCPhysReg MipsRegUnitRoots[][2] = {
1591  { Mips::AT },
1592  { Mips::DSPCCond },
1593  { Mips::DSPCarry },
1594  { Mips::DSPEFI },
1595  { Mips::DSPOutFlag16_19 },
1596  { Mips::DSPOutFlag20 },
1597  { Mips::DSPOutFlag21 },
1598  { Mips::DSPOutFlag22 },
1599  { Mips::DSPOutFlag23 },
1600  { Mips::DSPPos },
1601  { Mips::DSPSCount },
1602  { Mips::FP },
1603  { Mips::GP },
1604  { Mips::MSAAccess },
1605  { Mips::MSACSR },
1606  { Mips::MSAIR },
1607  { Mips::MSAMap },
1608  { Mips::MSAModify },
1609  { Mips::MSARequest },
1610  { Mips::MSASave },
1611  { Mips::MSAUnmap },
1612  { Mips::PC },
1613  { Mips::RA },
1614  { Mips::SP },
1615  { Mips::ZERO },
1616  { Mips::A0 },
1617  { Mips::A1 },
1618  { Mips::A2 },
1619  { Mips::A3 },
1620  { Mips::LO0 },
1621  { Mips::HI0 },
1622  { Mips::LO1 },
1623  { Mips::HI1 },
1624  { Mips::LO2 },
1625  { Mips::HI2 },
1626  { Mips::LO3 },
1627  { Mips::HI3 },
1628  { Mips::COP00 },
1629  { Mips::COP01 },
1630  { Mips::COP02 },
1631  { Mips::COP03 },
1632  { Mips::COP04 },
1633  { Mips::COP05 },
1634  { Mips::COP06 },
1635  { Mips::COP07 },
1636  { Mips::COP08 },
1637  { Mips::COP09 },
1638  { Mips::COP20 },
1639  { Mips::COP21 },
1640  { Mips::COP22 },
1641  { Mips::COP23 },
1642  { Mips::COP24 },
1643  { Mips::COP25 },
1644  { Mips::COP26 },
1645  { Mips::COP27 },
1646  { Mips::COP28 },
1647  { Mips::COP29 },
1648  { Mips::COP30 },
1649  { Mips::COP31 },
1650  { Mips::COP32 },
1651  { Mips::COP33 },
1652  { Mips::COP34 },
1653  { Mips::COP35 },
1654  { Mips::COP36 },
1655  { Mips::COP37 },
1656  { Mips::COP38 },
1657  { Mips::COP39 },
1658  { Mips::COP010 },
1659  { Mips::COP011 },
1660  { Mips::COP012 },
1661  { Mips::COP013 },
1662  { Mips::COP014 },
1663  { Mips::COP015 },
1664  { Mips::COP016 },
1665  { Mips::COP017 },
1666  { Mips::COP018 },
1667  { Mips::COP019 },
1668  { Mips::COP020 },
1669  { Mips::COP021 },
1670  { Mips::COP022 },
1671  { Mips::COP023 },
1672  { Mips::COP024 },
1673  { Mips::COP025 },
1674  { Mips::COP026 },
1675  { Mips::COP027 },
1676  { Mips::COP028 },
1677  { Mips::COP029 },
1678  { Mips::COP030 },
1679  { Mips::COP031 },
1680  { Mips::COP210 },
1681  { Mips::COP211 },
1682  { Mips::COP212 },
1683  { Mips::COP213 },
1684  { Mips::COP214 },
1685  { Mips::COP215 },
1686  { Mips::COP216 },
1687  { Mips::COP217 },
1688  { Mips::COP218 },
1689  { Mips::COP219 },
1690  { Mips::COP220 },
1691  { Mips::COP221 },
1692  { Mips::COP222 },
1693  { Mips::COP223 },
1694  { Mips::COP224 },
1695  { Mips::COP225 },
1696  { Mips::COP226 },
1697  { Mips::COP227 },
1698  { Mips::COP228 },
1699  { Mips::COP229 },
1700  { Mips::COP230 },
1701  { Mips::COP231 },
1702  { Mips::COP310 },
1703  { Mips::COP311 },
1704  { Mips::COP312 },
1705  { Mips::COP313 },
1706  { Mips::COP314 },
1707  { Mips::COP315 },
1708  { Mips::COP316 },
1709  { Mips::COP317 },
1710  { Mips::COP318 },
1711  { Mips::COP319 },
1712  { Mips::COP320 },
1713  { Mips::COP321 },
1714  { Mips::COP322 },
1715  { Mips::COP323 },
1716  { Mips::COP324 },
1717  { Mips::COP325 },
1718  { Mips::COP326 },
1719  { Mips::COP327 },
1720  { Mips::COP328 },
1721  { Mips::COP329 },
1722  { Mips::COP330 },
1723  { Mips::COP331 },
1724  { Mips::F0 },
1725  { Mips::F1 },
1726  { Mips::F2 },
1727  { Mips::F3 },
1728  { Mips::F4 },
1729  { Mips::F5 },
1730  { Mips::F6 },
1731  { Mips::F7 },
1732  { Mips::F8 },
1733  { Mips::F9 },
1734  { Mips::F10 },
1735  { Mips::F11 },
1736  { Mips::F12 },
1737  { Mips::F13 },
1738  { Mips::F14 },
1739  { Mips::F15 },
1740  { Mips::F16 },
1741  { Mips::F17 },
1742  { Mips::F18 },
1743  { Mips::F19 },
1744  { Mips::F20 },
1745  { Mips::F21 },
1746  { Mips::F22 },
1747  { Mips::F23 },
1748  { Mips::F24 },
1749  { Mips::F25 },
1750  { Mips::F26 },
1751  { Mips::F27 },
1752  { Mips::F28 },
1753  { Mips::F29 },
1754  { Mips::F30 },
1755  { Mips::F31 },
1756  { Mips::FCC0 },
1757  { Mips::FCC1 },
1758  { Mips::FCC2 },
1759  { Mips::FCC3 },
1760  { Mips::FCC4 },
1761  { Mips::FCC5 },
1762  { Mips::FCC6 },
1763  { Mips::FCC7 },
1764  { Mips::FCR0 },
1765  { Mips::FCR1 },
1766  { Mips::FCR2 },
1767  { Mips::FCR3 },
1768  { Mips::FCR4 },
1769  { Mips::FCR5 },
1770  { Mips::FCR6 },
1771  { Mips::FCR7 },
1772  { Mips::FCR8 },
1773  { Mips::FCR9 },
1774  { Mips::FCR10 },
1775  { Mips::FCR11 },
1776  { Mips::FCR12 },
1777  { Mips::FCR13 },
1778  { Mips::FCR14 },
1779  { Mips::FCR15 },
1780  { Mips::FCR16 },
1781  { Mips::FCR17 },
1782  { Mips::FCR18 },
1783  { Mips::FCR19 },
1784  { Mips::FCR20 },
1785  { Mips::FCR21 },
1786  { Mips::FCR22 },
1787  { Mips::FCR23 },
1788  { Mips::FCR24 },
1789  { Mips::FCR25 },
1790  { Mips::FCR26 },
1791  { Mips::FCR27 },
1792  { Mips::FCR28 },
1793  { Mips::FCR29 },
1794  { Mips::FCR30 },
1795  { Mips::FCR31 },
1796  { Mips::F_HI0 },
1797  { Mips::F_HI1 },
1798  { Mips::F_HI2 },
1799  { Mips::F_HI3 },
1800  { Mips::F_HI4 },
1801  { Mips::F_HI5 },
1802  { Mips::F_HI6 },
1803  { Mips::F_HI7 },
1804  { Mips::F_HI8 },
1805  { Mips::F_HI9 },
1806  { Mips::F_HI10 },
1807  { Mips::F_HI11 },
1808  { Mips::F_HI12 },
1809  { Mips::F_HI13 },
1810  { Mips::F_HI14 },
1811  { Mips::F_HI15 },
1812  { Mips::F_HI16 },
1813  { Mips::F_HI17 },
1814  { Mips::F_HI18 },
1815  { Mips::F_HI19 },
1816  { Mips::F_HI20 },
1817  { Mips::F_HI21 },
1818  { Mips::F_HI22 },
1819  { Mips::F_HI23 },
1820  { Mips::F_HI24 },
1821  { Mips::F_HI25 },
1822  { Mips::F_HI26 },
1823  { Mips::F_HI27 },
1824  { Mips::F_HI28 },
1825  { Mips::F_HI29 },
1826  { Mips::F_HI30 },
1827  { Mips::F_HI31 },
1828  { Mips::HWR0 },
1829  { Mips::HWR1 },
1830  { Mips::HWR2 },
1831  { Mips::HWR3 },
1832  { Mips::HWR4 },
1833  { Mips::HWR5 },
1834  { Mips::HWR6 },
1835  { Mips::HWR7 },
1836  { Mips::HWR8 },
1837  { Mips::HWR9 },
1838  { Mips::HWR10 },
1839  { Mips::HWR11 },
1840  { Mips::HWR12 },
1841  { Mips::HWR13 },
1842  { Mips::HWR14 },
1843  { Mips::HWR15 },
1844  { Mips::HWR16 },
1845  { Mips::HWR17 },
1846  { Mips::HWR18 },
1847  { Mips::HWR19 },
1848  { Mips::HWR20 },
1849  { Mips::HWR21 },
1850  { Mips::HWR22 },
1851  { Mips::HWR23 },
1852  { Mips::HWR24 },
1853  { Mips::HWR25 },
1854  { Mips::HWR26 },
1855  { Mips::HWR27 },
1856  { Mips::HWR28 },
1857  { Mips::HWR29 },
1858  { Mips::HWR30 },
1859  { Mips::HWR31 },
1860  { Mips::K0 },
1861  { Mips::K1 },
1862  { Mips::MPL0 },
1863  { Mips::MPL1 },
1864  { Mips::MPL2 },
1865  { Mips::MSA8 },
1866  { Mips::MSA9 },
1867  { Mips::MSA10 },
1868  { Mips::MSA11 },
1869  { Mips::MSA12 },
1870  { Mips::MSA13 },
1871  { Mips::MSA14 },
1872  { Mips::MSA15 },
1873  { Mips::MSA16 },
1874  { Mips::MSA17 },
1875  { Mips::MSA18 },
1876  { Mips::MSA19 },
1877  { Mips::MSA20 },
1878  { Mips::MSA21 },
1879  { Mips::MSA22 },
1880  { Mips::MSA23 },
1881  { Mips::MSA24 },
1882  { Mips::MSA25 },
1883  { Mips::MSA26 },
1884  { Mips::MSA27 },
1885  { Mips::MSA28 },
1886  { Mips::MSA29 },
1887  { Mips::MSA30 },
1888  { Mips::MSA31 },
1889  { Mips::P0 },
1890  { Mips::P1 },
1891  { Mips::P2 },
1892  { Mips::S0 },
1893  { Mips::S1 },
1894  { Mips::S2 },
1895  { Mips::S3 },
1896  { Mips::S4 },
1897  { Mips::S5 },
1898  { Mips::S6 },
1899  { Mips::S7 },
1900  { Mips::T0 },
1901  { Mips::T1 },
1902  { Mips::T2 },
1903  { Mips::T3 },
1904  { Mips::T4 },
1905  { Mips::T5 },
1906  { Mips::T6 },
1907  { Mips::T7 },
1908  { Mips::T8 },
1909  { Mips::T9 },
1910  { Mips::V0 },
1911  { Mips::V1 },
1912};
1913
1914namespace {     // Register classes...
1915  // MSA128F16 Register Class...
1916  const MCPhysReg MSA128F16[] = {
1917    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
1918  };
1919
1920  // MSA128F16 Bit set.
1921  const uint8_t MSA128F16Bits[] = {
1922    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1923  };
1924
1925  // CCR Register Class...
1926  const MCPhysReg CCR[] = {
1927    Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31,
1928  };
1929
1930  // CCR Bit set.
1931  const uint8_t CCRBits[] = {
1932    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1933  };
1934
1935  // COP0 Register Class...
1936  const MCPhysReg COP0[] = {
1937    Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031,
1938  };
1939
1940  // COP0 Bit set.
1941  const uint8_t COP0Bits[] = {
1942    0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07,
1943  };
1944
1945  // COP2 Register Class...
1946  const MCPhysReg COP2[] = {
1947    Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231,
1948  };
1949
1950  // COP2 Bit set.
1951  const uint8_t COP2Bits[] = {
1952    0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01,
1953  };
1954
1955  // COP3 Register Class...
1956  const MCPhysReg COP3[] = {
1957    Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331,
1958  };
1959
1960  // COP3 Bit set.
1961  const uint8_t COP3Bits[] = {
1962    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f,
1963  };
1964
1965  // DSPR Register Class...
1966  const MCPhysReg DSPR[] = {
1967    Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
1968  };
1969
1970  // DSPR Bit set.
1971  const uint8_t DSPRBits[] = {
1972    0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
1973  };
1974
1975  // FGR32 Register Class...
1976  const MCPhysReg FGR32[] = {
1977    Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
1978  };
1979
1980  // FGR32 Bit set.
1981  const uint8_t FGR32Bits[] = {
1982    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1983  };
1984
1985  // FGRCC Register Class...
1986  const MCPhysReg FGRCC[] = {
1987    Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
1988  };
1989
1990  // FGRCC Bit set.
1991  const uint8_t FGRCCBits[] = {
1992    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1993  };
1994
1995  // GPR32 Register Class...
1996  const MCPhysReg GPR32[] = {
1997    Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
1998  };
1999
2000  // GPR32 Bit set.
2001  const uint8_t GPR32Bits[] = {
2002    0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
2003  };
2004
2005  // HWRegs Register Class...
2006  const MCPhysReg HWRegs[] = {
2007    Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31,
2008  };
2009
2010  // HWRegs Bit set.
2011  const uint8_t HWRegsBits[] = {
2012    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2013  };
2014
2015  // MSACtrl Register Class...
2016  const MCPhysReg MSACtrl[] = {
2017    Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, Mips::MSA8, Mips::MSA9, Mips::MSA10, Mips::MSA11, Mips::MSA12, Mips::MSA13, Mips::MSA14, Mips::MSA15, Mips::MSA16, Mips::MSA17, Mips::MSA18, Mips::MSA19, Mips::MSA20, Mips::MSA21, Mips::MSA22, Mips::MSA23, Mips::MSA24, Mips::MSA25, Mips::MSA26, Mips::MSA27, Mips::MSA28, Mips::MSA29, Mips::MSA30, Mips::MSA31,
2018  };
2019
2020  // MSACtrl Bit set.
2021  const uint8_t MSACtrlBits[] = {
2022    0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03,
2023  };
2024
2025  // GPR32NONZERO Register Class...
2026  const MCPhysReg GPR32NONZERO[] = {
2027    Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
2028  };
2029
2030  // GPR32NONZERO Bit set.
2031  const uint8_t GPR32NONZEROBits[] = {
2032    0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
2033  };
2034
2035  // CPU16RegsPlusSP Register Class...
2036  const MCPhysReg CPU16RegsPlusSP[] = {
2037    Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP,
2038  };
2039
2040  // CPU16RegsPlusSP Bit set.
2041  const uint8_t CPU16RegsPlusSPBits[] = {
2042    0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2043  };
2044
2045  // CPU16Regs Register Class...
2046  const MCPhysReg CPU16Regs[] = {
2047    Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1,
2048  };
2049
2050  // CPU16Regs Bit set.
2051  const uint8_t CPU16RegsBits[] = {
2052    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2053  };
2054
2055  // FCC Register Class...
2056  const MCPhysReg FCC[] = {
2057    Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7,
2058  };
2059
2060  // FCC Bit set.
2061  const uint8_t FCCBits[] = {
2062    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2063  };
2064
2065  // GPRMM16 Register Class...
2066  const MCPhysReg GPRMM16[] = {
2067    Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2068  };
2069
2070  // GPRMM16 Bit set.
2071  const uint8_t GPRMM16Bits[] = {
2072    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2073  };
2074
2075  // GPRMM16MoveP Register Class...
2076  const MCPhysReg GPRMM16MoveP[] = {
2077    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
2078  };
2079
2080  // GPRMM16MoveP Bit set.
2081  const uint8_t GPRMM16MovePBits[] = {
2082    0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
2083  };
2084
2085  // GPRMM16Zero Register Class...
2086  const MCPhysReg GPRMM16Zero[] = {
2087    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2088  };
2089
2090  // GPRMM16Zero Bit set.
2091  const uint8_t GPRMM16ZeroBits[] = {
2092    0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2093  };
2094
2095  // CPU16Regs_and_GPRMM16Zero Register Class...
2096  const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
2097    Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2098  };
2099
2100  // CPU16Regs_and_GPRMM16Zero Bit set.
2101  const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {
2102    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2103  };
2104
2105  // GPR32NONZERO_and_GPRMM16MoveP Register Class...
2106  const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = {
2107    Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
2108  };
2109
2110  // GPR32NONZERO_and_GPRMM16MoveP Bit set.
2111  const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = {
2112    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
2113  };
2114
2115  // GPRMM16MovePPairSecond Register Class...
2116  const MCPhysReg GPRMM16MovePPairSecond[] = {
2117    Mips::A1, Mips::A2, Mips::A3, Mips::S5, Mips::S6,
2118  };
2119
2120  // GPRMM16MovePPairSecond Bit set.
2121  const uint8_t GPRMM16MovePPairSecondBits[] = {
2122    0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2123  };
2124
2125  // CPU16Regs_and_GPRMM16MoveP Register Class...
2126  const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
2127    Mips::S1, Mips::V0, Mips::V1, Mips::S0,
2128  };
2129
2130  // CPU16Regs_and_GPRMM16MoveP Bit set.
2131  const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {
2132    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2133  };
2134
2135  // GPRMM16MoveP_and_GPRMM16Zero Register Class...
2136  const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
2137    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1,
2138  };
2139
2140  // GPRMM16MoveP_and_GPRMM16Zero Bit set.
2141  const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
2142    0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2143  };
2144
2145  // HI32DSP Register Class...
2146  const MCPhysReg HI32DSP[] = {
2147    Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3,
2148  };
2149
2150  // HI32DSP Bit set.
2151  const uint8_t HI32DSPBits[] = {
2152    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
2153  };
2154
2155  // LO32DSP Register Class...
2156  const MCPhysReg LO32DSP[] = {
2157    Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3,
2158  };
2159
2160  // LO32DSP Bit set.
2161  const uint8_t LO32DSPBits[] = {
2162    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
2163  };
2164
2165  // CPU16Regs_and_GPRMM16MovePPairSecond Register Class...
2166  const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = {
2167    Mips::A1, Mips::A2, Mips::A3,
2168  };
2169
2170  // CPU16Regs_and_GPRMM16MovePPairSecond Bit set.
2171  const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {
2172    0x00, 0x00, 0x80, 0x03,
2173  };
2174
2175  // GPRMM16MovePPairFirst Register Class...
2176  const MCPhysReg GPRMM16MovePPairFirst[] = {
2177    Mips::A0, Mips::A1, Mips::A2,
2178  };
2179
2180  // GPRMM16MovePPairFirst Bit set.
2181  const uint8_t GPRMM16MovePPairFirstBits[] = {
2182    0x00, 0x00, 0xc0, 0x01,
2183  };
2184
2185  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
2186  const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2187    Mips::S1, Mips::V0, Mips::V1,
2188  };
2189
2190  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
2191  const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
2192    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2193  };
2194
2195  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...
2196  const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
2197    Mips::A1, Mips::A2,
2198  };
2199
2200  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.
2201  const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {
2202    0x00, 0x00, 0x80, 0x01,
2203  };
2204
2205  // CPURAReg Register Class...
2206  const MCPhysReg CPURAReg[] = {
2207    Mips::RA,
2208  };
2209
2210  // CPURAReg Bit set.
2211  const uint8_t CPURARegBits[] = {
2212    0x00, 0x00, 0x08,
2213  };
2214
2215  // CPUSPReg Register Class...
2216  const MCPhysReg CPUSPReg[] = {
2217    Mips::SP,
2218  };
2219
2220  // CPUSPReg Bit set.
2221  const uint8_t CPUSPRegBits[] = {
2222    0x00, 0x00, 0x10,
2223  };
2224
2225  // DSPCC Register Class...
2226  const MCPhysReg DSPCC[] = {
2227    Mips::DSPCCond,
2228  };
2229
2230  // DSPCC Bit set.
2231  const uint8_t DSPCCBits[] = {
2232    0x04,
2233  };
2234
2235  // GP32 Register Class...
2236  const MCPhysReg GP32[] = {
2237    Mips::GP,
2238  };
2239
2240  // GP32 Bit set.
2241  const uint8_t GP32Bits[] = {
2242    0x00, 0x02,
2243  };
2244
2245  // GPR32ZERO Register Class...
2246  const MCPhysReg GPR32ZERO[] = {
2247    Mips::ZERO,
2248  };
2249
2250  // GPR32ZERO Bit set.
2251  const uint8_t GPR32ZEROBits[] = {
2252    0x00, 0x00, 0x20,
2253  };
2254
2255  // HI32 Register Class...
2256  const MCPhysReg HI32[] = {
2257    Mips::HI0,
2258  };
2259
2260  // HI32 Bit set.
2261  const uint8_t HI32Bits[] = {
2262    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2263  };
2264
2265  // LO32 Register Class...
2266  const MCPhysReg LO32[] = {
2267    Mips::LO0,
2268  };
2269
2270  // LO32 Bit set.
2271  const uint8_t LO32Bits[] = {
2272    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2273  };
2274
2275  // SP32 Register Class...
2276  const MCPhysReg SP32[] = {
2277    Mips::SP,
2278  };
2279
2280  // SP32 Bit set.
2281  const uint8_t SP32Bits[] = {
2282    0x00, 0x00, 0x10,
2283  };
2284
2285  // FGR64 Register Class...
2286  const MCPhysReg FGR64[] = {
2287    Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64,
2288  };
2289
2290  // FGR64 Bit set.
2291  const uint8_t FGR64Bits[] = {
2292    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2293  };
2294
2295  // GPR64 Register Class...
2296  const MCPhysReg GPR64[] = {
2297    Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
2298  };
2299
2300  // GPR64 Bit set.
2301  const uint8_t GPR64Bits[] = {
2302    0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
2303  };
2304
2305  // GPR64_with_sub_32_in_GPR32NONZERO Register Class...
2306  const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = {
2307    Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
2308  };
2309
2310  // GPR64_with_sub_32_in_GPR32NONZERO Bit set.
2311  const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = {
2312    0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
2313  };
2314
2315  // AFGR64 Register Class...
2316  const MCPhysReg AFGR64[] = {
2317    Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,
2318  };
2319
2320  // AFGR64 Bit set.
2321  const uint8_t AFGR64Bits[] = {
2322    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2323  };
2324
2325  // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
2326  const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
2327    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64,
2328  };
2329
2330  // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
2331  const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
2332    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2333  };
2334
2335  // GPR64_with_sub_32_in_CPU16Regs Register Class...
2336  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
2337    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64,
2338  };
2339
2340  // GPR64_with_sub_32_in_CPU16Regs Bit set.
2341  const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
2342    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2343  };
2344
2345  // GPR64_with_sub_32_in_GPRMM16MoveP Register Class...
2346  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
2347    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
2348  };
2349
2350  // GPR64_with_sub_32_in_GPRMM16MoveP Bit set.
2351  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {
2352    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
2353  };
2354
2355  // GPR64_with_sub_32_in_GPRMM16Zero Register Class...
2356  const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
2357    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
2358  };
2359
2360  // GPR64_with_sub_32_in_GPRMM16Zero Bit set.
2361  const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {
2362    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2363  };
2364
2365  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...
2366  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
2367    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
2368  };
2369
2370  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.
2371  const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {
2372    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2373  };
2374
2375  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class...
2376  const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = {
2377    Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
2378  };
2379
2380  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set.
2381  const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = {
2382    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
2383  };
2384
2385  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class...
2386  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = {
2387    Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S5_64, Mips::S6_64,
2388  };
2389
2390  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set.
2391  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = {
2392    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2393  };
2394
2395  // ACC64DSP Register Class...
2396  const MCPhysReg ACC64DSP[] = {
2397    Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3,
2398  };
2399
2400  // ACC64DSP Bit set.
2401  const uint8_t ACC64DSPBits[] = {
2402    0x00, 0x00, 0x00, 0x3c,
2403  };
2404
2405  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...
2406  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
2407    Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64,
2408  };
2409
2410  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.
2411  const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {
2412    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2413  };
2414
2415  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...
2416  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
2417    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64,
2418  };
2419
2420  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.
2421  const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
2422    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2423  };
2424
2425  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class...
2426  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = {
2427    Mips::A1_64, Mips::A2_64, Mips::A3_64,
2428  };
2429
2430  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set.
2431  const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {
2432    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
2433  };
2434
2435  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class...
2436  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = {
2437    Mips::A0_64, Mips::A1_64, Mips::A2_64,
2438  };
2439
2440  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set.
2441  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = {
2442    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
2443  };
2444
2445  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
2446  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2447    Mips::V0_64, Mips::V1_64, Mips::S1_64,
2448  };
2449
2450  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
2451  const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
2452    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2453  };
2454
2455  // OCTEON_MPL Register Class...
2456  const MCPhysReg OCTEON_MPL[] = {
2457    Mips::MPL0, Mips::MPL1, Mips::MPL2,
2458  };
2459
2460  // OCTEON_MPL Bit set.
2461  const uint8_t OCTEON_MPLBits[] = {
2462    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
2463  };
2464
2465  // OCTEON_P Register Class...
2466  const MCPhysReg OCTEON_P[] = {
2467    Mips::P0, Mips::P1, Mips::P2,
2468  };
2469
2470  // OCTEON_P Bit set.
2471  const uint8_t OCTEON_PBits[] = {
2472    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
2473  };
2474
2475  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...
2476  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
2477    Mips::A1_64, Mips::A2_64,
2478  };
2479
2480  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.
2481  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {
2482    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
2483  };
2484
2485  // ACC64 Register Class...
2486  const MCPhysReg ACC64[] = {
2487    Mips::AC0,
2488  };
2489
2490  // ACC64 Bit set.
2491  const uint8_t ACC64Bits[] = {
2492    0x00, 0x00, 0x00, 0x04,
2493  };
2494
2495  // GP64 Register Class...
2496  const MCPhysReg GP64[] = {
2497    Mips::GP_64,
2498  };
2499
2500  // GP64 Bit set.
2501  const uint8_t GP64Bits[] = {
2502    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2503  };
2504
2505  // GPR64_with_sub_32_in_CPURAReg Register Class...
2506  const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
2507    Mips::RA_64,
2508  };
2509
2510  // GPR64_with_sub_32_in_CPURAReg Bit set.
2511  const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
2512    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2513  };
2514
2515  // GPR64_with_sub_32_in_GPR32ZERO Register Class...
2516  const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = {
2517    Mips::ZERO_64,
2518  };
2519
2520  // GPR64_with_sub_32_in_GPR32ZERO Bit set.
2521  const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = {
2522    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2523  };
2524
2525  // HI64 Register Class...
2526  const MCPhysReg HI64[] = {
2527    Mips::HI0_64,
2528  };
2529
2530  // HI64 Bit set.
2531  const uint8_t HI64Bits[] = {
2532    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2533  };
2534
2535  // LO64 Register Class...
2536  const MCPhysReg LO64[] = {
2537    Mips::LO0_64,
2538  };
2539
2540  // LO64 Bit set.
2541  const uint8_t LO64Bits[] = {
2542    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2543  };
2544
2545  // SP64 Register Class...
2546  const MCPhysReg SP64[] = {
2547    Mips::SP_64,
2548  };
2549
2550  // SP64 Bit set.
2551  const uint8_t SP64Bits[] = {
2552    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2553  };
2554
2555  // MSA128B Register Class...
2556  const MCPhysReg MSA128B[] = {
2557    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2558  };
2559
2560  // MSA128B Bit set.
2561  const uint8_t MSA128BBits[] = {
2562    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2563  };
2564
2565  // MSA128D Register Class...
2566  const MCPhysReg MSA128D[] = {
2567    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2568  };
2569
2570  // MSA128D Bit set.
2571  const uint8_t MSA128DBits[] = {
2572    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2573  };
2574
2575  // MSA128H Register Class...
2576  const MCPhysReg MSA128H[] = {
2577    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2578  };
2579
2580  // MSA128H Bit set.
2581  const uint8_t MSA128HBits[] = {
2582    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2583  };
2584
2585  // MSA128W Register Class...
2586  const MCPhysReg MSA128W[] = {
2587    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2588  };
2589
2590  // MSA128W Bit set.
2591  const uint8_t MSA128WBits[] = {
2592    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2593  };
2594
2595  // MSA128WEvens Register Class...
2596  const MCPhysReg MSA128WEvens[] = {
2597    Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30,
2598  };
2599
2600  // MSA128WEvens Bit set.
2601  const uint8_t MSA128WEvensBits[] = {
2602    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,
2603  };
2604
2605  // ACC128 Register Class...
2606  const MCPhysReg ACC128[] = {
2607    Mips::AC0_64,
2608  };
2609
2610  // ACC128 Bit set.
2611  const uint8_t ACC128Bits[] = {
2612    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
2613  };
2614
2615} // end anonymous namespace
2616
2617extern const char MipsRegClassStrings[] = {
2618  /* 0 */ 'C', 'O', 'P', '0', 0,
2619  /* 5 */ 'H', 'I', '3', '2', 0,
2620  /* 10 */ 'L', 'O', '3', '2', 0,
2621  /* 15 */ 'G', 'P', '3', '2', 0,
2622  /* 20 */ 'S', 'P', '3', '2', 0,
2623  /* 25 */ 'F', 'G', 'R', '3', '2', 0,
2624  /* 31 */ 'G', 'P', 'R', '3', '2', 0,
2625  /* 37 */ 'C', 'O', 'P', '2', 0,
2626  /* 42 */ 'C', 'O', 'P', '3', 0,
2627  /* 47 */ 'A', 'C', 'C', '6', '4', 0,
2628  /* 53 */ 'H', 'I', '6', '4', 0,
2629  /* 58 */ 'L', 'O', '6', '4', 0,
2630  /* 63 */ 'G', 'P', '6', '4', 0,
2631  /* 68 */ 'S', 'P', '6', '4', 0,
2632  /* 73 */ 'A', 'F', 'G', 'R', '6', '4', 0,
2633  /* 80 */ 'G', 'P', 'R', '6', '4', 0,
2634  /* 86 */ 'M', 'S', 'A', '1', '2', '8', 'F', '1', '6', 0,
2635  /* 96 */ 'G', 'P', 'R', 'M', 'M', '1', '6', 0,
2636  /* 104 */ 'A', 'C', 'C', '1', '2', '8', 0,
2637  /* 111 */ 'M', 'S', 'A', '1', '2', '8', 'B', 0,
2638  /* 119 */ 'F', 'C', 'C', 0,
2639  /* 123 */ 'D', 'S', 'P', 'C', 'C', 0,
2640  /* 129 */ 'F', 'G', 'R', 'C', 'C', 0,
2641  /* 135 */ 'M', 'S', 'A', '1', '2', '8', 'D', 0,
2642  /* 143 */ 'M', 'S', 'A', '1', '2', '8', 'H', 0,
2643  /* 151 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'M', 'P', 'L', 0,
2644  /* 162 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'Z', 'E', 'R', 'O', 0,
2645  /* 193 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'N', 'O', 'N', 'Z', 'E', 'R', 'O', 0,
2646  /* 227 */ 'H', 'I', '3', '2', 'D', 'S', 'P', 0,
2647  /* 235 */ 'L', 'O', '3', '2', 'D', 'S', 'P', 0,
2648  /* 243 */ 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0,
2649  /* 252 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 'P', 'l', 'u', 's', 'S', 'P', 0,
2650  /* 289 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'P', 0,
2651  /* 298 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'N', 'O', 'N', 'Z', 'E', 'R', 'O', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
2652  /* 349 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
2653  /* 397 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
2654  /* 431 */ 'C', 'C', 'R', 0,
2655  /* 435 */ 'D', 'S', 'P', 'R', 0,
2656  /* 440 */ 'M', 'S', 'A', '1', '2', '8', 'W', 0,
2657  /* 448 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'S', 'e', 'c', 'o', 'n', 'd', 0,
2658  /* 506 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'F', 'i', 'r', 's', 't', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'S', 'e', 'c', 'o', 'n', 'd', 0,
2659  /* 576 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'S', 'e', 'c', 'o', 'n', 'd', 0,
2660  /* 620 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', 'R', 'A', 'R', 'e', 'g', 0,
2661  /* 650 */ 'C', 'P', 'U', 'S', 'P', 'R', 'e', 'g', 0,
2662  /* 659 */ 'M', 'S', 'A', 'C', 't', 'r', 'l', 0,
2663  /* 667 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2664  /* 717 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2665  /* 781 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2666  /* 828 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
2667  /* 861 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 0,
2668  /* 892 */ 'H', 'W', 'R', 'e', 'g', 's', 0,
2669  /* 899 */ 'M', 'S', 'A', '1', '2', '8', 'W', 'E', 'v', 'e', 'n', 's', 0,
2670  /* 912 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'F', 'i', 'r', 's', 't', 0,
2671};
2672
2673extern const MCRegisterClass MipsMCRegisterClasses[] = {
2674  { MSA128F16, MSA128F16Bits, 86, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 1, true },
2675  { CCR, CCRBits, 431, 32, sizeof(CCRBits), Mips::CCRRegClassID, 1, false },
2676  { COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 1, false },
2677  { COP2, COP2Bits, 37, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 1, false },
2678  { COP3, COP3Bits, 42, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 1, false },
2679  { DSPR, DSPRBits, 435, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 1, true },
2680  { FGR32, FGR32Bits, 25, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 1, true },
2681  { FGRCC, FGRCCBits, 129, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 1, true },
2682  { GPR32, GPR32Bits, 31, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 1, true },
2683  { HWRegs, HWRegsBits, 892, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 1, false },
2684  { MSACtrl, MSACtrlBits, 659, 32, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 1, false },
2685  { GPR32NONZERO, GPR32NONZEROBits, 214, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 1, true },
2686  { CPU16RegsPlusSP, CPU16RegsPlusSPBits, 273, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 1, true },
2687  { CPU16Regs, CPU16RegsBits, 882, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 1, true },
2688  { FCC, FCCBits, 119, 8, sizeof(FCCBits), Mips::FCCRegClassID, 1, false },
2689  { GPRMM16, GPRMM16Bits, 96, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 1, true },
2690  { GPRMM16MoveP, GPRMM16MovePBits, 336, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 1, true },
2691  { GPRMM16Zero, GPRMM16ZeroBits, 705, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 1, true },
2692  { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 755, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 1, true },
2693  { GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 319, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 1, true },
2694  { GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, 483, 5, sizeof(GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairSecondRegClassID, 1, true },
2695  { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 370, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 1, true },
2696  { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 688, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 1, true },
2697  { HI32DSP, HI32DSPBits, 227, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 1, true },
2698  { LO32DSP, LO32DSPBits, 235, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 1, true },
2699  { CPU16Regs_and_GPRMM16MovePPairSecond, CPU16Regs_and_GPRMM16MovePPairSecondBits, 469, 3, sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 1, true },
2700  { GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, 933, 3, sizeof(GPRMM16MovePPairFirstBits), Mips::GPRMM16MovePPairFirstRegClassID, 1, true },
2701  { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 738, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 1, true },
2702  { GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 527, 2, sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 1, true },
2703  { CPURAReg, CPURARegBits, 641, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 1, false },
2704  { CPUSPReg, CPUSPRegBits, 650, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 1, false },
2705  { DSPCC, DSPCCBits, 123, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 1, true },
2706  { GP32, GP32Bits, 15, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 1, false },
2707  { GPR32ZERO, GPR32ZEROBits, 183, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 1, true },
2708  { HI32, HI32Bits, 5, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 1, true },
2709  { LO32, LO32Bits, 10, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 1, true },
2710  { SP32, SP32Bits, 20, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 1, false },
2711  { FGR64, FGR64Bits, 74, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 1, true },
2712  { GPR64, GPR64Bits, 80, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 1, true },
2713  { GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 193, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 1, true },
2714  { AFGR64, AFGR64Bits, 73, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 1, true },
2715  { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 252, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 1, true },
2716  { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 861, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 1, true },
2717  { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 397, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 1, true },
2718  { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 828, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 1, true },
2719  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 781, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 1, true },
2720  { GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 298, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 1, true },
2721  { GPR64_with_sub_32_in_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, 576, 5, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, 1, true },
2722  { ACC64DSP, ACC64DSPBits, 243, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 1, true },
2723  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 349, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 1, true },
2724  { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 667, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 1, true },
2725  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, 448, 3, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 1, true },
2726  { GPR64_with_sub_32_in_GPRMM16MovePPairFirst, GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, 912, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, 1, true },
2727  { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 717, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 1, true },
2728  { OCTEON_MPL, OCTEON_MPLBits, 151, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 1, false },
2729  { OCTEON_P, OCTEON_PBits, 289, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 1, false },
2730  { GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 506, 2, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 1, true },
2731  { ACC64, ACC64Bits, 47, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 1, true },
2732  { GP64, GP64Bits, 63, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 1, false },
2733  { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 620, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 1, true },
2734  { GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 162, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 1, true },
2735  { HI64, HI64Bits, 53, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 1, true },
2736  { LO64, LO64Bits, 58, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 1, true },
2737  { SP64, SP64Bits, 68, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 1, false },
2738  { MSA128B, MSA128BBits, 111, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 1, true },
2739  { MSA128D, MSA128DBits, 135, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 1, true },
2740  { MSA128H, MSA128HBits, 143, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 1, true },
2741  { MSA128W, MSA128WBits, 440, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 1, true },
2742  { MSA128WEvens, MSA128WEvensBits, 899, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 1, true },
2743  { ACC128, ACC128Bits, 104, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 1, true },
2744};
2745
2746// Mips Dwarf<->LLVM register mappings.
2747extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {
2748  { 0U, Mips::ZERO_64 },
2749  { 1U, Mips::AT_64 },
2750  { 2U, Mips::V0_64 },
2751  { 3U, Mips::V1_64 },
2752  { 4U, Mips::A0_64 },
2753  { 5U, Mips::A1_64 },
2754  { 6U, Mips::A2_64 },
2755  { 7U, Mips::A3_64 },
2756  { 8U, Mips::T0_64 },
2757  { 9U, Mips::T1_64 },
2758  { 10U, Mips::T2_64 },
2759  { 11U, Mips::T3_64 },
2760  { 12U, Mips::T4_64 },
2761  { 13U, Mips::T5_64 },
2762  { 14U, Mips::T6_64 },
2763  { 15U, Mips::T7_64 },
2764  { 16U, Mips::S0_64 },
2765  { 17U, Mips::S1_64 },
2766  { 18U, Mips::S2_64 },
2767  { 19U, Mips::S3_64 },
2768  { 20U, Mips::S4_64 },
2769  { 21U, Mips::S5_64 },
2770  { 22U, Mips::S6_64 },
2771  { 23U, Mips::S7_64 },
2772  { 24U, Mips::T8_64 },
2773  { 25U, Mips::T9_64 },
2774  { 26U, Mips::K0_64 },
2775  { 27U, Mips::K1_64 },
2776  { 28U, Mips::GP_64 },
2777  { 29U, Mips::SP_64 },
2778  { 30U, Mips::FP_64 },
2779  { 31U, Mips::RA_64 },
2780  { 32U, Mips::D0_64 },
2781  { 33U, Mips::D1_64 },
2782  { 34U, Mips::D2_64 },
2783  { 35U, Mips::D3_64 },
2784  { 36U, Mips::D4_64 },
2785  { 37U, Mips::D5_64 },
2786  { 38U, Mips::D6_64 },
2787  { 39U, Mips::D7_64 },
2788  { 40U, Mips::D8_64 },
2789  { 41U, Mips::D9_64 },
2790  { 42U, Mips::D10_64 },
2791  { 43U, Mips::D11_64 },
2792  { 44U, Mips::D12_64 },
2793  { 45U, Mips::D13_64 },
2794  { 46U, Mips::D14_64 },
2795  { 47U, Mips::D15_64 },
2796  { 48U, Mips::D16_64 },
2797  { 49U, Mips::D17_64 },
2798  { 50U, Mips::D18_64 },
2799  { 51U, Mips::D19_64 },
2800  { 52U, Mips::D20_64 },
2801  { 53U, Mips::D21_64 },
2802  { 54U, Mips::D22_64 },
2803  { 55U, Mips::D23_64 },
2804  { 56U, Mips::D24_64 },
2805  { 57U, Mips::D25_64 },
2806  { 58U, Mips::D26_64 },
2807  { 59U, Mips::D27_64 },
2808  { 60U, Mips::D28_64 },
2809  { 61U, Mips::D29_64 },
2810  { 62U, Mips::D30_64 },
2811  { 63U, Mips::D31_64 },
2812  { 64U, Mips::HI0 },
2813  { 65U, Mips::LO0 },
2814  { 176U, Mips::HI1 },
2815  { 177U, Mips::LO1 },
2816  { 178U, Mips::HI2 },
2817  { 179U, Mips::LO2 },
2818  { 180U, Mips::HI3 },
2819  { 181U, Mips::LO3 },
2820};
2821extern const unsigned MipsDwarfFlavour0Dwarf2LSize = array_lengthof(MipsDwarfFlavour0Dwarf2L);
2822
2823extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {
2824  { 0U, Mips::ZERO_64 },
2825  { 1U, Mips::AT_64 },
2826  { 2U, Mips::V0_64 },
2827  { 3U, Mips::V1_64 },
2828  { 4U, Mips::A0_64 },
2829  { 5U, Mips::A1_64 },
2830  { 6U, Mips::A2_64 },
2831  { 7U, Mips::A3_64 },
2832  { 8U, Mips::T0_64 },
2833  { 9U, Mips::T1_64 },
2834  { 10U, Mips::T2_64 },
2835  { 11U, Mips::T3_64 },
2836  { 12U, Mips::T4_64 },
2837  { 13U, Mips::T5_64 },
2838  { 14U, Mips::T6_64 },
2839  { 15U, Mips::T7_64 },
2840  { 16U, Mips::S0_64 },
2841  { 17U, Mips::S1_64 },
2842  { 18U, Mips::S2_64 },
2843  { 19U, Mips::S3_64 },
2844  { 20U, Mips::S4_64 },
2845  { 21U, Mips::S5_64 },
2846  { 22U, Mips::S6_64 },
2847  { 23U, Mips::S7_64 },
2848  { 24U, Mips::T8_64 },
2849  { 25U, Mips::T9_64 },
2850  { 26U, Mips::K0_64 },
2851  { 27U, Mips::K1_64 },
2852  { 28U, Mips::GP_64 },
2853  { 29U, Mips::SP_64 },
2854  { 30U, Mips::FP_64 },
2855  { 31U, Mips::RA_64 },
2856  { 32U, Mips::D0_64 },
2857  { 33U, Mips::D1_64 },
2858  { 34U, Mips::D2_64 },
2859  { 35U, Mips::D3_64 },
2860  { 36U, Mips::D4_64 },
2861  { 37U, Mips::D5_64 },
2862  { 38U, Mips::D6_64 },
2863  { 39U, Mips::D7_64 },
2864  { 40U, Mips::D8_64 },
2865  { 41U, Mips::D9_64 },
2866  { 42U, Mips::D10_64 },
2867  { 43U, Mips::D11_64 },
2868  { 44U, Mips::D12_64 },
2869  { 45U, Mips::D13_64 },
2870  { 46U, Mips::D14_64 },
2871  { 47U, Mips::D15_64 },
2872  { 48U, Mips::D16_64 },
2873  { 49U, Mips::D17_64 },
2874  { 50U, Mips::D18_64 },
2875  { 51U, Mips::D19_64 },
2876  { 52U, Mips::D20_64 },
2877  { 53U, Mips::D21_64 },
2878  { 54U, Mips::D22_64 },
2879  { 55U, Mips::D23_64 },
2880  { 56U, Mips::D24_64 },
2881  { 57U, Mips::D25_64 },
2882  { 58U, Mips::D26_64 },
2883  { 59U, Mips::D27_64 },
2884  { 60U, Mips::D28_64 },
2885  { 61U, Mips::D29_64 },
2886  { 62U, Mips::D30_64 },
2887  { 63U, Mips::D31_64 },
2888  { 64U, Mips::HI0 },
2889  { 65U, Mips::LO0 },
2890  { 176U, Mips::HI1 },
2891  { 177U, Mips::LO1 },
2892  { 178U, Mips::HI2 },
2893  { 179U, Mips::LO2 },
2894  { 180U, Mips::HI3 },
2895  { 181U, Mips::LO3 },
2896};
2897extern const unsigned MipsEHFlavour0Dwarf2LSize = array_lengthof(MipsEHFlavour0Dwarf2L);
2898
2899extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {
2900  { Mips::AT, 1U },
2901  { Mips::FP, 30U },
2902  { Mips::GP, 28U },
2903  { Mips::RA, 31U },
2904  { Mips::SP, 29U },
2905  { Mips::ZERO, 0U },
2906  { Mips::A0, 4U },
2907  { Mips::A1, 5U },
2908  { Mips::A2, 6U },
2909  { Mips::A3, 7U },
2910  { Mips::AT_64, 1U },
2911  { Mips::F0, 32U },
2912  { Mips::F1, 33U },
2913  { Mips::F2, 34U },
2914  { Mips::F3, 35U },
2915  { Mips::F4, 36U },
2916  { Mips::F5, 37U },
2917  { Mips::F6, 38U },
2918  { Mips::F7, 39U },
2919  { Mips::F8, 40U },
2920  { Mips::F9, 41U },
2921  { Mips::F10, 42U },
2922  { Mips::F11, 43U },
2923  { Mips::F12, 44U },
2924  { Mips::F13, 45U },
2925  { Mips::F14, 46U },
2926  { Mips::F15, 47U },
2927  { Mips::F16, 48U },
2928  { Mips::F17, 49U },
2929  { Mips::F18, 50U },
2930  { Mips::F19, 51U },
2931  { Mips::F20, 52U },
2932  { Mips::F21, 53U },
2933  { Mips::F22, 54U },
2934  { Mips::F23, 55U },
2935  { Mips::F24, 56U },
2936  { Mips::F25, 57U },
2937  { Mips::F26, 58U },
2938  { Mips::F27, 59U },
2939  { Mips::F28, 60U },
2940  { Mips::F29, 61U },
2941  { Mips::F30, 62U },
2942  { Mips::F31, 63U },
2943  { Mips::FP_64, 30U },
2944  { Mips::F_HI0, 32U },
2945  { Mips::F_HI1, 33U },
2946  { Mips::F_HI2, 34U },
2947  { Mips::F_HI3, 35U },
2948  { Mips::F_HI4, 36U },
2949  { Mips::F_HI5, 37U },
2950  { Mips::F_HI6, 38U },
2951  { Mips::F_HI7, 39U },
2952  { Mips::F_HI8, 40U },
2953  { Mips::F_HI9, 41U },
2954  { Mips::F_HI10, 42U },
2955  { Mips::F_HI11, 43U },
2956  { Mips::F_HI12, 44U },
2957  { Mips::F_HI13, 45U },
2958  { Mips::F_HI14, 46U },
2959  { Mips::F_HI15, 47U },
2960  { Mips::F_HI16, 48U },
2961  { Mips::F_HI17, 49U },
2962  { Mips::F_HI18, 50U },
2963  { Mips::F_HI19, 51U },
2964  { Mips::F_HI20, 52U },
2965  { Mips::F_HI21, 53U },
2966  { Mips::F_HI22, 54U },
2967  { Mips::F_HI23, 55U },
2968  { Mips::F_HI24, 56U },
2969  { Mips::F_HI25, 57U },
2970  { Mips::F_HI26, 58U },
2971  { Mips::F_HI27, 59U },
2972  { Mips::F_HI28, 60U },
2973  { Mips::F_HI29, 61U },
2974  { Mips::F_HI30, 62U },
2975  { Mips::F_HI31, 63U },
2976  { Mips::GP_64, 28U },
2977  { Mips::HI0, 64U },
2978  { Mips::HI1, 176U },
2979  { Mips::HI2, 178U },
2980  { Mips::HI3, 180U },
2981  { Mips::K0, 26U },
2982  { Mips::K1, 27U },
2983  { Mips::LO0, 65U },
2984  { Mips::LO1, 177U },
2985  { Mips::LO2, 179U },
2986  { Mips::LO3, 181U },
2987  { Mips::RA_64, 31U },
2988  { Mips::S0, 16U },
2989  { Mips::S1, 17U },
2990  { Mips::S2, 18U },
2991  { Mips::S3, 19U },
2992  { Mips::S4, 20U },
2993  { Mips::S5, 21U },
2994  { Mips::S6, 22U },
2995  { Mips::S7, 23U },
2996  { Mips::SP_64, 29U },
2997  { Mips::T0, 8U },
2998  { Mips::T1, 9U },
2999  { Mips::T2, 10U },
3000  { Mips::T3, 11U },
3001  { Mips::T4, 12U },
3002  { Mips::T5, 13U },
3003  { Mips::T6, 14U },
3004  { Mips::T7, 15U },
3005  { Mips::T8, 24U },
3006  { Mips::T9, 25U },
3007  { Mips::V0, 2U },
3008  { Mips::V1, 3U },
3009  { Mips::W0, 32U },
3010  { Mips::W1, 33U },
3011  { Mips::W2, 34U },
3012  { Mips::W3, 35U },
3013  { Mips::W4, 36U },
3014  { Mips::W5, 37U },
3015  { Mips::W6, 38U },
3016  { Mips::W7, 39U },
3017  { Mips::W8, 40U },
3018  { Mips::W9, 41U },
3019  { Mips::W10, 42U },
3020  { Mips::W11, 43U },
3021  { Mips::W12, 44U },
3022  { Mips::W13, 45U },
3023  { Mips::W14, 46U },
3024  { Mips::W15, 47U },
3025  { Mips::W16, 48U },
3026  { Mips::W17, 49U },
3027  { Mips::W18, 50U },
3028  { Mips::W19, 51U },
3029  { Mips::W20, 52U },
3030  { Mips::W21, 53U },
3031  { Mips::W22, 54U },
3032  { Mips::W23, 55U },
3033  { Mips::W24, 56U },
3034  { Mips::W25, 57U },
3035  { Mips::W26, 58U },
3036  { Mips::W27, 59U },
3037  { Mips::W28, 60U },
3038  { Mips::W29, 61U },
3039  { Mips::W30, 62U },
3040  { Mips::W31, 63U },
3041  { Mips::ZERO_64, 0U },
3042  { Mips::A0_64, 4U },
3043  { Mips::A1_64, 5U },
3044  { Mips::A2_64, 6U },
3045  { Mips::A3_64, 7U },
3046  { Mips::D0_64, 32U },
3047  { Mips::D1_64, 33U },
3048  { Mips::D2_64, 34U },
3049  { Mips::D3_64, 35U },
3050  { Mips::D4_64, 36U },
3051  { Mips::D5_64, 37U },
3052  { Mips::D6_64, 38U },
3053  { Mips::D7_64, 39U },
3054  { Mips::D8_64, 40U },
3055  { Mips::D9_64, 41U },
3056  { Mips::D10_64, 42U },
3057  { Mips::D11_64, 43U },
3058  { Mips::D12_64, 44U },
3059  { Mips::D13_64, 45U },
3060  { Mips::D14_64, 46U },
3061  { Mips::D15_64, 47U },
3062  { Mips::D16_64, 48U },
3063  { Mips::D17_64, 49U },
3064  { Mips::D18_64, 50U },
3065  { Mips::D19_64, 51U },
3066  { Mips::D20_64, 52U },
3067  { Mips::D21_64, 53U },
3068  { Mips::D22_64, 54U },
3069  { Mips::D23_64, 55U },
3070  { Mips::D24_64, 56U },
3071  { Mips::D25_64, 57U },
3072  { Mips::D26_64, 58U },
3073  { Mips::D27_64, 59U },
3074  { Mips::D28_64, 60U },
3075  { Mips::D29_64, 61U },
3076  { Mips::D30_64, 62U },
3077  { Mips::D31_64, 63U },
3078  { Mips::K0_64, 26U },
3079  { Mips::K1_64, 27U },
3080  { Mips::S0_64, 16U },
3081  { Mips::S1_64, 17U },
3082  { Mips::S2_64, 18U },
3083  { Mips::S3_64, 19U },
3084  { Mips::S4_64, 20U },
3085  { Mips::S5_64, 21U },
3086  { Mips::S6_64, 22U },
3087  { Mips::S7_64, 23U },
3088  { Mips::T0_64, 8U },
3089  { Mips::T1_64, 9U },
3090  { Mips::T2_64, 10U },
3091  { Mips::T3_64, 11U },
3092  { Mips::T4_64, 12U },
3093  { Mips::T5_64, 13U },
3094  { Mips::T6_64, 14U },
3095  { Mips::T7_64, 15U },
3096  { Mips::T8_64, 24U },
3097  { Mips::T9_64, 25U },
3098  { Mips::V0_64, 2U },
3099  { Mips::V1_64, 3U },
3100};
3101extern const unsigned MipsDwarfFlavour0L2DwarfSize = array_lengthof(MipsDwarfFlavour0L2Dwarf);
3102
3103extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {
3104  { Mips::AT, 1U },
3105  { Mips::FP, 30U },
3106  { Mips::GP, 28U },
3107  { Mips::RA, 31U },
3108  { Mips::SP, 29U },
3109  { Mips::ZERO, 0U },
3110  { Mips::A0, 4U },
3111  { Mips::A1, 5U },
3112  { Mips::A2, 6U },
3113  { Mips::A3, 7U },
3114  { Mips::AT_64, 1U },
3115  { Mips::F0, 32U },
3116  { Mips::F1, 33U },
3117  { Mips::F2, 34U },
3118  { Mips::F3, 35U },
3119  { Mips::F4, 36U },
3120  { Mips::F5, 37U },
3121  { Mips::F6, 38U },
3122  { Mips::F7, 39U },
3123  { Mips::F8, 40U },
3124  { Mips::F9, 41U },
3125  { Mips::F10, 42U },
3126  { Mips::F11, 43U },
3127  { Mips::F12, 44U },
3128  { Mips::F13, 45U },
3129  { Mips::F14, 46U },
3130  { Mips::F15, 47U },
3131  { Mips::F16, 48U },
3132  { Mips::F17, 49U },
3133  { Mips::F18, 50U },
3134  { Mips::F19, 51U },
3135  { Mips::F20, 52U },
3136  { Mips::F21, 53U },
3137  { Mips::F22, 54U },
3138  { Mips::F23, 55U },
3139  { Mips::F24, 56U },
3140  { Mips::F25, 57U },
3141  { Mips::F26, 58U },
3142  { Mips::F27, 59U },
3143  { Mips::F28, 60U },
3144  { Mips::F29, 61U },
3145  { Mips::F30, 62U },
3146  { Mips::F31, 63U },
3147  { Mips::FP_64, 30U },
3148  { Mips::F_HI0, 32U },
3149  { Mips::F_HI1, 33U },
3150  { Mips::F_HI2, 34U },
3151  { Mips::F_HI3, 35U },
3152  { Mips::F_HI4, 36U },
3153  { Mips::F_HI5, 37U },
3154  { Mips::F_HI6, 38U },
3155  { Mips::F_HI7, 39U },
3156  { Mips::F_HI8, 40U },
3157  { Mips::F_HI9, 41U },
3158  { Mips::F_HI10, 42U },
3159  { Mips::F_HI11, 43U },
3160  { Mips::F_HI12, 44U },
3161  { Mips::F_HI13, 45U },
3162  { Mips::F_HI14, 46U },
3163  { Mips::F_HI15, 47U },
3164  { Mips::F_HI16, 48U },
3165  { Mips::F_HI17, 49U },
3166  { Mips::F_HI18, 50U },
3167  { Mips::F_HI19, 51U },
3168  { Mips::F_HI20, 52U },
3169  { Mips::F_HI21, 53U },
3170  { Mips::F_HI22, 54U },
3171  { Mips::F_HI23, 55U },
3172  { Mips::F_HI24, 56U },
3173  { Mips::F_HI25, 57U },
3174  { Mips::F_HI26, 58U },
3175  { Mips::F_HI27, 59U },
3176  { Mips::F_HI28, 60U },
3177  { Mips::F_HI29, 61U },
3178  { Mips::F_HI30, 62U },
3179  { Mips::F_HI31, 63U },
3180  { Mips::GP_64, 28U },
3181  { Mips::HI0, 64U },
3182  { Mips::HI1, 176U },
3183  { Mips::HI2, 178U },
3184  { Mips::HI3, 180U },
3185  { Mips::K0, 26U },
3186  { Mips::K1, 27U },
3187  { Mips::LO0, 65U },
3188  { Mips::LO1, 177U },
3189  { Mips::LO2, 179U },
3190  { Mips::LO3, 181U },
3191  { Mips::RA_64, 31U },
3192  { Mips::S0, 16U },
3193  { Mips::S1, 17U },
3194  { Mips::S2, 18U },
3195  { Mips::S3, 19U },
3196  { Mips::S4, 20U },
3197  { Mips::S5, 21U },
3198  { Mips::S6, 22U },
3199  { Mips::S7, 23U },
3200  { Mips::SP_64, 29U },
3201  { Mips::T0, 8U },
3202  { Mips::T1, 9U },
3203  { Mips::T2, 10U },
3204  { Mips::T3, 11U },
3205  { Mips::T4, 12U },
3206  { Mips::T5, 13U },
3207  { Mips::T6, 14U },
3208  { Mips::T7, 15U },
3209  { Mips::T8, 24U },
3210  { Mips::T9, 25U },
3211  { Mips::V0, 2U },
3212  { Mips::V1, 3U },
3213  { Mips::W0, 32U },
3214  { Mips::W1, 33U },
3215  { Mips::W2, 34U },
3216  { Mips::W3, 35U },
3217  { Mips::W4, 36U },
3218  { Mips::W5, 37U },
3219  { Mips::W6, 38U },
3220  { Mips::W7, 39U },
3221  { Mips::W8, 40U },
3222  { Mips::W9, 41U },
3223  { Mips::W10, 42U },
3224  { Mips::W11, 43U },
3225  { Mips::W12, 44U },
3226  { Mips::W13, 45U },
3227  { Mips::W14, 46U },
3228  { Mips::W15, 47U },
3229  { Mips::W16, 48U },
3230  { Mips::W17, 49U },
3231  { Mips::W18, 50U },
3232  { Mips::W19, 51U },
3233  { Mips::W20, 52U },
3234  { Mips::W21, 53U },
3235  { Mips::W22, 54U },
3236  { Mips::W23, 55U },
3237  { Mips::W24, 56U },
3238  { Mips::W25, 57U },
3239  { Mips::W26, 58U },
3240  { Mips::W27, 59U },
3241  { Mips::W28, 60U },
3242  { Mips::W29, 61U },
3243  { Mips::W30, 62U },
3244  { Mips::W31, 63U },
3245  { Mips::ZERO_64, 0U },
3246  { Mips::A0_64, 4U },
3247  { Mips::A1_64, 5U },
3248  { Mips::A2_64, 6U },
3249  { Mips::A3_64, 7U },
3250  { Mips::D0_64, 32U },
3251  { Mips::D1_64, 33U },
3252  { Mips::D2_64, 34U },
3253  { Mips::D3_64, 35U },
3254  { Mips::D4_64, 36U },
3255  { Mips::D5_64, 37U },
3256  { Mips::D6_64, 38U },
3257  { Mips::D7_64, 39U },
3258  { Mips::D8_64, 40U },
3259  { Mips::D9_64, 41U },
3260  { Mips::D10_64, 42U },
3261  { Mips::D11_64, 43U },
3262  { Mips::D12_64, 44U },
3263  { Mips::D13_64, 45U },
3264  { Mips::D14_64, 46U },
3265  { Mips::D15_64, 47U },
3266  { Mips::D16_64, 48U },
3267  { Mips::D17_64, 49U },
3268  { Mips::D18_64, 50U },
3269  { Mips::D19_64, 51U },
3270  { Mips::D20_64, 52U },
3271  { Mips::D21_64, 53U },
3272  { Mips::D22_64, 54U },
3273  { Mips::D23_64, 55U },
3274  { Mips::D24_64, 56U },
3275  { Mips::D25_64, 57U },
3276  { Mips::D26_64, 58U },
3277  { Mips::D27_64, 59U },
3278  { Mips::D28_64, 60U },
3279  { Mips::D29_64, 61U },
3280  { Mips::D30_64, 62U },
3281  { Mips::D31_64, 63U },
3282  { Mips::K0_64, 26U },
3283  { Mips::K1_64, 27U },
3284  { Mips::S0_64, 16U },
3285  { Mips::S1_64, 17U },
3286  { Mips::S2_64, 18U },
3287  { Mips::S3_64, 19U },
3288  { Mips::S4_64, 20U },
3289  { Mips::S5_64, 21U },
3290  { Mips::S6_64, 22U },
3291  { Mips::S7_64, 23U },
3292  { Mips::T0_64, 8U },
3293  { Mips::T1_64, 9U },
3294  { Mips::T2_64, 10U },
3295  { Mips::T3_64, 11U },
3296  { Mips::T4_64, 12U },
3297  { Mips::T5_64, 13U },
3298  { Mips::T6_64, 14U },
3299  { Mips::T7_64, 15U },
3300  { Mips::T8_64, 24U },
3301  { Mips::T9_64, 25U },
3302  { Mips::V0_64, 2U },
3303  { Mips::V1_64, 3U },
3304};
3305extern const unsigned MipsEHFlavour0L2DwarfSize = array_lengthof(MipsEHFlavour0L2Dwarf);
3306
3307extern const uint16_t MipsRegEncodingTable[] = {
3308  0,
3309  1,
3310  0,
3311  0,
3312  0,
3313  0,
3314  0,
3315  0,
3316  30,
3317  28,
3318  2,
3319  1,
3320  0,
3321  6,
3322  4,
3323  5,
3324  3,
3325  7,
3326  0,
3327  31,
3328  29,
3329  0,
3330  4,
3331  5,
3332  6,
3333  7,
3334  0,
3335  1,
3336  2,
3337  3,
3338  1,
3339  0,
3340  1,
3341  2,
3342  3,
3343  4,
3344  5,
3345  6,
3346  7,
3347  8,
3348  9,
3349  0,
3350  1,
3351  2,
3352  3,
3353  4,
3354  5,
3355  6,
3356  7,
3357  8,
3358  9,
3359  0,
3360  1,
3361  2,
3362  3,
3363  4,
3364  5,
3365  6,
3366  7,
3367  8,
3368  9,
3369  10,
3370  11,
3371  12,
3372  13,
3373  14,
3374  15,
3375  16,
3376  17,
3377  18,
3378  19,
3379  20,
3380  21,
3381  22,
3382  23,
3383  24,
3384  25,
3385  26,
3386  27,
3387  28,
3388  29,
3389  30,
3390  31,
3391  10,
3392  11,
3393  12,
3394  13,
3395  14,
3396  15,
3397  16,
3398  17,
3399  18,
3400  19,
3401  20,
3402  21,
3403  22,
3404  23,
3405  24,
3406  25,
3407  26,
3408  27,
3409  28,
3410  29,
3411  30,
3412  31,
3413  10,
3414  11,
3415  12,
3416  13,
3417  14,
3418  15,
3419  16,
3420  17,
3421  18,
3422  19,
3423  20,
3424  21,
3425  22,
3426  23,
3427  24,
3428  25,
3429  26,
3430  27,
3431  28,
3432  29,
3433  30,
3434  31,
3435  0,
3436  2,
3437  4,
3438  6,
3439  8,
3440  10,
3441  12,
3442  14,
3443  16,
3444  18,
3445  20,
3446  22,
3447  24,
3448  26,
3449  28,
3450  30,
3451  0,
3452  0,
3453  0,
3454  0,
3455  0,
3456  1,
3457  2,
3458  3,
3459  4,
3460  5,
3461  6,
3462  7,
3463  8,
3464  9,
3465  10,
3466  11,
3467  12,
3468  13,
3469  14,
3470  15,
3471  16,
3472  17,
3473  18,
3474  19,
3475  20,
3476  21,
3477  22,
3478  23,
3479  24,
3480  25,
3481  26,
3482  27,
3483  28,
3484  29,
3485  30,
3486  31,
3487  0,
3488  1,
3489  2,
3490  3,
3491  4,
3492  5,
3493  6,
3494  7,
3495  0,
3496  1,
3497  2,
3498  3,
3499  4,
3500  5,
3501  6,
3502  7,
3503  8,
3504  9,
3505  10,
3506  11,
3507  12,
3508  13,
3509  14,
3510  15,
3511  16,
3512  17,
3513  18,
3514  19,
3515  20,
3516  21,
3517  22,
3518  23,
3519  24,
3520  25,
3521  26,
3522  27,
3523  28,
3524  29,
3525  30,
3526  31,
3527  30,
3528  0,
3529  1,
3530  2,
3531  3,
3532  4,
3533  5,
3534  6,
3535  7,
3536  8,
3537  9,
3538  10,
3539  11,
3540  12,
3541  13,
3542  14,
3543  15,
3544  16,
3545  17,
3546  18,
3547  19,
3548  20,
3549  21,
3550  22,
3551  23,
3552  24,
3553  25,
3554  26,
3555  27,
3556  28,
3557  29,
3558  30,
3559  31,
3560  28,
3561  0,
3562  1,
3563  2,
3564  3,
3565  0,
3566  1,
3567  2,
3568  3,
3569  4,
3570  5,
3571  6,
3572  7,
3573  8,
3574  9,
3575  10,
3576  11,
3577  12,
3578  13,
3579  14,
3580  15,
3581  16,
3582  17,
3583  18,
3584  19,
3585  20,
3586  21,
3587  22,
3588  23,
3589  24,
3590  25,
3591  26,
3592  27,
3593  28,
3594  29,
3595  30,
3596  31,
3597  26,
3598  27,
3599  0,
3600  1,
3601  2,
3602  3,
3603  0,
3604  1,
3605  2,
3606  8,
3607  9,
3608  10,
3609  11,
3610  12,
3611  13,
3612  14,
3613  15,
3614  16,
3615  17,
3616  18,
3617  19,
3618  20,
3619  21,
3620  22,
3621  23,
3622  24,
3623  25,
3624  26,
3625  27,
3626  28,
3627  29,
3628  30,
3629  31,
3630  0,
3631  1,
3632  2,
3633  31,
3634  16,
3635  17,
3636  18,
3637  19,
3638  20,
3639  21,
3640  22,
3641  23,
3642  29,
3643  8,
3644  9,
3645  10,
3646  11,
3647  12,
3648  13,
3649  14,
3650  15,
3651  24,
3652  25,
3653  2,
3654  3,
3655  0,
3656  1,
3657  2,
3658  3,
3659  4,
3660  5,
3661  6,
3662  7,
3663  8,
3664  9,
3665  10,
3666  11,
3667  12,
3668  13,
3669  14,
3670  15,
3671  16,
3672  17,
3673  18,
3674  19,
3675  20,
3676  21,
3677  22,
3678  23,
3679  24,
3680  25,
3681  26,
3682  27,
3683  28,
3684  29,
3685  30,
3686  31,
3687  0,
3688  4,
3689  5,
3690  6,
3691  7,
3692  0,
3693  0,
3694  1,
3695  2,
3696  3,
3697  4,
3698  5,
3699  6,
3700  7,
3701  8,
3702  9,
3703  10,
3704  11,
3705  12,
3706  13,
3707  14,
3708  15,
3709  16,
3710  17,
3711  18,
3712  19,
3713  20,
3714  21,
3715  22,
3716  23,
3717  24,
3718  25,
3719  26,
3720  27,
3721  28,
3722  29,
3723  30,
3724  31,
3725  0,
3726  0,
3727  26,
3728  27,
3729  0,
3730  16,
3731  17,
3732  18,
3733  19,
3734  20,
3735  21,
3736  22,
3737  23,
3738  8,
3739  9,
3740  10,
3741  11,
3742  12,
3743  13,
3744  14,
3745  15,
3746  24,
3747  25,
3748  2,
3749  3,
3750};
3751static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3752  RI->InitMCRegisterInfo(MipsRegDesc, 442, RA, PC, MipsMCRegisterClasses, 70, MipsRegUnitRoots, 321, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12,
3753MipsSubRegIdxRanges, MipsRegEncodingTable);
3754
3755  switch (DwarfFlavour) {
3756  default:
3757    llvm_unreachable("Unknown DWARF flavour");
3758  case 0:
3759    RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
3760    break;
3761  }
3762  switch (EHFlavour) {
3763  default:
3764    llvm_unreachable("Unknown DWARF flavour");
3765  case 0:
3766    RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
3767    break;
3768  }
3769  switch (DwarfFlavour) {
3770  default:
3771    llvm_unreachable("Unknown DWARF flavour");
3772  case 0:
3773    RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
3774    break;
3775  }
3776  switch (EHFlavour) {
3777  default:
3778    llvm_unreachable("Unknown DWARF flavour");
3779  case 0:
3780    RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
3781    break;
3782  }
3783}
3784
3785} // end namespace llvm
3786
3787#endif // GET_REGINFO_MC_DESC
3788
3789/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3790|*                                                                            *|
3791|* Register Information Header Fragment                                       *|
3792|*                                                                            *|
3793|* Automatically generated file, do not edit!                                 *|
3794|*                                                                            *|
3795\*===----------------------------------------------------------------------===*/
3796
3797
3798#ifdef GET_REGINFO_HEADER
3799#undef GET_REGINFO_HEADER
3800
3801#include "llvm/CodeGen/TargetRegisterInfo.h"
3802
3803namespace llvm {
3804
3805class MipsFrameLowering;
3806
3807struct MipsGenRegisterInfo : public TargetRegisterInfo {
3808  explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
3809      unsigned PC = 0, unsigned HwMode = 0);
3810  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
3811  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3812  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3813  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
3814  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3815  unsigned getRegUnitWeight(unsigned RegUnit) const override;
3816  unsigned getNumRegPressureSets() const override;
3817  const char *getRegPressureSetName(unsigned Idx) const override;
3818  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
3819  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3820  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
3821  ArrayRef<const char *> getRegMaskNames() const override;
3822  ArrayRef<const uint32_t *> getRegMasks() const override;
3823  /// Devirtualized TargetFrameLowering.
3824  static const MipsFrameLowering *getFrameLowering(
3825      const MachineFunction &MF);
3826};
3827
3828namespace Mips { // Register classes
3829  extern const TargetRegisterClass MSA128F16RegClass;
3830  extern const TargetRegisterClass CCRRegClass;
3831  extern const TargetRegisterClass COP0RegClass;
3832  extern const TargetRegisterClass COP2RegClass;
3833  extern const TargetRegisterClass COP3RegClass;
3834  extern const TargetRegisterClass DSPRRegClass;
3835  extern const TargetRegisterClass FGR32RegClass;
3836  extern const TargetRegisterClass FGRCCRegClass;
3837  extern const TargetRegisterClass GPR32RegClass;
3838  extern const TargetRegisterClass HWRegsRegClass;
3839  extern const TargetRegisterClass MSACtrlRegClass;
3840  extern const TargetRegisterClass GPR32NONZERORegClass;
3841  extern const TargetRegisterClass CPU16RegsPlusSPRegClass;
3842  extern const TargetRegisterClass CPU16RegsRegClass;
3843  extern const TargetRegisterClass FCCRegClass;
3844  extern const TargetRegisterClass GPRMM16RegClass;
3845  extern const TargetRegisterClass GPRMM16MovePRegClass;
3846  extern const TargetRegisterClass GPRMM16ZeroRegClass;
3847  extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass;
3848  extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass;
3849  extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass;
3850  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass;
3851  extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3852  extern const TargetRegisterClass HI32DSPRegClass;
3853  extern const TargetRegisterClass LO32DSPRegClass;
3854  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
3855  extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass;
3856  extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3857  extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
3858  extern const TargetRegisterClass CPURARegRegClass;
3859  extern const TargetRegisterClass CPUSPRegRegClass;
3860  extern const TargetRegisterClass DSPCCRegClass;
3861  extern const TargetRegisterClass GP32RegClass;
3862  extern const TargetRegisterClass GPR32ZERORegClass;
3863  extern const TargetRegisterClass HI32RegClass;
3864  extern const TargetRegisterClass LO32RegClass;
3865  extern const TargetRegisterClass SP32RegClass;
3866  extern const TargetRegisterClass FGR64RegClass;
3867  extern const TargetRegisterClass GPR64RegClass;
3868  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass;
3869  extern const TargetRegisterClass AFGR64RegClass;
3870  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass;
3871  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass;
3872  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass;
3873  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass;
3874  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass;
3875  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass;
3876  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass;
3877  extern const TargetRegisterClass ACC64DSPRegClass;
3878  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass;
3879  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3880  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
3881  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass;
3882  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3883  extern const TargetRegisterClass OCTEON_MPLRegClass;
3884  extern const TargetRegisterClass OCTEON_PRegClass;
3885  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
3886  extern const TargetRegisterClass ACC64RegClass;
3887  extern const TargetRegisterClass GP64RegClass;
3888  extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass;
3889  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass;
3890  extern const TargetRegisterClass HI64RegClass;
3891  extern const TargetRegisterClass LO64RegClass;
3892  extern const TargetRegisterClass SP64RegClass;
3893  extern const TargetRegisterClass MSA128BRegClass;
3894  extern const TargetRegisterClass MSA128DRegClass;
3895  extern const TargetRegisterClass MSA128HRegClass;
3896  extern const TargetRegisterClass MSA128WRegClass;
3897  extern const TargetRegisterClass MSA128WEvensRegClass;
3898  extern const TargetRegisterClass ACC128RegClass;
3899} // end namespace Mips
3900
3901} // end namespace llvm
3902
3903#endif // GET_REGINFO_HEADER
3904
3905/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
3906|*                                                                            *|
3907|* Target Register and Register Classes Information                           *|
3908|*                                                                            *|
3909|* Automatically generated file, do not edit!                                 *|
3910|*                                                                            *|
3911\*===----------------------------------------------------------------------===*/
3912
3913
3914#ifdef GET_REGINFO_TARGET_DESC
3915#undef GET_REGINFO_TARGET_DESC
3916
3917namespace llvm {
3918
3919extern const MCRegisterClass MipsMCRegisterClasses[];
3920
3921static const MVT::SimpleValueType VTLists[] = {
3922  /* 0 */ MVT::i32, MVT::Other,
3923  /* 2 */ MVT::i64, MVT::Other,
3924  /* 4 */ MVT::f16, MVT::Other,
3925  /* 6 */ MVT::f32, MVT::Other,
3926  /* 8 */ MVT::f64, MVT::Other,
3927  /* 10 */ MVT::v16i8, MVT::Other,
3928  /* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other,
3929  /* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other,
3930  /* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other,
3931  /* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other,
3932  /* 24 */ MVT::Untyped, MVT::Other,
3933};
3934
3935static const char *const SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };
3936
3937
3938static const LaneBitmask SubRegIndexLaneMaskTable[] = {
3939  LaneBitmask::getAll(),
3940  LaneBitmask(0x00000001), // sub_32
3941  LaneBitmask(0x00000041), // sub_64
3942  LaneBitmask(0x00000002), // sub_dsp16_19
3943  LaneBitmask(0x00000004), // sub_dsp20
3944  LaneBitmask(0x00000008), // sub_dsp21
3945  LaneBitmask(0x00000010), // sub_dsp22
3946  LaneBitmask(0x00000020), // sub_dsp23
3947  LaneBitmask(0x00000040), // sub_hi
3948  LaneBitmask(0x00000001), // sub_lo
3949  LaneBitmask(0x00000040), // sub_hi_then_sub_32
3950  LaneBitmask(0x00000041), // sub_32_sub_hi_then_sub_32
3951 };
3952
3953
3954
3955static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
3956  // Mode = 0 (Default)
3957  { 16, 16, 128, VTLists+4 },    // MSA128F16
3958  { 32, 32, 32, VTLists+0 },    // CCR
3959  { 32, 32, 32, VTLists+0 },    // COP0
3960  { 32, 32, 32, VTLists+0 },    // COP2
3961  { 32, 32, 32, VTLists+0 },    // COP3
3962  { 32, 32, 32, VTLists+12 },    // DSPR
3963  { 32, 32, 32, VTLists+6 },    // FGR32
3964  { 32, 32, 32, VTLists+0 },    // FGRCC
3965  { 32, 32, 32, VTLists+0 },    // GPR32
3966  { 32, 32, 32, VTLists+0 },    // HWRegs
3967  { 32, 32, 32, VTLists+0 },    // MSACtrl
3968  { 32, 32, 32, VTLists+0 },    // GPR32NONZERO
3969  { 32, 32, 32, VTLists+0 },    // CPU16RegsPlusSP
3970  { 32, 32, 32, VTLists+0 },    // CPU16Regs
3971  { 32, 32, 32, VTLists+0 },    // FCC
3972  { 32, 32, 32, VTLists+0 },    // GPRMM16
3973  { 32, 32, 32, VTLists+0 },    // GPRMM16MoveP
3974  { 32, 32, 32, VTLists+0 },    // GPRMM16Zero
3975  { 32, 32, 32, VTLists+0 },    // CPU16Regs_and_GPRMM16Zero
3976  { 32, 32, 32, VTLists+0 },    // GPR32NONZERO_and_GPRMM16MoveP
3977  { 32, 32, 32, VTLists+0 },    // GPRMM16MovePPairSecond
3978  { 32, 32, 32, VTLists+0 },    // CPU16Regs_and_GPRMM16MoveP
3979  { 32, 32, 32, VTLists+0 },    // GPRMM16MoveP_and_GPRMM16Zero
3980  { 32, 32, 32, VTLists+0 },    // HI32DSP
3981  { 32, 32, 32, VTLists+0 },    // LO32DSP
3982  { 32, 32, 32, VTLists+0 },    // CPU16Regs_and_GPRMM16MovePPairSecond
3983  { 32, 32, 32, VTLists+0 },    // GPRMM16MovePPairFirst
3984  { 32, 32, 32, VTLists+0 },    // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
3985  { 32, 32, 32, VTLists+0 },    // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
3986  { 32, 32, 32, VTLists+0 },    // CPURAReg
3987  { 32, 32, 32, VTLists+0 },    // CPUSPReg
3988  { 32, 32, 32, VTLists+12 },    // DSPCC
3989  { 32, 32, 32, VTLists+0 },    // GP32
3990  { 32, 32, 32, VTLists+0 },    // GPR32ZERO
3991  { 32, 32, 32, VTLists+0 },    // HI32
3992  { 32, 32, 32, VTLists+0 },    // LO32
3993  { 32, 32, 32, VTLists+0 },    // SP32
3994  { 64, 64, 64, VTLists+8 },    // FGR64
3995  { 64, 64, 64, VTLists+2 },    // GPR64
3996  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPR32NONZERO
3997  { 64, 64, 64, VTLists+8 },    // AFGR64
3998  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16RegsPlusSP
3999  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs
4000  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MoveP
4001  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16Zero
4002  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
4003  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
4004  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
4005  { 64, 64, 64, VTLists+24 },    // ACC64DSP
4006  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
4007  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
4008  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
4009  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
4010  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4011  { 64, 64, 64, VTLists+2 },    // OCTEON_MPL
4012  { 64, 64, 64, VTLists+2 },    // OCTEON_P
4013  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4014  { 64, 64, 64, VTLists+24 },    // ACC64
4015  { 64, 64, 64, VTLists+2 },    // GP64
4016  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_CPURAReg
4017  { 64, 64, 64, VTLists+2 },    // GPR64_with_sub_32_in_GPR32ZERO
4018  { 64, 64, 64, VTLists+2 },    // HI64
4019  { 64, 64, 64, VTLists+2 },    // LO64
4020  { 64, 64, 64, VTLists+2 },    // SP64
4021  { 128, 128, 128, VTLists+10 },    // MSA128B
4022  { 128, 128, 128, VTLists+21 },    // MSA128D
4023  { 128, 128, 128, VTLists+15 },    // MSA128H
4024  { 128, 128, 128, VTLists+18 },    // MSA128W
4025  { 128, 128, 128, VTLists+18 },    // MSA128WEvens
4026  { 128, 128, 128, VTLists+24 },    // ACC128
4027};
4028
4029static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
4030
4031static const uint32_t MSA128F16SubClassMask[] = {
4032  0x00000001, 0x00000000, 0x0000001f,
4033};
4034
4035static const uint32_t CCRSubClassMask[] = {
4036  0x00000002, 0x00000000, 0x00000000,
4037};
4038
4039static const uint32_t COP0SubClassMask[] = {
4040  0x00000004, 0x00000000, 0x00000000,
4041};
4042
4043static const uint32_t COP2SubClassMask[] = {
4044  0x00000008, 0x00000000, 0x00000000,
4045};
4046
4047static const uint32_t COP3SubClassMask[] = {
4048  0x00000010, 0x00000000, 0x00000000,
4049};
4050
4051static const uint32_t DSPRSubClassMask[] = {
4052  0x7e7fb920, 0x00000013, 0x00000000,
4053  0x00000000, 0x9d3efec0, 0x00000000, // sub_32
4054};
4055
4056static const uint32_t FGR32SubClassMask[] = {
4057  0x000000c0, 0x00000000, 0x00000000,
4058  0x00000000, 0x00000100, 0x00000000, // sub_hi
4059  0x00000001, 0x00000120, 0x0000001f, // sub_lo
4060};
4061
4062static const uint32_t FGRCCSubClassMask[] = {
4063  0x000000c0, 0x00000000, 0x00000000,
4064  0x00000000, 0x00000100, 0x00000000, // sub_hi
4065  0x00000001, 0x00000120, 0x0000001f, // sub_lo
4066};
4067
4068static const uint32_t GPR32SubClassMask[] = {
4069  0x7e7fb900, 0x00000013, 0x00000000,
4070  0x00000000, 0x9d3efec0, 0x00000000, // sub_32
4071};
4072
4073static const uint32_t HWRegsSubClassMask[] = {
4074  0x00000200, 0x00000000, 0x00000000,
4075};
4076
4077static const uint32_t MSACtrlSubClassMask[] = {
4078  0x00000400, 0x00000000, 0x00000000,
4079};
4080
4081static const uint32_t GPR32NONZEROSubClassMask[] = {
4082  0x7e3cb800, 0x00000011, 0x00000000,
4083  0x00000000, 0x8d3ae680, 0x00000000, // sub_32
4084};
4085
4086static const uint32_t CPU16RegsPlusSPSubClassMask[] = {
4087  0x5e24b000, 0x00000010, 0x00000000,
4088  0x00000000, 0x813a2600, 0x00000000, // sub_32
4089};
4090
4091static const uint32_t CPU16RegsSubClassMask[] = {
4092  0x1e24a000, 0x00000000, 0x00000000,
4093  0x00000000, 0x013a2400, 0x00000000, // sub_32
4094};
4095
4096static const uint32_t FCCSubClassMask[] = {
4097  0x00004000, 0x00000000, 0x00000000,
4098};
4099
4100static const uint32_t GPRMM16SubClassMask[] = {
4101  0x1e248000, 0x00000000, 0x00000000,
4102  0x00000000, 0x013a2400, 0x00000000, // sub_32
4103};
4104
4105static const uint32_t GPRMM16MovePSubClassMask[] = {
4106  0x08690000, 0x00000002, 0x00000000,
4107  0x00000000, 0x10264800, 0x00000000, // sub_32
4108};
4109
4110static const uint32_t GPRMM16ZeroSubClassMask[] = {
4111  0x1e460000, 0x00000002, 0x00000000,
4112  0x00000000, 0x113c3000, 0x00000000, // sub_32
4113};
4114
4115static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4116  0x1e040000, 0x00000000, 0x00000000,
4117  0x00000000, 0x01382000, 0x00000000, // sub_32
4118};
4119
4120static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
4121  0x08280000, 0x00000000, 0x00000000,
4122  0x00000000, 0x00224000, 0x00000000, // sub_32
4123};
4124
4125static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {
4126  0x12100000, 0x00000000, 0x00000000,
4127  0x00000000, 0x01088000, 0x00000000, // sub_32
4128};
4129
4130static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
4131  0x08200000, 0x00000000, 0x00000000,
4132  0x00000000, 0x00220000, 0x00000000, // sub_32
4133};
4134
4135static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
4136  0x08400000, 0x00000002, 0x00000000,
4137  0x00000000, 0x10240000, 0x00000000, // sub_32
4138};
4139
4140static const uint32_t HI32DSPSubClassMask[] = {
4141  0x00800000, 0x00000004, 0x00000000,
4142  0x00000000, 0x20000000, 0x00000000, // sub_32
4143  0x00000000, 0x02010000, 0x00000000, // sub_hi
4144  0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32
4145};
4146
4147static const uint32_t LO32DSPSubClassMask[] = {
4148  0x01000000, 0x00000008, 0x00000000,
4149  0x00000000, 0x40000000, 0x00000020, // sub_32
4150  0x00000000, 0x02010000, 0x00000000, // sub_lo
4151};
4152
4153static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
4154  0x12000000, 0x00000000, 0x00000000,
4155  0x00000000, 0x01080000, 0x00000000, // sub_32
4156};
4157
4158static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {
4159  0x14000000, 0x00000000, 0x00000000,
4160  0x00000000, 0x01100000, 0x00000000, // sub_32
4161};
4162
4163static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4164  0x08000000, 0x00000000, 0x00000000,
4165  0x00000000, 0x00200000, 0x00000000, // sub_32
4166};
4167
4168static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
4169  0x10000000, 0x00000000, 0x00000000,
4170  0x00000000, 0x01000000, 0x00000000, // sub_32
4171};
4172
4173static const uint32_t CPURARegSubClassMask[] = {
4174  0x20000000, 0x00000000, 0x00000000,
4175  0x00000000, 0x08000000, 0x00000000, // sub_32
4176};
4177
4178static const uint32_t CPUSPRegSubClassMask[] = {
4179  0x40000000, 0x00000010, 0x00000000,
4180  0x00000000, 0x80000000, 0x00000000, // sub_32
4181};
4182
4183static const uint32_t DSPCCSubClassMask[] = {
4184  0x80000000, 0x00000000, 0x00000000,
4185};
4186
4187static const uint32_t GP32SubClassMask[] = {
4188  0x00000000, 0x00000001, 0x00000000,
4189  0x00000000, 0x04000000, 0x00000000, // sub_32
4190};
4191
4192static const uint32_t GPR32ZEROSubClassMask[] = {
4193  0x00000000, 0x00000002, 0x00000000,
4194  0x00000000, 0x10000000, 0x00000000, // sub_32
4195};
4196
4197static const uint32_t HI32SubClassMask[] = {
4198  0x00000000, 0x00000004, 0x00000000,
4199  0x00000000, 0x20000000, 0x00000000, // sub_32
4200  0x00000000, 0x02000000, 0x00000000, // sub_hi
4201  0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32
4202};
4203
4204static const uint32_t LO32SubClassMask[] = {
4205  0x00000000, 0x00000008, 0x00000000,
4206  0x00000000, 0x40000000, 0x00000020, // sub_32
4207  0x00000000, 0x02000000, 0x00000000, // sub_lo
4208};
4209
4210static const uint32_t SP32SubClassMask[] = {
4211  0x00000000, 0x00000010, 0x00000000,
4212  0x00000000, 0x80000000, 0x00000000, // sub_32
4213};
4214
4215static const uint32_t FGR64SubClassMask[] = {
4216  0x00000000, 0x00000020, 0x00000000,
4217  0x00000001, 0x00000000, 0x0000001f, // sub_64
4218};
4219
4220static const uint32_t GPR64SubClassMask[] = {
4221  0x00000000, 0x9d3efec0, 0x00000000,
4222};
4223
4224static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {
4225  0x00000000, 0x8d3ae680, 0x00000000,
4226};
4227
4228static const uint32_t AFGR64SubClassMask[] = {
4229  0x00000000, 0x00000100, 0x00000000,
4230};
4231
4232static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {
4233  0x00000000, 0x813a2600, 0x00000000,
4234};
4235
4236static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {
4237  0x00000000, 0x013a2400, 0x00000000,
4238};
4239
4240static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {
4241  0x00000000, 0x10264800, 0x00000000,
4242};
4243
4244static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {
4245  0x00000000, 0x113c3000, 0x00000000,
4246};
4247
4248static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4249  0x00000000, 0x01382000, 0x00000000,
4250};
4251
4252static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
4253  0x00000000, 0x00224000, 0x00000000,
4254};
4255
4256static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {
4257  0x00000000, 0x01088000, 0x00000000,
4258};
4259
4260static const uint32_t ACC64DSPSubClassMask[] = {
4261  0x00000000, 0x02010000, 0x00000000,
4262  0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32
4263};
4264
4265static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
4266  0x00000000, 0x00220000, 0x00000000,
4267};
4268
4269static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
4270  0x00000000, 0x10240000, 0x00000000,
4271};
4272
4273static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
4274  0x00000000, 0x01080000, 0x00000000,
4275};
4276
4277static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {
4278  0x00000000, 0x01100000, 0x00000000,
4279};
4280
4281static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4282  0x00000000, 0x00200000, 0x00000000,
4283};
4284
4285static const uint32_t OCTEON_MPLSubClassMask[] = {
4286  0x00000000, 0x00400000, 0x00000000,
4287};
4288
4289static const uint32_t OCTEON_PSubClassMask[] = {
4290  0x00000000, 0x00800000, 0x00000000,
4291};
4292
4293static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
4294  0x00000000, 0x01000000, 0x00000000,
4295};
4296
4297static const uint32_t ACC64SubClassMask[] = {
4298  0x00000000, 0x02000000, 0x00000000,
4299  0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32
4300};
4301
4302static const uint32_t GP64SubClassMask[] = {
4303  0x00000000, 0x04000000, 0x00000000,
4304};
4305
4306static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {
4307  0x00000000, 0x08000000, 0x00000000,
4308};
4309
4310static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {
4311  0x00000000, 0x10000000, 0x00000000,
4312};
4313
4314static const uint32_t HI64SubClassMask[] = {
4315  0x00000000, 0x20000000, 0x00000000,
4316  0x00000000, 0x00000000, 0x00000020, // sub_hi
4317};
4318
4319static const uint32_t LO64SubClassMask[] = {
4320  0x00000000, 0x40000000, 0x00000000,
4321  0x00000000, 0x00000000, 0x00000020, // sub_lo
4322};
4323
4324static const uint32_t SP64SubClassMask[] = {
4325  0x00000000, 0x80000000, 0x00000000,
4326};
4327
4328static const uint32_t MSA128BSubClassMask[] = {
4329  0x00000000, 0x00000000, 0x0000001f,
4330};
4331
4332static const uint32_t MSA128DSubClassMask[] = {
4333  0x00000000, 0x00000000, 0x0000001f,
4334};
4335
4336static const uint32_t MSA128HSubClassMask[] = {
4337  0x00000000, 0x00000000, 0x0000001f,
4338};
4339
4340static const uint32_t MSA128WSubClassMask[] = {
4341  0x00000000, 0x00000000, 0x0000001f,
4342};
4343
4344static const uint32_t MSA128WEvensSubClassMask[] = {
4345  0x00000000, 0x00000000, 0x00000010,
4346};
4347
4348static const uint32_t ACC128SubClassMask[] = {
4349  0x00000000, 0x00000000, 0x00000020,
4350};
4351
4352static const uint16_t SuperRegIdxSeqs[] = {
4353  /* 0 */ 1, 0,
4354  /* 2 */ 2, 0,
4355  /* 4 */ 8, 0,
4356  /* 6 */ 1, 9, 0,
4357  /* 9 */ 8, 9, 0,
4358  /* 12 */ 1, 8, 10, 0,
4359  /* 16 */ 11, 0,
4360};
4361
4362static const TargetRegisterClass *const FGR32Superclasses[] = {
4363  &Mips::FGRCCRegClass,
4364  nullptr
4365};
4366
4367static const TargetRegisterClass *const FGRCCSuperclasses[] = {
4368  &Mips::FGR32RegClass,
4369  nullptr
4370};
4371
4372static const TargetRegisterClass *const GPR32Superclasses[] = {
4373  &Mips::DSPRRegClass,
4374  nullptr
4375};
4376
4377static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = {
4378  &Mips::DSPRRegClass,
4379  &Mips::GPR32RegClass,
4380  nullptr
4381};
4382
4383static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = {
4384  &Mips::DSPRRegClass,
4385  &Mips::GPR32RegClass,
4386  &Mips::GPR32NONZERORegClass,
4387  nullptr
4388};
4389
4390static const TargetRegisterClass *const CPU16RegsSuperclasses[] = {
4391  &Mips::DSPRRegClass,
4392  &Mips::GPR32RegClass,
4393  &Mips::GPR32NONZERORegClass,
4394  &Mips::CPU16RegsPlusSPRegClass,
4395  nullptr
4396};
4397
4398static const TargetRegisterClass *const GPRMM16Superclasses[] = {
4399  &Mips::DSPRRegClass,
4400  &Mips::GPR32RegClass,
4401  &Mips::GPR32NONZERORegClass,
4402  &Mips::CPU16RegsPlusSPRegClass,
4403  &Mips::CPU16RegsRegClass,
4404  nullptr
4405};
4406
4407static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = {
4408  &Mips::DSPRRegClass,
4409  &Mips::GPR32RegClass,
4410  nullptr
4411};
4412
4413static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = {
4414  &Mips::DSPRRegClass,
4415  &Mips::GPR32RegClass,
4416  nullptr
4417};
4418
4419static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4420  &Mips::DSPRRegClass,
4421  &Mips::GPR32RegClass,
4422  &Mips::GPR32NONZERORegClass,
4423  &Mips::CPU16RegsPlusSPRegClass,
4424  &Mips::CPU16RegsRegClass,
4425  &Mips::GPRMM16RegClass,
4426  &Mips::GPRMM16ZeroRegClass,
4427  nullptr
4428};
4429
4430static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4431  &Mips::DSPRRegClass,
4432  &Mips::GPR32RegClass,
4433  &Mips::GPR32NONZERORegClass,
4434  &Mips::GPRMM16MovePRegClass,
4435  nullptr
4436};
4437
4438static const TargetRegisterClass *const GPRMM16MovePPairSecondSuperclasses[] = {
4439  &Mips::DSPRRegClass,
4440  &Mips::GPR32RegClass,
4441  &Mips::GPR32NONZERORegClass,
4442  nullptr
4443};
4444
4445static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4446  &Mips::DSPRRegClass,
4447  &Mips::GPR32RegClass,
4448  &Mips::GPR32NONZERORegClass,
4449  &Mips::CPU16RegsPlusSPRegClass,
4450  &Mips::CPU16RegsRegClass,
4451  &Mips::GPRMM16RegClass,
4452  &Mips::GPRMM16MovePRegClass,
4453  &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
4454  nullptr
4455};
4456
4457static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4458  &Mips::DSPRRegClass,
4459  &Mips::GPR32RegClass,
4460  &Mips::GPRMM16MovePRegClass,
4461  &Mips::GPRMM16ZeroRegClass,
4462  nullptr
4463};
4464
4465static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
4466  &Mips::DSPRRegClass,
4467  &Mips::GPR32RegClass,
4468  &Mips::GPR32NONZERORegClass,
4469  &Mips::CPU16RegsPlusSPRegClass,
4470  &Mips::CPU16RegsRegClass,
4471  &Mips::GPRMM16RegClass,
4472  &Mips::GPRMM16ZeroRegClass,
4473  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4474  &Mips::GPRMM16MovePPairSecondRegClass,
4475  nullptr
4476};
4477
4478static const TargetRegisterClass *const GPRMM16MovePPairFirstSuperclasses[] = {
4479  &Mips::DSPRRegClass,
4480  &Mips::GPR32RegClass,
4481  &Mips::GPR32NONZERORegClass,
4482  &Mips::CPU16RegsPlusSPRegClass,
4483  &Mips::CPU16RegsRegClass,
4484  &Mips::GPRMM16RegClass,
4485  &Mips::GPRMM16ZeroRegClass,
4486  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4487  nullptr
4488};
4489
4490static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4491  &Mips::DSPRRegClass,
4492  &Mips::GPR32RegClass,
4493  &Mips::GPR32NONZERORegClass,
4494  &Mips::CPU16RegsPlusSPRegClass,
4495  &Mips::CPU16RegsRegClass,
4496  &Mips::GPRMM16RegClass,
4497  &Mips::GPRMM16MovePRegClass,
4498  &Mips::GPRMM16ZeroRegClass,
4499  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4500  &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
4501  &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
4502  &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4503  nullptr
4504};
4505
4506static const TargetRegisterClass *const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
4507  &Mips::DSPRRegClass,
4508  &Mips::GPR32RegClass,
4509  &Mips::GPR32NONZERORegClass,
4510  &Mips::CPU16RegsPlusSPRegClass,
4511  &Mips::CPU16RegsRegClass,
4512  &Mips::GPRMM16RegClass,
4513  &Mips::GPRMM16ZeroRegClass,
4514  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4515  &Mips::GPRMM16MovePPairSecondRegClass,
4516  &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
4517  &Mips::GPRMM16MovePPairFirstRegClass,
4518  nullptr
4519};
4520
4521static const TargetRegisterClass *const CPURARegSuperclasses[] = {
4522  &Mips::DSPRRegClass,
4523  &Mips::GPR32RegClass,
4524  &Mips::GPR32NONZERORegClass,
4525  nullptr
4526};
4527
4528static const TargetRegisterClass *const CPUSPRegSuperclasses[] = {
4529  &Mips::DSPRRegClass,
4530  &Mips::GPR32RegClass,
4531  &Mips::GPR32NONZERORegClass,
4532  &Mips::CPU16RegsPlusSPRegClass,
4533  nullptr
4534};
4535
4536static const TargetRegisterClass *const GP32Superclasses[] = {
4537  &Mips::DSPRRegClass,
4538  &Mips::GPR32RegClass,
4539  &Mips::GPR32NONZERORegClass,
4540  nullptr
4541};
4542
4543static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = {
4544  &Mips::DSPRRegClass,
4545  &Mips::GPR32RegClass,
4546  &Mips::GPRMM16MovePRegClass,
4547  &Mips::GPRMM16ZeroRegClass,
4548  &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4549  nullptr
4550};
4551
4552static const TargetRegisterClass *const HI32Superclasses[] = {
4553  &Mips::HI32DSPRegClass,
4554  nullptr
4555};
4556
4557static const TargetRegisterClass *const LO32Superclasses[] = {
4558  &Mips::LO32DSPRegClass,
4559  nullptr
4560};
4561
4562static const TargetRegisterClass *const SP32Superclasses[] = {
4563  &Mips::DSPRRegClass,
4564  &Mips::GPR32RegClass,
4565  &Mips::GPR32NONZERORegClass,
4566  &Mips::CPU16RegsPlusSPRegClass,
4567  &Mips::CPUSPRegRegClass,
4568  nullptr
4569};
4570
4571static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {
4572  &Mips::GPR64RegClass,
4573  nullptr
4574};
4575
4576static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {
4577  &Mips::GPR64RegClass,
4578  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4579  nullptr
4580};
4581
4582static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {
4583  &Mips::GPR64RegClass,
4584  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4585  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4586  nullptr
4587};
4588
4589static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {
4590  &Mips::GPR64RegClass,
4591  nullptr
4592};
4593
4594static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {
4595  &Mips::GPR64RegClass,
4596  nullptr
4597};
4598
4599static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4600  &Mips::GPR64RegClass,
4601  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4602  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4603  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4604  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4605  nullptr
4606};
4607
4608static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4609  &Mips::GPR64RegClass,
4610  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4611  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4612  nullptr
4613};
4614
4615static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {
4616  &Mips::GPR64RegClass,
4617  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4618  nullptr
4619};
4620
4621static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4622  &Mips::GPR64RegClass,
4623  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4624  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4625  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4626  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4627  &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
4628  nullptr
4629};
4630
4631static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4632  &Mips::GPR64RegClass,
4633  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4634  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4635  nullptr
4636};
4637
4638static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
4639  &Mips::GPR64RegClass,
4640  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4641  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4642  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4643  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4644  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4645  &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
4646  nullptr
4647};
4648
4649static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {
4650  &Mips::GPR64RegClass,
4651  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4652  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4653  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4654  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4655  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4656  nullptr
4657};
4658
4659static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4660  &Mips::GPR64RegClass,
4661  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4662  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4663  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4664  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4665  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4666  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4667  &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
4668  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
4669  &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4670  nullptr
4671};
4672
4673static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
4674  &Mips::GPR64RegClass,
4675  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4676  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4677  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4678  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4679  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4680  &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
4681  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
4682  &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
4683  nullptr
4684};
4685
4686static const TargetRegisterClass *const ACC64Superclasses[] = {
4687  &Mips::ACC64DSPRegClass,
4688  nullptr
4689};
4690
4691static const TargetRegisterClass *const GP64Superclasses[] = {
4692  &Mips::GPR64RegClass,
4693  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4694  nullptr
4695};
4696
4697static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {
4698  &Mips::GPR64RegClass,
4699  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4700  nullptr
4701};
4702
4703static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {
4704  &Mips::GPR64RegClass,
4705  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4706  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4707  &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4708  nullptr
4709};
4710
4711static const TargetRegisterClass *const SP64Superclasses[] = {
4712  &Mips::GPR64RegClass,
4713  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4714  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4715  nullptr
4716};
4717
4718static const TargetRegisterClass *const MSA128BSuperclasses[] = {
4719  &Mips::MSA128F16RegClass,
4720  &Mips::MSA128DRegClass,
4721  &Mips::MSA128HRegClass,
4722  &Mips::MSA128WRegClass,
4723  nullptr
4724};
4725
4726static const TargetRegisterClass *const MSA128DSuperclasses[] = {
4727  &Mips::MSA128F16RegClass,
4728  &Mips::MSA128BRegClass,
4729  &Mips::MSA128HRegClass,
4730  &Mips::MSA128WRegClass,
4731  nullptr
4732};
4733
4734static const TargetRegisterClass *const MSA128HSuperclasses[] = {
4735  &Mips::MSA128F16RegClass,
4736  &Mips::MSA128BRegClass,
4737  &Mips::MSA128DRegClass,
4738  &Mips::MSA128WRegClass,
4739  nullptr
4740};
4741
4742static const TargetRegisterClass *const MSA128WSuperclasses[] = {
4743  &Mips::MSA128F16RegClass,
4744  &Mips::MSA128BRegClass,
4745  &Mips::MSA128DRegClass,
4746  &Mips::MSA128HRegClass,
4747  nullptr
4748};
4749
4750static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = {
4751  &Mips::MSA128F16RegClass,
4752  &Mips::MSA128BRegClass,
4753  &Mips::MSA128DRegClass,
4754  &Mips::MSA128HRegClass,
4755  &Mips::MSA128WRegClass,
4756  nullptr
4757};
4758
4759
4760static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF) {
4761    const auto & S = MF.getSubtarget<MipsSubtarget>();
4762    return S.isABI_O32() && !S.useOddSPReg();
4763  }
4764
4765static ArrayRef<MCPhysReg> FGR32GetRawAllocationOrder(const MachineFunction &MF) {
4766  static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };
4767  const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];
4768  const ArrayRef<MCPhysReg> Order[] = {
4769    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
4770    makeArrayRef(AltOrder1)
4771  };
4772  const unsigned Select = FGR32AltOrderSelect(MF);
4773  assert(Select < 2);
4774  return Order[Select];
4775}
4776
4777static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF) {
4778    const auto & S = MF.getSubtarget<MipsSubtarget>();
4779    return S.isABI_O32() && !S.useOddSPReg();
4780  }
4781
4782static ArrayRef<MCPhysReg> FGR64GetRawAllocationOrder(const MachineFunction &MF) {
4783  static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };
4784  const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];
4785  const ArrayRef<MCPhysReg> Order[] = {
4786    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
4787    makeArrayRef(AltOrder1)
4788  };
4789  const unsigned Select = FGR64AltOrderSelect(MF);
4790  assert(Select < 2);
4791  return Order[Select];
4792}
4793
4794namespace Mips {   // Register class instances
4795  extern const TargetRegisterClass MSA128F16RegClass = {
4796    &MipsMCRegisterClasses[MSA128F16RegClassID],
4797    MSA128F16SubClassMask,
4798    SuperRegIdxSeqs + 1,
4799    LaneBitmask(0x00000041),
4800    0,
4801    true, /* HasDisjunctSubRegs */
4802    false, /* CoveredBySubRegs */
4803    NullRegClasses,
4804    nullptr
4805  };
4806
4807  extern const TargetRegisterClass CCRRegClass = {
4808    &MipsMCRegisterClasses[CCRRegClassID],
4809    CCRSubClassMask,
4810    SuperRegIdxSeqs + 1,
4811    LaneBitmask(0x00000001),
4812    0,
4813    false, /* HasDisjunctSubRegs */
4814    false, /* CoveredBySubRegs */
4815    NullRegClasses,
4816    nullptr
4817  };
4818
4819  extern const TargetRegisterClass COP0RegClass = {
4820    &MipsMCRegisterClasses[COP0RegClassID],
4821    COP0SubClassMask,
4822    SuperRegIdxSeqs + 1,
4823    LaneBitmask(0x00000001),
4824    0,
4825    false, /* HasDisjunctSubRegs */
4826    false, /* CoveredBySubRegs */
4827    NullRegClasses,
4828    nullptr
4829  };
4830
4831  extern const TargetRegisterClass COP2RegClass = {
4832    &MipsMCRegisterClasses[COP2RegClassID],
4833    COP2SubClassMask,
4834    SuperRegIdxSeqs + 1,
4835    LaneBitmask(0x00000001),
4836    0,
4837    false, /* HasDisjunctSubRegs */
4838    false, /* CoveredBySubRegs */
4839    NullRegClasses,
4840    nullptr
4841  };
4842
4843  extern const TargetRegisterClass COP3RegClass = {
4844    &MipsMCRegisterClasses[COP3RegClassID],
4845    COP3SubClassMask,
4846    SuperRegIdxSeqs + 1,
4847    LaneBitmask(0x00000001),
4848    0,
4849    false, /* HasDisjunctSubRegs */
4850    false, /* CoveredBySubRegs */
4851    NullRegClasses,
4852    nullptr
4853  };
4854
4855  extern const TargetRegisterClass DSPRRegClass = {
4856    &MipsMCRegisterClasses[DSPRRegClassID],
4857    DSPRSubClassMask,
4858    SuperRegIdxSeqs + 0,
4859    LaneBitmask(0x00000001),
4860    0,
4861    false, /* HasDisjunctSubRegs */
4862    false, /* CoveredBySubRegs */
4863    NullRegClasses,
4864    nullptr
4865  };
4866
4867  extern const TargetRegisterClass FGR32RegClass = {
4868    &MipsMCRegisterClasses[FGR32RegClassID],
4869    FGR32SubClassMask,
4870    SuperRegIdxSeqs + 9,
4871    LaneBitmask(0x00000001),
4872    0,
4873    false, /* HasDisjunctSubRegs */
4874    false, /* CoveredBySubRegs */
4875    FGR32Superclasses,
4876    FGR32GetRawAllocationOrder
4877  };
4878
4879  extern const TargetRegisterClass FGRCCRegClass = {
4880    &MipsMCRegisterClasses[FGRCCRegClassID],
4881    FGRCCSubClassMask,
4882    SuperRegIdxSeqs + 9,
4883    LaneBitmask(0x00000001),
4884    0,
4885    false, /* HasDisjunctSubRegs */
4886    false, /* CoveredBySubRegs */
4887    FGRCCSuperclasses,
4888    nullptr
4889  };
4890
4891  extern const TargetRegisterClass GPR32RegClass = {
4892    &MipsMCRegisterClasses[GPR32RegClassID],
4893    GPR32SubClassMask,
4894    SuperRegIdxSeqs + 0,
4895    LaneBitmask(0x00000001),
4896    0,
4897    false, /* HasDisjunctSubRegs */
4898    false, /* CoveredBySubRegs */
4899    GPR32Superclasses,
4900    nullptr
4901  };
4902
4903  extern const TargetRegisterClass HWRegsRegClass = {
4904    &MipsMCRegisterClasses[HWRegsRegClassID],
4905    HWRegsSubClassMask,
4906    SuperRegIdxSeqs + 1,
4907    LaneBitmask(0x00000001),
4908    0,
4909    false, /* HasDisjunctSubRegs */
4910    false, /* CoveredBySubRegs */
4911    NullRegClasses,
4912    nullptr
4913  };
4914
4915  extern const TargetRegisterClass MSACtrlRegClass = {
4916    &MipsMCRegisterClasses[MSACtrlRegClassID],
4917    MSACtrlSubClassMask,
4918    SuperRegIdxSeqs + 1,
4919    LaneBitmask(0x00000001),
4920    0,
4921    false, /* HasDisjunctSubRegs */
4922    false, /* CoveredBySubRegs */
4923    NullRegClasses,
4924    nullptr
4925  };
4926
4927  extern const TargetRegisterClass GPR32NONZERORegClass = {
4928    &MipsMCRegisterClasses[GPR32NONZERORegClassID],
4929    GPR32NONZEROSubClassMask,
4930    SuperRegIdxSeqs + 0,
4931    LaneBitmask(0x00000001),
4932    0,
4933    false, /* HasDisjunctSubRegs */
4934    false, /* CoveredBySubRegs */
4935    GPR32NONZEROSuperclasses,
4936    nullptr
4937  };
4938
4939  extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {
4940    &MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],
4941    CPU16RegsPlusSPSubClassMask,
4942    SuperRegIdxSeqs + 0,
4943    LaneBitmask(0x00000001),
4944    0,
4945    false, /* HasDisjunctSubRegs */
4946    false, /* CoveredBySubRegs */
4947    CPU16RegsPlusSPSuperclasses,
4948    nullptr
4949  };
4950
4951  extern const TargetRegisterClass CPU16RegsRegClass = {
4952    &MipsMCRegisterClasses[CPU16RegsRegClassID],
4953    CPU16RegsSubClassMask,
4954    SuperRegIdxSeqs + 0,
4955    LaneBitmask(0x00000001),
4956    0,
4957    false, /* HasDisjunctSubRegs */
4958    false, /* CoveredBySubRegs */
4959    CPU16RegsSuperclasses,
4960    nullptr
4961  };
4962
4963  extern const TargetRegisterClass FCCRegClass = {
4964    &MipsMCRegisterClasses[FCCRegClassID],
4965    FCCSubClassMask,
4966    SuperRegIdxSeqs + 1,
4967    LaneBitmask(0x00000001),
4968    0,
4969    false, /* HasDisjunctSubRegs */
4970    false, /* CoveredBySubRegs */
4971    NullRegClasses,
4972    nullptr
4973  };
4974
4975  extern const TargetRegisterClass GPRMM16RegClass = {
4976    &MipsMCRegisterClasses[GPRMM16RegClassID],
4977    GPRMM16SubClassMask,
4978    SuperRegIdxSeqs + 0,
4979    LaneBitmask(0x00000001),
4980    0,
4981    false, /* HasDisjunctSubRegs */
4982    false, /* CoveredBySubRegs */
4983    GPRMM16Superclasses,
4984    nullptr
4985  };
4986
4987  extern const TargetRegisterClass GPRMM16MovePRegClass = {
4988    &MipsMCRegisterClasses[GPRMM16MovePRegClassID],
4989    GPRMM16MovePSubClassMask,
4990    SuperRegIdxSeqs + 0,
4991    LaneBitmask(0x00000001),
4992    0,
4993    false, /* HasDisjunctSubRegs */
4994    false, /* CoveredBySubRegs */
4995    GPRMM16MovePSuperclasses,
4996    nullptr
4997  };
4998
4999  extern const TargetRegisterClass GPRMM16ZeroRegClass = {
5000    &MipsMCRegisterClasses[GPRMM16ZeroRegClassID],
5001    GPRMM16ZeroSubClassMask,
5002    SuperRegIdxSeqs + 0,
5003    LaneBitmask(0x00000001),
5004    0,
5005    false, /* HasDisjunctSubRegs */
5006    false, /* CoveredBySubRegs */
5007    GPRMM16ZeroSuperclasses,
5008    nullptr
5009  };
5010
5011  extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {
5012    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],
5013    CPU16Regs_and_GPRMM16ZeroSubClassMask,
5014    SuperRegIdxSeqs + 0,
5015    LaneBitmask(0x00000001),
5016    0,
5017    false, /* HasDisjunctSubRegs */
5018    false, /* CoveredBySubRegs */
5019    CPU16Regs_and_GPRMM16ZeroSuperclasses,
5020    nullptr
5021  };
5022
5023  extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {
5024    &MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],
5025    GPR32NONZERO_and_GPRMM16MovePSubClassMask,
5026    SuperRegIdxSeqs + 0,
5027    LaneBitmask(0x00000001),
5028    0,
5029    false, /* HasDisjunctSubRegs */
5030    false, /* CoveredBySubRegs */
5031    GPR32NONZERO_and_GPRMM16MovePSuperclasses,
5032    nullptr
5033  };
5034
5035  extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {
5036    &MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],
5037    GPRMM16MovePPairSecondSubClassMask,
5038    SuperRegIdxSeqs + 0,
5039    LaneBitmask(0x00000001),
5040    0,
5041    false, /* HasDisjunctSubRegs */
5042    false, /* CoveredBySubRegs */
5043    GPRMM16MovePPairSecondSuperclasses,
5044    nullptr
5045  };
5046
5047  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {
5048    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],
5049    CPU16Regs_and_GPRMM16MovePSubClassMask,
5050    SuperRegIdxSeqs + 0,
5051    LaneBitmask(0x00000001),
5052    0,
5053    false, /* HasDisjunctSubRegs */
5054    false, /* CoveredBySubRegs */
5055    CPU16Regs_and_GPRMM16MovePSuperclasses,
5056    nullptr
5057  };
5058
5059  extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5060    &MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
5061    GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
5062    SuperRegIdxSeqs + 0,
5063    LaneBitmask(0x00000001),
5064    0,
5065    false, /* HasDisjunctSubRegs */
5066    false, /* CoveredBySubRegs */
5067    GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
5068    nullptr
5069  };
5070
5071  extern const TargetRegisterClass HI32DSPRegClass = {
5072    &MipsMCRegisterClasses[HI32DSPRegClassID],
5073    HI32DSPSubClassMask,
5074    SuperRegIdxSeqs + 12,
5075    LaneBitmask(0x00000001),
5076    0,
5077    false, /* HasDisjunctSubRegs */
5078    false, /* CoveredBySubRegs */
5079    NullRegClasses,
5080    nullptr
5081  };
5082
5083  extern const TargetRegisterClass LO32DSPRegClass = {
5084    &MipsMCRegisterClasses[LO32DSPRegClassID],
5085    LO32DSPSubClassMask,
5086    SuperRegIdxSeqs + 6,
5087    LaneBitmask(0x00000001),
5088    0,
5089    false, /* HasDisjunctSubRegs */
5090    false, /* CoveredBySubRegs */
5091    NullRegClasses,
5092    nullptr
5093  };
5094
5095  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
5096    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
5097    CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
5098    SuperRegIdxSeqs + 0,
5099    LaneBitmask(0x00000001),
5100    0,
5101    false, /* HasDisjunctSubRegs */
5102    false, /* CoveredBySubRegs */
5103    CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,
5104    nullptr
5105  };
5106
5107  extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {
5108    &MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],
5109    GPRMM16MovePPairFirstSubClassMask,
5110    SuperRegIdxSeqs + 0,
5111    LaneBitmask(0x00000001),
5112    0,
5113    false, /* HasDisjunctSubRegs */
5114    false, /* CoveredBySubRegs */
5115    GPRMM16MovePPairFirstSuperclasses,
5116    nullptr
5117  };
5118
5119  extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5120    &MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
5121    GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5122    SuperRegIdxSeqs + 0,
5123    LaneBitmask(0x00000001),
5124    0,
5125    false, /* HasDisjunctSubRegs */
5126    false, /* CoveredBySubRegs */
5127    GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5128    nullptr
5129  };
5130
5131  extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
5132    &MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
5133    GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
5134    SuperRegIdxSeqs + 0,
5135    LaneBitmask(0x00000001),
5136    0,
5137    false, /* HasDisjunctSubRegs */
5138    false, /* CoveredBySubRegs */
5139    GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,
5140    nullptr
5141  };
5142
5143  extern const TargetRegisterClass CPURARegRegClass = {
5144    &MipsMCRegisterClasses[CPURARegRegClassID],
5145    CPURARegSubClassMask,
5146    SuperRegIdxSeqs + 0,
5147    LaneBitmask(0x00000001),
5148    0,
5149    false, /* HasDisjunctSubRegs */
5150    false, /* CoveredBySubRegs */
5151    CPURARegSuperclasses,
5152    nullptr
5153  };
5154
5155  extern const TargetRegisterClass CPUSPRegRegClass = {
5156    &MipsMCRegisterClasses[CPUSPRegRegClassID],
5157    CPUSPRegSubClassMask,
5158    SuperRegIdxSeqs + 0,
5159    LaneBitmask(0x00000001),
5160    0,
5161    false, /* HasDisjunctSubRegs */
5162    false, /* CoveredBySubRegs */
5163    CPUSPRegSuperclasses,
5164    nullptr
5165  };
5166
5167  extern const TargetRegisterClass DSPCCRegClass = {
5168    &MipsMCRegisterClasses[DSPCCRegClassID],
5169    DSPCCSubClassMask,
5170    SuperRegIdxSeqs + 1,
5171    LaneBitmask(0x00000001),
5172    0,
5173    false, /* HasDisjunctSubRegs */
5174    false, /* CoveredBySubRegs */
5175    NullRegClasses,
5176    nullptr
5177  };
5178
5179  extern const TargetRegisterClass GP32RegClass = {
5180    &MipsMCRegisterClasses[GP32RegClassID],
5181    GP32SubClassMask,
5182    SuperRegIdxSeqs + 0,
5183    LaneBitmask(0x00000001),
5184    0,
5185    false, /* HasDisjunctSubRegs */
5186    false, /* CoveredBySubRegs */
5187    GP32Superclasses,
5188    nullptr
5189  };
5190
5191  extern const TargetRegisterClass GPR32ZERORegClass = {
5192    &MipsMCRegisterClasses[GPR32ZERORegClassID],
5193    GPR32ZEROSubClassMask,
5194    SuperRegIdxSeqs + 0,
5195    LaneBitmask(0x00000001),
5196    0,
5197    false, /* HasDisjunctSubRegs */
5198    false, /* CoveredBySubRegs */
5199    GPR32ZEROSuperclasses,
5200    nullptr
5201  };
5202
5203  extern const TargetRegisterClass HI32RegClass = {
5204    &MipsMCRegisterClasses[HI32RegClassID],
5205    HI32SubClassMask,
5206    SuperRegIdxSeqs + 12,
5207    LaneBitmask(0x00000001),
5208    0,
5209    false, /* HasDisjunctSubRegs */
5210    false, /* CoveredBySubRegs */
5211    HI32Superclasses,
5212    nullptr
5213  };
5214
5215  extern const TargetRegisterClass LO32RegClass = {
5216    &MipsMCRegisterClasses[LO32RegClassID],
5217    LO32SubClassMask,
5218    SuperRegIdxSeqs + 6,
5219    LaneBitmask(0x00000001),
5220    0,
5221    false, /* HasDisjunctSubRegs */
5222    false, /* CoveredBySubRegs */
5223    LO32Superclasses,
5224    nullptr
5225  };
5226
5227  extern const TargetRegisterClass SP32RegClass = {
5228    &MipsMCRegisterClasses[SP32RegClassID],
5229    SP32SubClassMask,
5230    SuperRegIdxSeqs + 0,
5231    LaneBitmask(0x00000001),
5232    0,
5233    false, /* HasDisjunctSubRegs */
5234    false, /* CoveredBySubRegs */
5235    SP32Superclasses,
5236    nullptr
5237  };
5238
5239  extern const TargetRegisterClass FGR64RegClass = {
5240    &MipsMCRegisterClasses[FGR64RegClassID],
5241    FGR64SubClassMask,
5242    SuperRegIdxSeqs + 2,
5243    LaneBitmask(0x00000041),
5244    0,
5245    true, /* HasDisjunctSubRegs */
5246    true, /* CoveredBySubRegs */
5247    NullRegClasses,
5248    FGR64GetRawAllocationOrder
5249  };
5250
5251  extern const TargetRegisterClass GPR64RegClass = {
5252    &MipsMCRegisterClasses[GPR64RegClassID],
5253    GPR64SubClassMask,
5254    SuperRegIdxSeqs + 1,
5255    LaneBitmask(0x00000001),
5256    0,
5257    false, /* HasDisjunctSubRegs */
5258    false, /* CoveredBySubRegs */
5259    NullRegClasses,
5260    nullptr
5261  };
5262
5263  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {
5264    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],
5265    GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,
5266    SuperRegIdxSeqs + 1,
5267    LaneBitmask(0x00000001),
5268    0,
5269    false, /* HasDisjunctSubRegs */
5270    false, /* CoveredBySubRegs */
5271    GPR64_with_sub_32_in_GPR32NONZEROSuperclasses,
5272    nullptr
5273  };
5274
5275  extern const TargetRegisterClass AFGR64RegClass = {
5276    &MipsMCRegisterClasses[AFGR64RegClassID],
5277    AFGR64SubClassMask,
5278    SuperRegIdxSeqs + 1,
5279    LaneBitmask(0x00000041),
5280    0,
5281    true, /* HasDisjunctSubRegs */
5282    true, /* CoveredBySubRegs */
5283    NullRegClasses,
5284    nullptr
5285  };
5286
5287  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {
5288    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],
5289    GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,
5290    SuperRegIdxSeqs + 1,
5291    LaneBitmask(0x00000001),
5292    0,
5293    false, /* HasDisjunctSubRegs */
5294    false, /* CoveredBySubRegs */
5295    GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses,
5296    nullptr
5297  };
5298
5299  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {
5300    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],
5301    GPR64_with_sub_32_in_CPU16RegsSubClassMask,
5302    SuperRegIdxSeqs + 1,
5303    LaneBitmask(0x00000001),
5304    0,
5305    false, /* HasDisjunctSubRegs */
5306    false, /* CoveredBySubRegs */
5307    GPR64_with_sub_32_in_CPU16RegsSuperclasses,
5308    nullptr
5309  };
5310
5311  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {
5312    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],
5313    GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,
5314    SuperRegIdxSeqs + 1,
5315    LaneBitmask(0x00000001),
5316    0,
5317    false, /* HasDisjunctSubRegs */
5318    false, /* CoveredBySubRegs */
5319    GPR64_with_sub_32_in_GPRMM16MovePSuperclasses,
5320    nullptr
5321  };
5322
5323  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {
5324    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],
5325    GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,
5326    SuperRegIdxSeqs + 1,
5327    LaneBitmask(0x00000001),
5328    0,
5329    false, /* HasDisjunctSubRegs */
5330    false, /* CoveredBySubRegs */
5331    GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses,
5332    nullptr
5333  };
5334
5335  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {
5336    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],
5337    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5338    SuperRegIdxSeqs + 1,
5339    LaneBitmask(0x00000001),
5340    0,
5341    false, /* HasDisjunctSubRegs */
5342    false, /* CoveredBySubRegs */
5343    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5344    nullptr
5345  };
5346
5347  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {
5348    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],
5349    GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,
5350    SuperRegIdxSeqs + 1,
5351    LaneBitmask(0x00000001),
5352    0,
5353    false, /* HasDisjunctSubRegs */
5354    false, /* CoveredBySubRegs */
5355    GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses,
5356    nullptr
5357  };
5358
5359  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {
5360    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID],
5361    GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask,
5362    SuperRegIdxSeqs + 1,
5363    LaneBitmask(0x00000001),
5364    0,
5365    false, /* HasDisjunctSubRegs */
5366    false, /* CoveredBySubRegs */
5367    GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses,
5368    nullptr
5369  };
5370
5371  extern const TargetRegisterClass ACC64DSPRegClass = {
5372    &MipsMCRegisterClasses[ACC64DSPRegClassID],
5373    ACC64DSPSubClassMask,
5374    SuperRegIdxSeqs + 16,
5375    LaneBitmask(0x00000041),
5376    0,
5377    true, /* HasDisjunctSubRegs */
5378    true, /* CoveredBySubRegs */
5379    NullRegClasses,
5380    nullptr
5381  };
5382
5383  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {
5384    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],
5385    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,
5386    SuperRegIdxSeqs + 1,
5387    LaneBitmask(0x00000001),
5388    0,
5389    false, /* HasDisjunctSubRegs */
5390    false, /* CoveredBySubRegs */
5391    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses,
5392    nullptr
5393  };
5394
5395  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5396    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
5397    GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
5398    SuperRegIdxSeqs + 1,
5399    LaneBitmask(0x00000001),
5400    0,
5401    false, /* HasDisjunctSubRegs */
5402    false, /* CoveredBySubRegs */
5403    GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
5404    nullptr
5405  };
5406
5407  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
5408    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
5409    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
5410    SuperRegIdxSeqs + 1,
5411    LaneBitmask(0x00000001),
5412    0,
5413    false, /* HasDisjunctSubRegs */
5414    false, /* CoveredBySubRegs */
5415    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,
5416    nullptr
5417  };
5418
5419  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {
5420    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID],
5421    GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask,
5422    SuperRegIdxSeqs + 1,
5423    LaneBitmask(0x00000001),
5424    0,
5425    false, /* HasDisjunctSubRegs */
5426    false, /* CoveredBySubRegs */
5427    GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses,
5428    nullptr
5429  };
5430
5431  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5432    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
5433    GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5434    SuperRegIdxSeqs + 1,
5435    LaneBitmask(0x00000001),
5436    0,
5437    false, /* HasDisjunctSubRegs */
5438    false, /* CoveredBySubRegs */
5439    GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5440    nullptr
5441  };
5442
5443  extern const TargetRegisterClass OCTEON_MPLRegClass = {
5444    &MipsMCRegisterClasses[OCTEON_MPLRegClassID],
5445    OCTEON_MPLSubClassMask,
5446    SuperRegIdxSeqs + 1,
5447    LaneBitmask(0x00000001),
5448    0,
5449    false, /* HasDisjunctSubRegs */
5450    false, /* CoveredBySubRegs */
5451    NullRegClasses,
5452    nullptr
5453  };
5454
5455  extern const TargetRegisterClass OCTEON_PRegClass = {
5456    &MipsMCRegisterClasses[OCTEON_PRegClassID],
5457    OCTEON_PSubClassMask,
5458    SuperRegIdxSeqs + 1,
5459    LaneBitmask(0x00000001),
5460    0,
5461    false, /* HasDisjunctSubRegs */
5462    false, /* CoveredBySubRegs */
5463    NullRegClasses,
5464    nullptr
5465  };
5466
5467  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
5468    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
5469    GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
5470    SuperRegIdxSeqs + 1,
5471    LaneBitmask(0x00000001),
5472    0,
5473    false, /* HasDisjunctSubRegs */
5474    false, /* CoveredBySubRegs */
5475    GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,
5476    nullptr
5477  };
5478
5479  extern const TargetRegisterClass ACC64RegClass = {
5480    &MipsMCRegisterClasses[ACC64RegClassID],
5481    ACC64SubClassMask,
5482    SuperRegIdxSeqs + 16,
5483    LaneBitmask(0x00000041),
5484    0,
5485    true, /* HasDisjunctSubRegs */
5486    true, /* CoveredBySubRegs */
5487    ACC64Superclasses,
5488    nullptr
5489  };
5490
5491  extern const TargetRegisterClass GP64RegClass = {
5492    &MipsMCRegisterClasses[GP64RegClassID],
5493    GP64SubClassMask,
5494    SuperRegIdxSeqs + 1,
5495    LaneBitmask(0x00000001),
5496    0,
5497    false, /* HasDisjunctSubRegs */
5498    false, /* CoveredBySubRegs */
5499    GP64Superclasses,
5500    nullptr
5501  };
5502
5503  extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {
5504    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],
5505    GPR64_with_sub_32_in_CPURARegSubClassMask,
5506    SuperRegIdxSeqs + 1,
5507    LaneBitmask(0x00000001),
5508    0,
5509    false, /* HasDisjunctSubRegs */
5510    false, /* CoveredBySubRegs */
5511    GPR64_with_sub_32_in_CPURARegSuperclasses,
5512    nullptr
5513  };
5514
5515  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {
5516    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],
5517    GPR64_with_sub_32_in_GPR32ZEROSubClassMask,
5518    SuperRegIdxSeqs + 1,
5519    LaneBitmask(0x00000001),
5520    0,
5521    false, /* HasDisjunctSubRegs */
5522    false, /* CoveredBySubRegs */
5523    GPR64_with_sub_32_in_GPR32ZEROSuperclasses,
5524    nullptr
5525  };
5526
5527  extern const TargetRegisterClass HI64RegClass = {
5528    &MipsMCRegisterClasses[HI64RegClassID],
5529    HI64SubClassMask,
5530    SuperRegIdxSeqs + 4,
5531    LaneBitmask(0x00000001),
5532    0,
5533    false, /* HasDisjunctSubRegs */
5534    false, /* CoveredBySubRegs */
5535    NullRegClasses,
5536    nullptr
5537  };
5538
5539  extern const TargetRegisterClass LO64RegClass = {
5540    &MipsMCRegisterClasses[LO64RegClassID],
5541    LO64SubClassMask,
5542    SuperRegIdxSeqs + 7,
5543    LaneBitmask(0x00000001),
5544    0,
5545    false, /* HasDisjunctSubRegs */
5546    false, /* CoveredBySubRegs */
5547    NullRegClasses,
5548    nullptr
5549  };
5550
5551  extern const TargetRegisterClass SP64RegClass = {
5552    &MipsMCRegisterClasses[SP64RegClassID],
5553    SP64SubClassMask,
5554    SuperRegIdxSeqs + 1,
5555    LaneBitmask(0x00000001),
5556    0,
5557    false, /* HasDisjunctSubRegs */
5558    false, /* CoveredBySubRegs */
5559    SP64Superclasses,
5560    nullptr
5561  };
5562
5563  extern const TargetRegisterClass MSA128BRegClass = {
5564    &MipsMCRegisterClasses[MSA128BRegClassID],
5565    MSA128BSubClassMask,
5566    SuperRegIdxSeqs + 1,
5567    LaneBitmask(0x00000041),
5568    0,
5569    true, /* HasDisjunctSubRegs */
5570    false, /* CoveredBySubRegs */
5571    MSA128BSuperclasses,
5572    nullptr
5573  };
5574
5575  extern const TargetRegisterClass MSA128DRegClass = {
5576    &MipsMCRegisterClasses[MSA128DRegClassID],
5577    MSA128DSubClassMask,
5578    SuperRegIdxSeqs + 1,
5579    LaneBitmask(0x00000041),
5580    0,
5581    true, /* HasDisjunctSubRegs */
5582    false, /* CoveredBySubRegs */
5583    MSA128DSuperclasses,
5584    nullptr
5585  };
5586
5587  extern const TargetRegisterClass MSA128HRegClass = {
5588    &MipsMCRegisterClasses[MSA128HRegClassID],
5589    MSA128HSubClassMask,
5590    SuperRegIdxSeqs + 1,
5591    LaneBitmask(0x00000041),
5592    0,
5593    true, /* HasDisjunctSubRegs */
5594    false, /* CoveredBySubRegs */
5595    MSA128HSuperclasses,
5596    nullptr
5597  };
5598
5599  extern const TargetRegisterClass MSA128WRegClass = {
5600    &MipsMCRegisterClasses[MSA128WRegClassID],
5601    MSA128WSubClassMask,
5602    SuperRegIdxSeqs + 1,
5603    LaneBitmask(0x00000041),
5604    0,
5605    true, /* HasDisjunctSubRegs */
5606    false, /* CoveredBySubRegs */
5607    MSA128WSuperclasses,
5608    nullptr
5609  };
5610
5611  extern const TargetRegisterClass MSA128WEvensRegClass = {
5612    &MipsMCRegisterClasses[MSA128WEvensRegClassID],
5613    MSA128WEvensSubClassMask,
5614    SuperRegIdxSeqs + 1,
5615    LaneBitmask(0x00000041),
5616    0,
5617    true, /* HasDisjunctSubRegs */
5618    false, /* CoveredBySubRegs */
5619    MSA128WEvensSuperclasses,
5620    nullptr
5621  };
5622
5623  extern const TargetRegisterClass ACC128RegClass = {
5624    &MipsMCRegisterClasses[ACC128RegClassID],
5625    ACC128SubClassMask,
5626    SuperRegIdxSeqs + 1,
5627    LaneBitmask(0x00000041),
5628    0,
5629    true, /* HasDisjunctSubRegs */
5630    true, /* CoveredBySubRegs */
5631    NullRegClasses,
5632    nullptr
5633  };
5634
5635} // end namespace Mips
5636
5637namespace {
5638  const TargetRegisterClass* const RegisterClasses[] = {
5639    &Mips::MSA128F16RegClass,
5640    &Mips::CCRRegClass,
5641    &Mips::COP0RegClass,
5642    &Mips::COP2RegClass,
5643    &Mips::COP3RegClass,
5644    &Mips::DSPRRegClass,
5645    &Mips::FGR32RegClass,
5646    &Mips::FGRCCRegClass,
5647    &Mips::GPR32RegClass,
5648    &Mips::HWRegsRegClass,
5649    &Mips::MSACtrlRegClass,
5650    &Mips::GPR32NONZERORegClass,
5651    &Mips::CPU16RegsPlusSPRegClass,
5652    &Mips::CPU16RegsRegClass,
5653    &Mips::FCCRegClass,
5654    &Mips::GPRMM16RegClass,
5655    &Mips::GPRMM16MovePRegClass,
5656    &Mips::GPRMM16ZeroRegClass,
5657    &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
5658    &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
5659    &Mips::GPRMM16MovePPairSecondRegClass,
5660    &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
5661    &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
5662    &Mips::HI32DSPRegClass,
5663    &Mips::LO32DSPRegClass,
5664    &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
5665    &Mips::GPRMM16MovePPairFirstRegClass,
5666    &Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
5667    &Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
5668    &Mips::CPURARegRegClass,
5669    &Mips::CPUSPRegRegClass,
5670    &Mips::DSPCCRegClass,
5671    &Mips::GP32RegClass,
5672    &Mips::GPR32ZERORegClass,
5673    &Mips::HI32RegClass,
5674    &Mips::LO32RegClass,
5675    &Mips::SP32RegClass,
5676    &Mips::FGR64RegClass,
5677    &Mips::GPR64RegClass,
5678    &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
5679    &Mips::AFGR64RegClass,
5680    &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
5681    &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
5682    &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
5683    &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
5684    &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
5685    &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
5686    &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
5687    &Mips::ACC64DSPRegClass,
5688    &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
5689    &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
5690    &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
5691    &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
5692    &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
5693    &Mips::OCTEON_MPLRegClass,
5694    &Mips::OCTEON_PRegClass,
5695    &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
5696    &Mips::ACC64RegClass,
5697    &Mips::GP64RegClass,
5698    &Mips::GPR64_with_sub_32_in_CPURARegRegClass,
5699    &Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,
5700    &Mips::HI64RegClass,
5701    &Mips::LO64RegClass,
5702    &Mips::SP64RegClass,
5703    &Mips::MSA128BRegClass,
5704    &Mips::MSA128DRegClass,
5705    &Mips::MSA128HRegClass,
5706    &Mips::MSA128WRegClass,
5707    &Mips::MSA128WEvensRegClass,
5708    &Mips::ACC128RegClass,
5709  };
5710} // end anonymous namespace
5711
5712static const TargetRegisterInfoDesc MipsRegInfoDesc[] = { // Extra Descriptors
5713  { 0, false },
5714  { 0, true },
5715  { 0, true },
5716  { 0, false },
5717  { 0, false },
5718  { 0, false },
5719  { 0, false },
5720  { 0, false },
5721  { 0, true },
5722  { 0, true },
5723  { 0, false },
5724  { 0, false },
5725  { 0, false },
5726  { 0, false },
5727  { 0, false },
5728  { 0, false },
5729  { 0, false },
5730  { 0, false },
5731  { 0, false },
5732  { 0, true },
5733  { 0, true },
5734  { 0, true },
5735  { 0, true },
5736  { 0, true },
5737  { 0, true },
5738  { 0, true },
5739  { 0, true },
5740  { 0, true },
5741  { 0, true },
5742  { 0, true },
5743  { 0, true },
5744  { 0, false },
5745  { 0, false },
5746  { 0, false },
5747  { 0, false },
5748  { 0, false },
5749  { 0, false },
5750  { 0, false },
5751  { 0, false },
5752  { 0, false },
5753  { 0, false },
5754  { 0, false },
5755  { 0, false },
5756  { 0, false },
5757  { 0, false },
5758  { 0, false },
5759  { 0, false },
5760  { 0, false },
5761  { 0, false },
5762  { 0, false },
5763  { 0, false },
5764  { 0, false },
5765  { 0, false },
5766  { 0, false },
5767  { 0, false },
5768  { 0, false },
5769  { 0, false },
5770  { 0, false },
5771  { 0, false },
5772  { 0, false },
5773  { 0, false },
5774  { 0, false },
5775  { 0, false },
5776  { 0, false },
5777  { 0, false },
5778  { 0, false },
5779  { 0, false },
5780  { 0, false },
5781  { 0, false },
5782  { 0, false },
5783  { 0, false },
5784  { 0, false },
5785  { 0, false },
5786  { 0, false },
5787  { 0, false },
5788  { 0, false },
5789  { 0, false },
5790  { 0, false },
5791  { 0, false },
5792  { 0, false },
5793  { 0, false },
5794  { 0, false },
5795  { 0, false },
5796  { 0, false },
5797  { 0, false },
5798  { 0, false },
5799  { 0, false },
5800  { 0, false },
5801  { 0, false },
5802  { 0, false },
5803  { 0, false },
5804  { 0, false },
5805  { 0, false },
5806  { 0, false },
5807  { 0, false },
5808  { 0, false },
5809  { 0, false },
5810  { 0, false },
5811  { 0, false },
5812  { 0, false },
5813  { 0, false },
5814  { 0, false },
5815  { 0, false },
5816  { 0, false },
5817  { 0, false },
5818  { 0, false },
5819  { 0, false },
5820  { 0, false },
5821  { 0, false },
5822  { 0, false },
5823  { 0, false },
5824  { 0, false },
5825  { 0, false },
5826  { 0, false },
5827  { 0, false },
5828  { 0, false },
5829  { 0, false },
5830  { 0, false },
5831  { 0, false },
5832  { 0, false },
5833  { 0, false },
5834  { 0, false },
5835  { 0, false },
5836  { 0, false },
5837  { 0, false },
5838  { 0, false },
5839  { 0, false },
5840  { 0, true },
5841  { 0, true },
5842  { 0, true },
5843  { 0, true },
5844  { 0, true },
5845  { 0, true },
5846  { 0, true },
5847  { 0, true },
5848  { 0, true },
5849  { 0, true },
5850  { 0, true },
5851  { 0, true },
5852  { 0, true },
5853  { 0, true },
5854  { 0, true },
5855  { 0, true },
5856  { 0, false },
5857  { 0, false },
5858  { 0, false },
5859  { 0, false },
5860  { 0, true },
5861  { 0, true },
5862  { 0, true },
5863  { 0, true },
5864  { 0, true },
5865  { 0, true },
5866  { 0, true },
5867  { 0, true },
5868  { 0, true },
5869  { 0, true },
5870  { 0, true },
5871  { 0, true },
5872  { 0, true },
5873  { 0, true },
5874  { 0, true },
5875  { 0, true },
5876  { 0, true },
5877  { 0, true },
5878  { 0, true },
5879  { 0, true },
5880  { 0, true },
5881  { 0, true },
5882  { 0, true },
5883  { 0, true },
5884  { 0, true },
5885  { 0, true },
5886  { 0, true },
5887  { 0, true },
5888  { 0, true },
5889  { 0, true },
5890  { 0, true },
5891  { 0, true },
5892  { 0, false },
5893  { 0, false },
5894  { 0, false },
5895  { 0, false },
5896  { 0, false },
5897  { 0, false },
5898  { 0, false },
5899  { 0, false },
5900  { 0, false },
5901  { 0, false },
5902  { 0, false },
5903  { 0, false },
5904  { 0, false },
5905  { 0, false },
5906  { 0, false },
5907  { 0, false },
5908  { 0, false },
5909  { 0, false },
5910  { 0, false },
5911  { 0, false },
5912  { 0, false },
5913  { 0, false },
5914  { 0, false },
5915  { 0, false },
5916  { 0, false },
5917  { 0, false },
5918  { 0, false },
5919  { 0, false },
5920  { 0, false },
5921  { 0, false },
5922  { 0, false },
5923  { 0, false },
5924  { 0, false },
5925  { 0, false },
5926  { 0, false },
5927  { 0, false },
5928  { 0, false },
5929  { 0, false },
5930  { 0, false },
5931  { 0, false },
5932  { 0, true },
5933  { 0, false },
5934  { 0, false },
5935  { 0, false },
5936  { 0, false },
5937  { 0, false },
5938  { 0, false },
5939  { 0, false },
5940  { 0, false },
5941  { 0, false },
5942  { 0, false },
5943  { 0, false },
5944  { 0, false },
5945  { 0, false },
5946  { 0, false },
5947  { 0, false },
5948  { 0, false },
5949  { 0, false },
5950  { 0, false },
5951  { 0, false },
5952  { 0, false },
5953  { 0, false },
5954  { 0, false },
5955  { 0, false },
5956  { 0, false },
5957  { 0, false },
5958  { 0, false },
5959  { 0, false },
5960  { 0, false },
5961  { 0, false },
5962  { 0, false },
5963  { 0, false },
5964  { 0, false },
5965  { 0, true },
5966  { 0, true },
5967  { 0, true },
5968  { 0, true },
5969  { 0, true },
5970  { 0, false },
5971  { 0, false },
5972  { 0, false },
5973  { 0, false },
5974  { 0, false },
5975  { 0, false },
5976  { 0, false },
5977  { 0, false },
5978  { 0, false },
5979  { 0, false },
5980  { 0, false },
5981  { 0, false },
5982  { 0, false },
5983  { 0, false },
5984  { 0, false },
5985  { 0, false },
5986  { 0, false },
5987  { 0, false },
5988  { 0, false },
5989  { 0, false },
5990  { 0, false },
5991  { 0, false },
5992  { 0, false },
5993  { 0, false },
5994  { 0, false },
5995  { 0, false },
5996  { 0, false },
5997  { 0, false },
5998  { 0, false },
5999  { 0, false },
6000  { 0, false },
6001  { 0, false },
6002  { 0, true },
6003  { 0, true },
6004  { 0, true },
6005  { 0, true },
6006  { 0, true },
6007  { 0, true },
6008  { 0, false },
6009  { 0, false },
6010  { 0, false },
6011  { 0, false },
6012  { 0, false },
6013  { 0, false },
6014  { 0, false },
6015  { 0, false },
6016  { 0, false },
6017  { 0, false },
6018  { 0, false },
6019  { 0, false },
6020  { 0, false },
6021  { 0, false },
6022  { 0, false },
6023  { 0, false },
6024  { 0, false },
6025  { 0, false },
6026  { 0, false },
6027  { 0, false },
6028  { 0, false },
6029  { 0, false },
6030  { 0, false },
6031  { 0, false },
6032  { 0, false },
6033  { 0, false },
6034  { 0, false },
6035  { 0, false },
6036  { 0, false },
6037  { 0, false },
6038  { 0, true },
6039  { 0, true },
6040  { 0, true },
6041  { 0, true },
6042  { 0, true },
6043  { 0, true },
6044  { 0, true },
6045  { 0, true },
6046  { 0, true },
6047  { 0, true },
6048  { 0, true },
6049  { 0, true },
6050  { 0, true },
6051  { 0, true },
6052  { 0, true },
6053  { 0, true },
6054  { 0, true },
6055  { 0, true },
6056  { 0, true },
6057  { 0, true },
6058  { 0, true },
6059  { 0, true },
6060  { 0, true },
6061  { 0, true },
6062  { 0, true },
6063  { 0, true },
6064  { 0, true },
6065  { 0, true },
6066  { 0, true },
6067  { 0, true },
6068  { 0, true },
6069  { 0, true },
6070  { 0, true },
6071  { 0, true },
6072  { 0, true },
6073  { 0, true },
6074  { 0, true },
6075  { 0, true },
6076  { 0, true },
6077  { 0, true },
6078  { 0, true },
6079  { 0, true },
6080  { 0, true },
6081  { 0, true },
6082  { 0, true },
6083  { 0, true },
6084  { 0, true },
6085  { 0, true },
6086  { 0, true },
6087  { 0, true },
6088  { 0, true },
6089  { 0, true },
6090  { 0, true },
6091  { 0, true },
6092  { 0, true },
6093  { 0, true },
6094  { 0, true },
6095  { 0, true },
6096  { 0, true },
6097  { 0, true },
6098  { 0, true },
6099  { 0, true },
6100  { 0, true },
6101  { 0, true },
6102  { 0, true },
6103  { 0, true },
6104  { 0, true },
6105  { 0, true },
6106  { 0, true },
6107  { 0, true },
6108  { 0, true },
6109  { 0, true },
6110  { 0, true },
6111  { 0, true },
6112  { 0, true },
6113  { 0, true },
6114  { 0, true },
6115  { 0, true },
6116  { 0, true },
6117  { 0, true },
6118  { 0, true },
6119  { 0, true },
6120  { 0, true },
6121  { 0, true },
6122  { 0, true },
6123  { 0, true },
6124  { 0, true },
6125  { 0, true },
6126  { 0, true },
6127  { 0, true },
6128  { 0, true },
6129  { 0, true },
6130  { 0, false },
6131  { 0, true },
6132  { 0, true },
6133  { 0, true },
6134  { 0, true },
6135  { 0, true },
6136  { 0, true },
6137  { 0, true },
6138  { 0, true },
6139  { 0, true },
6140  { 0, true },
6141  { 0, true },
6142  { 0, true },
6143  { 0, true },
6144  { 0, true },
6145  { 0, true },
6146  { 0, true },
6147  { 0, true },
6148  { 0, true },
6149  { 0, true },
6150  { 0, true },
6151  { 0, true },
6152  { 0, true },
6153  { 0, true },
6154  { 0, true },
6155};
6156unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
6157  static const uint8_t RowMap[11] = {
6158    0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
6159  };
6160  static const uint8_t Rows[2][11] = {
6161    { Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },
6162    { Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, },
6163  };
6164
6165  --IdxA; assert(IdxA < 11);
6166  --IdxB; assert(IdxB < 11);
6167  return Rows[RowMap[IdxA]][IdxB];
6168}
6169
6170  struct MaskRolOp {
6171    LaneBitmask Mask;
6172    uint8_t  RotateLeft;
6173  };
6174  static const MaskRolOp LaneMaskComposeSequences[] = {
6175    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
6176    { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
6177    { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
6178    { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
6179    { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
6180    { LaneBitmask(0xFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
6181    { LaneBitmask(0xFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 }  // Sequence 12
6182  };
6183  static const MaskRolOp *const CompositeSequences[] = {
6184    &LaneMaskComposeSequences[0], // to sub_32
6185    &LaneMaskComposeSequences[0], // to sub_64
6186    &LaneMaskComposeSequences[2], // to sub_dsp16_19
6187    &LaneMaskComposeSequences[4], // to sub_dsp20
6188    &LaneMaskComposeSequences[6], // to sub_dsp21
6189    &LaneMaskComposeSequences[8], // to sub_dsp22
6190    &LaneMaskComposeSequences[10], // to sub_dsp23
6191    &LaneMaskComposeSequences[12], // to sub_hi
6192    &LaneMaskComposeSequences[0], // to sub_lo
6193    &LaneMaskComposeSequences[12], // to sub_hi_then_sub_32
6194    &LaneMaskComposeSequences[0] // to sub_32_sub_hi_then_sub_32
6195  };
6196
6197LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
6198  --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
6199  LaneBitmask Result;
6200  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
6201    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
6202    if (unsigned S = Ops->RotateLeft)
6203      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
6204    else
6205      Result |= LaneBitmask(M);
6206  }
6207  return Result;
6208}
6209
6210LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
6211  LaneMask &= getSubRegIndexLaneMask(IdxA);
6212  --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
6213  LaneBitmask Result;
6214  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
6215    LaneBitmask::Type M = LaneMask.getAsInteger();
6216    if (unsigned S = Ops->RotateLeft)
6217      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
6218    else
6219      Result |= LaneBitmask(M);
6220  }
6221  return Result;
6222}
6223
6224const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
6225  static const uint8_t Table[70][11] = {
6226    {	// MSA128F16
6227      0,	// sub_32
6228      1,	// sub_64 -> MSA128F16
6229      0,	// sub_dsp16_19
6230      0,	// sub_dsp20
6231      0,	// sub_dsp21
6232      0,	// sub_dsp22
6233      0,	// sub_dsp23
6234      1,	// sub_hi -> MSA128F16
6235      1,	// sub_lo -> MSA128F16
6236      0,	// sub_hi_then_sub_32
6237      0,	// sub_32_sub_hi_then_sub_32
6238    },
6239    {	// CCR
6240      0,	// sub_32
6241      0,	// sub_64
6242      0,	// sub_dsp16_19
6243      0,	// sub_dsp20
6244      0,	// sub_dsp21
6245      0,	// sub_dsp22
6246      0,	// sub_dsp23
6247      0,	// sub_hi
6248      0,	// sub_lo
6249      0,	// sub_hi_then_sub_32
6250      0,	// sub_32_sub_hi_then_sub_32
6251    },
6252    {	// COP0
6253      0,	// sub_32
6254      0,	// sub_64
6255      0,	// sub_dsp16_19
6256      0,	// sub_dsp20
6257      0,	// sub_dsp21
6258      0,	// sub_dsp22
6259      0,	// sub_dsp23
6260      0,	// sub_hi
6261      0,	// sub_lo
6262      0,	// sub_hi_then_sub_32
6263      0,	// sub_32_sub_hi_then_sub_32
6264    },
6265    {	// COP2
6266      0,	// sub_32
6267      0,	// sub_64
6268      0,	// sub_dsp16_19
6269      0,	// sub_dsp20
6270      0,	// sub_dsp21
6271      0,	// sub_dsp22
6272      0,	// sub_dsp23
6273      0,	// sub_hi
6274      0,	// sub_lo
6275      0,	// sub_hi_then_sub_32
6276      0,	// sub_32_sub_hi_then_sub_32
6277    },
6278    {	// COP3
6279      0,	// sub_32
6280      0,	// sub_64
6281      0,	// sub_dsp16_19
6282      0,	// sub_dsp20
6283      0,	// sub_dsp21
6284      0,	// sub_dsp22
6285      0,	// sub_dsp23
6286      0,	// sub_hi
6287      0,	// sub_lo
6288      0,	// sub_hi_then_sub_32
6289      0,	// sub_32_sub_hi_then_sub_32
6290    },
6291    {	// DSPR
6292      0,	// sub_32
6293      0,	// sub_64
6294      0,	// sub_dsp16_19
6295      0,	// sub_dsp20
6296      0,	// sub_dsp21
6297      0,	// sub_dsp22
6298      0,	// sub_dsp23
6299      0,	// sub_hi
6300      0,	// sub_lo
6301      0,	// sub_hi_then_sub_32
6302      0,	// sub_32_sub_hi_then_sub_32
6303    },
6304    {	// FGR32
6305      0,	// sub_32
6306      0,	// sub_64
6307      0,	// sub_dsp16_19
6308      0,	// sub_dsp20
6309      0,	// sub_dsp21
6310      0,	// sub_dsp22
6311      0,	// sub_dsp23
6312      0,	// sub_hi
6313      0,	// sub_lo
6314      0,	// sub_hi_then_sub_32
6315      0,	// sub_32_sub_hi_then_sub_32
6316    },
6317    {	// FGRCC
6318      0,	// sub_32
6319      0,	// sub_64
6320      0,	// sub_dsp16_19
6321      0,	// sub_dsp20
6322      0,	// sub_dsp21
6323      0,	// sub_dsp22
6324      0,	// sub_dsp23
6325      0,	// sub_hi
6326      0,	// sub_lo
6327      0,	// sub_hi_then_sub_32
6328      0,	// sub_32_sub_hi_then_sub_32
6329    },
6330    {	// GPR32
6331      0,	// sub_32
6332      0,	// sub_64
6333      0,	// sub_dsp16_19
6334      0,	// sub_dsp20
6335      0,	// sub_dsp21
6336      0,	// sub_dsp22
6337      0,	// sub_dsp23
6338      0,	// sub_hi
6339      0,	// sub_lo
6340      0,	// sub_hi_then_sub_32
6341      0,	// sub_32_sub_hi_then_sub_32
6342    },
6343    {	// HWRegs
6344      0,	// sub_32
6345      0,	// sub_64
6346      0,	// sub_dsp16_19
6347      0,	// sub_dsp20
6348      0,	// sub_dsp21
6349      0,	// sub_dsp22
6350      0,	// sub_dsp23
6351      0,	// sub_hi
6352      0,	// sub_lo
6353      0,	// sub_hi_then_sub_32
6354      0,	// sub_32_sub_hi_then_sub_32
6355    },
6356    {	// MSACtrl
6357      0,	// sub_32
6358      0,	// sub_64
6359      0,	// sub_dsp16_19
6360      0,	// sub_dsp20
6361      0,	// sub_dsp21
6362      0,	// sub_dsp22
6363      0,	// sub_dsp23
6364      0,	// sub_hi
6365      0,	// sub_lo
6366      0,	// sub_hi_then_sub_32
6367      0,	// sub_32_sub_hi_then_sub_32
6368    },
6369    {	// GPR32NONZERO
6370      0,	// sub_32
6371      0,	// sub_64
6372      0,	// sub_dsp16_19
6373      0,	// sub_dsp20
6374      0,	// sub_dsp21
6375      0,	// sub_dsp22
6376      0,	// sub_dsp23
6377      0,	// sub_hi
6378      0,	// sub_lo
6379      0,	// sub_hi_then_sub_32
6380      0,	// sub_32_sub_hi_then_sub_32
6381    },
6382    {	// CPU16RegsPlusSP
6383      0,	// sub_32
6384      0,	// sub_64
6385      0,	// sub_dsp16_19
6386      0,	// sub_dsp20
6387      0,	// sub_dsp21
6388      0,	// sub_dsp22
6389      0,	// sub_dsp23
6390      0,	// sub_hi
6391      0,	// sub_lo
6392      0,	// sub_hi_then_sub_32
6393      0,	// sub_32_sub_hi_then_sub_32
6394    },
6395    {	// CPU16Regs
6396      0,	// sub_32
6397      0,	// sub_64
6398      0,	// sub_dsp16_19
6399      0,	// sub_dsp20
6400      0,	// sub_dsp21
6401      0,	// sub_dsp22
6402      0,	// sub_dsp23
6403      0,	// sub_hi
6404      0,	// sub_lo
6405      0,	// sub_hi_then_sub_32
6406      0,	// sub_32_sub_hi_then_sub_32
6407    },
6408    {	// FCC
6409      0,	// sub_32
6410      0,	// sub_64
6411      0,	// sub_dsp16_19
6412      0,	// sub_dsp20
6413      0,	// sub_dsp21
6414      0,	// sub_dsp22
6415      0,	// sub_dsp23
6416      0,	// sub_hi
6417      0,	// sub_lo
6418      0,	// sub_hi_then_sub_32
6419      0,	// sub_32_sub_hi_then_sub_32
6420    },
6421    {	// GPRMM16
6422      0,	// sub_32
6423      0,	// sub_64
6424      0,	// sub_dsp16_19
6425      0,	// sub_dsp20
6426      0,	// sub_dsp21
6427      0,	// sub_dsp22
6428      0,	// sub_dsp23
6429      0,	// sub_hi
6430      0,	// sub_lo
6431      0,	// sub_hi_then_sub_32
6432      0,	// sub_32_sub_hi_then_sub_32
6433    },
6434    {	// GPRMM16MoveP
6435      0,	// sub_32
6436      0,	// sub_64
6437      0,	// sub_dsp16_19
6438      0,	// sub_dsp20
6439      0,	// sub_dsp21
6440      0,	// sub_dsp22
6441      0,	// sub_dsp23
6442      0,	// sub_hi
6443      0,	// sub_lo
6444      0,	// sub_hi_then_sub_32
6445      0,	// sub_32_sub_hi_then_sub_32
6446    },
6447    {	// GPRMM16Zero
6448      0,	// sub_32
6449      0,	// sub_64
6450      0,	// sub_dsp16_19
6451      0,	// sub_dsp20
6452      0,	// sub_dsp21
6453      0,	// sub_dsp22
6454      0,	// sub_dsp23
6455      0,	// sub_hi
6456      0,	// sub_lo
6457      0,	// sub_hi_then_sub_32
6458      0,	// sub_32_sub_hi_then_sub_32
6459    },
6460    {	// CPU16Regs_and_GPRMM16Zero
6461      0,	// sub_32
6462      0,	// sub_64
6463      0,	// sub_dsp16_19
6464      0,	// sub_dsp20
6465      0,	// sub_dsp21
6466      0,	// sub_dsp22
6467      0,	// sub_dsp23
6468      0,	// sub_hi
6469      0,	// sub_lo
6470      0,	// sub_hi_then_sub_32
6471      0,	// sub_32_sub_hi_then_sub_32
6472    },
6473    {	// GPR32NONZERO_and_GPRMM16MoveP
6474      0,	// sub_32
6475      0,	// sub_64
6476      0,	// sub_dsp16_19
6477      0,	// sub_dsp20
6478      0,	// sub_dsp21
6479      0,	// sub_dsp22
6480      0,	// sub_dsp23
6481      0,	// sub_hi
6482      0,	// sub_lo
6483      0,	// sub_hi_then_sub_32
6484      0,	// sub_32_sub_hi_then_sub_32
6485    },
6486    {	// GPRMM16MovePPairSecond
6487      0,	// sub_32
6488      0,	// sub_64
6489      0,	// sub_dsp16_19
6490      0,	// sub_dsp20
6491      0,	// sub_dsp21
6492      0,	// sub_dsp22
6493      0,	// sub_dsp23
6494      0,	// sub_hi
6495      0,	// sub_lo
6496      0,	// sub_hi_then_sub_32
6497      0,	// sub_32_sub_hi_then_sub_32
6498    },
6499    {	// CPU16Regs_and_GPRMM16MoveP
6500      0,	// sub_32
6501      0,	// sub_64
6502      0,	// sub_dsp16_19
6503      0,	// sub_dsp20
6504      0,	// sub_dsp21
6505      0,	// sub_dsp22
6506      0,	// sub_dsp23
6507      0,	// sub_hi
6508      0,	// sub_lo
6509      0,	// sub_hi_then_sub_32
6510      0,	// sub_32_sub_hi_then_sub_32
6511    },
6512    {	// GPRMM16MoveP_and_GPRMM16Zero
6513      0,	// sub_32
6514      0,	// sub_64
6515      0,	// sub_dsp16_19
6516      0,	// sub_dsp20
6517      0,	// sub_dsp21
6518      0,	// sub_dsp22
6519      0,	// sub_dsp23
6520      0,	// sub_hi
6521      0,	// sub_lo
6522      0,	// sub_hi_then_sub_32
6523      0,	// sub_32_sub_hi_then_sub_32
6524    },
6525    {	// HI32DSP
6526      0,	// sub_32
6527      0,	// sub_64
6528      0,	// sub_dsp16_19
6529      0,	// sub_dsp20
6530      0,	// sub_dsp21
6531      0,	// sub_dsp22
6532      0,	// sub_dsp23
6533      0,	// sub_hi
6534      0,	// sub_lo
6535      0,	// sub_hi_then_sub_32
6536      0,	// sub_32_sub_hi_then_sub_32
6537    },
6538    {	// LO32DSP
6539      0,	// sub_32
6540      0,	// sub_64
6541      0,	// sub_dsp16_19
6542      0,	// sub_dsp20
6543      0,	// sub_dsp21
6544      0,	// sub_dsp22
6545      0,	// sub_dsp23
6546      0,	// sub_hi
6547      0,	// sub_lo
6548      0,	// sub_hi_then_sub_32
6549      0,	// sub_32_sub_hi_then_sub_32
6550    },
6551    {	// CPU16Regs_and_GPRMM16MovePPairSecond
6552      0,	// sub_32
6553      0,	// sub_64
6554      0,	// sub_dsp16_19
6555      0,	// sub_dsp20
6556      0,	// sub_dsp21
6557      0,	// sub_dsp22
6558      0,	// sub_dsp23
6559      0,	// sub_hi
6560      0,	// sub_lo
6561      0,	// sub_hi_then_sub_32
6562      0,	// sub_32_sub_hi_then_sub_32
6563    },
6564    {	// GPRMM16MovePPairFirst
6565      0,	// sub_32
6566      0,	// sub_64
6567      0,	// sub_dsp16_19
6568      0,	// sub_dsp20
6569      0,	// sub_dsp21
6570      0,	// sub_dsp22
6571      0,	// sub_dsp23
6572      0,	// sub_hi
6573      0,	// sub_lo
6574      0,	// sub_hi_then_sub_32
6575      0,	// sub_32_sub_hi_then_sub_32
6576    },
6577    {	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6578      0,	// sub_32
6579      0,	// sub_64
6580      0,	// sub_dsp16_19
6581      0,	// sub_dsp20
6582      0,	// sub_dsp21
6583      0,	// sub_dsp22
6584      0,	// sub_dsp23
6585      0,	// sub_hi
6586      0,	// sub_lo
6587      0,	// sub_hi_then_sub_32
6588      0,	// sub_32_sub_hi_then_sub_32
6589    },
6590    {	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6591      0,	// sub_32
6592      0,	// sub_64
6593      0,	// sub_dsp16_19
6594      0,	// sub_dsp20
6595      0,	// sub_dsp21
6596      0,	// sub_dsp22
6597      0,	// sub_dsp23
6598      0,	// sub_hi
6599      0,	// sub_lo
6600      0,	// sub_hi_then_sub_32
6601      0,	// sub_32_sub_hi_then_sub_32
6602    },
6603    {	// CPURAReg
6604      0,	// sub_32
6605      0,	// sub_64
6606      0,	// sub_dsp16_19
6607      0,	// sub_dsp20
6608      0,	// sub_dsp21
6609      0,	// sub_dsp22
6610      0,	// sub_dsp23
6611      0,	// sub_hi
6612      0,	// sub_lo
6613      0,	// sub_hi_then_sub_32
6614      0,	// sub_32_sub_hi_then_sub_32
6615    },
6616    {	// CPUSPReg
6617      0,	// sub_32
6618      0,	// sub_64
6619      0,	// sub_dsp16_19
6620      0,	// sub_dsp20
6621      0,	// sub_dsp21
6622      0,	// sub_dsp22
6623      0,	// sub_dsp23
6624      0,	// sub_hi
6625      0,	// sub_lo
6626      0,	// sub_hi_then_sub_32
6627      0,	// sub_32_sub_hi_then_sub_32
6628    },
6629    {	// DSPCC
6630      0,	// sub_32
6631      0,	// sub_64
6632      0,	// sub_dsp16_19
6633      0,	// sub_dsp20
6634      0,	// sub_dsp21
6635      0,	// sub_dsp22
6636      0,	// sub_dsp23
6637      0,	// sub_hi
6638      0,	// sub_lo
6639      0,	// sub_hi_then_sub_32
6640      0,	// sub_32_sub_hi_then_sub_32
6641    },
6642    {	// GP32
6643      0,	// sub_32
6644      0,	// sub_64
6645      0,	// sub_dsp16_19
6646      0,	// sub_dsp20
6647      0,	// sub_dsp21
6648      0,	// sub_dsp22
6649      0,	// sub_dsp23
6650      0,	// sub_hi
6651      0,	// sub_lo
6652      0,	// sub_hi_then_sub_32
6653      0,	// sub_32_sub_hi_then_sub_32
6654    },
6655    {	// GPR32ZERO
6656      0,	// sub_32
6657      0,	// sub_64
6658      0,	// sub_dsp16_19
6659      0,	// sub_dsp20
6660      0,	// sub_dsp21
6661      0,	// sub_dsp22
6662      0,	// sub_dsp23
6663      0,	// sub_hi
6664      0,	// sub_lo
6665      0,	// sub_hi_then_sub_32
6666      0,	// sub_32_sub_hi_then_sub_32
6667    },
6668    {	// HI32
6669      0,	// sub_32
6670      0,	// sub_64
6671      0,	// sub_dsp16_19
6672      0,	// sub_dsp20
6673      0,	// sub_dsp21
6674      0,	// sub_dsp22
6675      0,	// sub_dsp23
6676      0,	// sub_hi
6677      0,	// sub_lo
6678      0,	// sub_hi_then_sub_32
6679      0,	// sub_32_sub_hi_then_sub_32
6680    },
6681    {	// LO32
6682      0,	// sub_32
6683      0,	// sub_64
6684      0,	// sub_dsp16_19
6685      0,	// sub_dsp20
6686      0,	// sub_dsp21
6687      0,	// sub_dsp22
6688      0,	// sub_dsp23
6689      0,	// sub_hi
6690      0,	// sub_lo
6691      0,	// sub_hi_then_sub_32
6692      0,	// sub_32_sub_hi_then_sub_32
6693    },
6694    {	// SP32
6695      0,	// sub_32
6696      0,	// sub_64
6697      0,	// sub_dsp16_19
6698      0,	// sub_dsp20
6699      0,	// sub_dsp21
6700      0,	// sub_dsp22
6701      0,	// sub_dsp23
6702      0,	// sub_hi
6703      0,	// sub_lo
6704      0,	// sub_hi_then_sub_32
6705      0,	// sub_32_sub_hi_then_sub_32
6706    },
6707    {	// FGR64
6708      0,	// sub_32
6709      0,	// sub_64
6710      0,	// sub_dsp16_19
6711      0,	// sub_dsp20
6712      0,	// sub_dsp21
6713      0,	// sub_dsp22
6714      0,	// sub_dsp23
6715      38,	// sub_hi -> FGR64
6716      38,	// sub_lo -> FGR64
6717      0,	// sub_hi_then_sub_32
6718      0,	// sub_32_sub_hi_then_sub_32
6719    },
6720    {	// GPR64
6721      39,	// sub_32 -> GPR64
6722      0,	// sub_64
6723      0,	// sub_dsp16_19
6724      0,	// sub_dsp20
6725      0,	// sub_dsp21
6726      0,	// sub_dsp22
6727      0,	// sub_dsp23
6728      0,	// sub_hi
6729      0,	// sub_lo
6730      0,	// sub_hi_then_sub_32
6731      0,	// sub_32_sub_hi_then_sub_32
6732    },
6733    {	// GPR64_with_sub_32_in_GPR32NONZERO
6734      40,	// sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO
6735      0,	// sub_64
6736      0,	// sub_dsp16_19
6737      0,	// sub_dsp20
6738      0,	// sub_dsp21
6739      0,	// sub_dsp22
6740      0,	// sub_dsp23
6741      0,	// sub_hi
6742      0,	// sub_lo
6743      0,	// sub_hi_then_sub_32
6744      0,	// sub_32_sub_hi_then_sub_32
6745    },
6746    {	// AFGR64
6747      0,	// sub_32
6748      0,	// sub_64
6749      0,	// sub_dsp16_19
6750      0,	// sub_dsp20
6751      0,	// sub_dsp21
6752      0,	// sub_dsp22
6753      0,	// sub_dsp23
6754      41,	// sub_hi -> AFGR64
6755      41,	// sub_lo -> AFGR64
6756      0,	// sub_hi_then_sub_32
6757      0,	// sub_32_sub_hi_then_sub_32
6758    },
6759    {	// GPR64_with_sub_32_in_CPU16RegsPlusSP
6760      42,	// sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP
6761      0,	// sub_64
6762      0,	// sub_dsp16_19
6763      0,	// sub_dsp20
6764      0,	// sub_dsp21
6765      0,	// sub_dsp22
6766      0,	// sub_dsp23
6767      0,	// sub_hi
6768      0,	// sub_lo
6769      0,	// sub_hi_then_sub_32
6770      0,	// sub_32_sub_hi_then_sub_32
6771    },
6772    {	// GPR64_with_sub_32_in_CPU16Regs
6773      43,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs
6774      0,	// sub_64
6775      0,	// sub_dsp16_19
6776      0,	// sub_dsp20
6777      0,	// sub_dsp21
6778      0,	// sub_dsp22
6779      0,	// sub_dsp23
6780      0,	// sub_hi
6781      0,	// sub_lo
6782      0,	// sub_hi_then_sub_32
6783      0,	// sub_32_sub_hi_then_sub_32
6784    },
6785    {	// GPR64_with_sub_32_in_GPRMM16MoveP
6786      44,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP
6787      0,	// sub_64
6788      0,	// sub_dsp16_19
6789      0,	// sub_dsp20
6790      0,	// sub_dsp21
6791      0,	// sub_dsp22
6792      0,	// sub_dsp23
6793      0,	// sub_hi
6794      0,	// sub_lo
6795      0,	// sub_hi_then_sub_32
6796      0,	// sub_32_sub_hi_then_sub_32
6797    },
6798    {	// GPR64_with_sub_32_in_GPRMM16Zero
6799      45,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero
6800      0,	// sub_64
6801      0,	// sub_dsp16_19
6802      0,	// sub_dsp20
6803      0,	// sub_dsp21
6804      0,	// sub_dsp22
6805      0,	// sub_dsp23
6806      0,	// sub_hi
6807      0,	// sub_lo
6808      0,	// sub_hi_then_sub_32
6809      0,	// sub_32_sub_hi_then_sub_32
6810    },
6811    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
6812      46,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
6813      0,	// sub_64
6814      0,	// sub_dsp16_19
6815      0,	// sub_dsp20
6816      0,	// sub_dsp21
6817      0,	// sub_dsp22
6818      0,	// sub_dsp23
6819      0,	// sub_hi
6820      0,	// sub_lo
6821      0,	// sub_hi_then_sub_32
6822      0,	// sub_32_sub_hi_then_sub_32
6823    },
6824    {	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
6825      47,	// sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
6826      0,	// sub_64
6827      0,	// sub_dsp16_19
6828      0,	// sub_dsp20
6829      0,	// sub_dsp21
6830      0,	// sub_dsp22
6831      0,	// sub_dsp23
6832      0,	// sub_hi
6833      0,	// sub_lo
6834      0,	// sub_hi_then_sub_32
6835      0,	// sub_32_sub_hi_then_sub_32
6836    },
6837    {	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond
6838      48,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond
6839      0,	// sub_64
6840      0,	// sub_dsp16_19
6841      0,	// sub_dsp20
6842      0,	// sub_dsp21
6843      0,	// sub_dsp22
6844      0,	// sub_dsp23
6845      0,	// sub_hi
6846      0,	// sub_lo
6847      0,	// sub_hi_then_sub_32
6848      0,	// sub_32_sub_hi_then_sub_32
6849    },
6850    {	// ACC64DSP
6851      0,	// sub_32
6852      0,	// sub_64
6853      0,	// sub_dsp16_19
6854      0,	// sub_dsp20
6855      0,	// sub_dsp21
6856      0,	// sub_dsp22
6857      0,	// sub_dsp23
6858      49,	// sub_hi -> ACC64DSP
6859      49,	// sub_lo -> ACC64DSP
6860      0,	// sub_hi_then_sub_32
6861      0,	// sub_32_sub_hi_then_sub_32
6862    },
6863    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
6864      50,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
6865      0,	// sub_64
6866      0,	// sub_dsp16_19
6867      0,	// sub_dsp20
6868      0,	// sub_dsp21
6869      0,	// sub_dsp22
6870      0,	// sub_dsp23
6871      0,	// sub_hi
6872      0,	// sub_lo
6873      0,	// sub_hi_then_sub_32
6874      0,	// sub_32_sub_hi_then_sub_32
6875    },
6876    {	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
6877      51,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
6878      0,	// sub_64
6879      0,	// sub_dsp16_19
6880      0,	// sub_dsp20
6881      0,	// sub_dsp21
6882      0,	// sub_dsp22
6883      0,	// sub_dsp23
6884      0,	// sub_hi
6885      0,	// sub_lo
6886      0,	// sub_hi_then_sub_32
6887      0,	// sub_32_sub_hi_then_sub_32
6888    },
6889    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
6890      52,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
6891      0,	// sub_64
6892      0,	// sub_dsp16_19
6893      0,	// sub_dsp20
6894      0,	// sub_dsp21
6895      0,	// sub_dsp22
6896      0,	// sub_dsp23
6897      0,	// sub_hi
6898      0,	// sub_lo
6899      0,	// sub_hi_then_sub_32
6900      0,	// sub_32_sub_hi_then_sub_32
6901    },
6902    {	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst
6903      53,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst
6904      0,	// sub_64
6905      0,	// sub_dsp16_19
6906      0,	// sub_dsp20
6907      0,	// sub_dsp21
6908      0,	// sub_dsp22
6909      0,	// sub_dsp23
6910      0,	// sub_hi
6911      0,	// sub_lo
6912      0,	// sub_hi_then_sub_32
6913      0,	// sub_32_sub_hi_then_sub_32
6914    },
6915    {	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6916      54,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6917      0,	// sub_64
6918      0,	// sub_dsp16_19
6919      0,	// sub_dsp20
6920      0,	// sub_dsp21
6921      0,	// sub_dsp22
6922      0,	// sub_dsp23
6923      0,	// sub_hi
6924      0,	// sub_lo
6925      0,	// sub_hi_then_sub_32
6926      0,	// sub_32_sub_hi_then_sub_32
6927    },
6928    {	// OCTEON_MPL
6929      0,	// sub_32
6930      0,	// sub_64
6931      0,	// sub_dsp16_19
6932      0,	// sub_dsp20
6933      0,	// sub_dsp21
6934      0,	// sub_dsp22
6935      0,	// sub_dsp23
6936      0,	// sub_hi
6937      0,	// sub_lo
6938      0,	// sub_hi_then_sub_32
6939      0,	// sub_32_sub_hi_then_sub_32
6940    },
6941    {	// OCTEON_P
6942      0,	// sub_32
6943      0,	// sub_64
6944      0,	// sub_dsp16_19
6945      0,	// sub_dsp20
6946      0,	// sub_dsp21
6947      0,	// sub_dsp22
6948      0,	// sub_dsp23
6949      0,	// sub_hi
6950      0,	// sub_lo
6951      0,	// sub_hi_then_sub_32
6952      0,	// sub_32_sub_hi_then_sub_32
6953    },
6954    {	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6955      57,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6956      0,	// sub_64
6957      0,	// sub_dsp16_19
6958      0,	// sub_dsp20
6959      0,	// sub_dsp21
6960      0,	// sub_dsp22
6961      0,	// sub_dsp23
6962      0,	// sub_hi
6963      0,	// sub_lo
6964      0,	// sub_hi_then_sub_32
6965      0,	// sub_32_sub_hi_then_sub_32
6966    },
6967    {	// ACC64
6968      0,	// sub_32
6969      0,	// sub_64
6970      0,	// sub_dsp16_19
6971      0,	// sub_dsp20
6972      0,	// sub_dsp21
6973      0,	// sub_dsp22
6974      0,	// sub_dsp23
6975      58,	// sub_hi -> ACC64
6976      58,	// sub_lo -> ACC64
6977      0,	// sub_hi_then_sub_32
6978      0,	// sub_32_sub_hi_then_sub_32
6979    },
6980    {	// GP64
6981      59,	// sub_32 -> GP64
6982      0,	// sub_64
6983      0,	// sub_dsp16_19
6984      0,	// sub_dsp20
6985      0,	// sub_dsp21
6986      0,	// sub_dsp22
6987      0,	// sub_dsp23
6988      0,	// sub_hi
6989      0,	// sub_lo
6990      0,	// sub_hi_then_sub_32
6991      0,	// sub_32_sub_hi_then_sub_32
6992    },
6993    {	// GPR64_with_sub_32_in_CPURAReg
6994      60,	// sub_32 -> GPR64_with_sub_32_in_CPURAReg
6995      0,	// sub_64
6996      0,	// sub_dsp16_19
6997      0,	// sub_dsp20
6998      0,	// sub_dsp21
6999      0,	// sub_dsp22
7000      0,	// sub_dsp23
7001      0,	// sub_hi
7002      0,	// sub_lo
7003      0,	// sub_hi_then_sub_32
7004      0,	// sub_32_sub_hi_then_sub_32
7005    },
7006    {	// GPR64_with_sub_32_in_GPR32ZERO
7007      61,	// sub_32 -> GPR64_with_sub_32_in_GPR32ZERO
7008      0,	// sub_64
7009      0,	// sub_dsp16_19
7010      0,	// sub_dsp20
7011      0,	// sub_dsp21
7012      0,	// sub_dsp22
7013      0,	// sub_dsp23
7014      0,	// sub_hi
7015      0,	// sub_lo
7016      0,	// sub_hi_then_sub_32
7017      0,	// sub_32_sub_hi_then_sub_32
7018    },
7019    {	// HI64
7020      62,	// sub_32 -> HI64
7021      0,	// sub_64
7022      0,	// sub_dsp16_19
7023      0,	// sub_dsp20
7024      0,	// sub_dsp21
7025      0,	// sub_dsp22
7026      0,	// sub_dsp23
7027      0,	// sub_hi
7028      0,	// sub_lo
7029      0,	// sub_hi_then_sub_32
7030      0,	// sub_32_sub_hi_then_sub_32
7031    },
7032    {	// LO64
7033      63,	// sub_32 -> LO64
7034      0,	// sub_64
7035      0,	// sub_dsp16_19
7036      0,	// sub_dsp20
7037      0,	// sub_dsp21
7038      0,	// sub_dsp22
7039      0,	// sub_dsp23
7040      0,	// sub_hi
7041      0,	// sub_lo
7042      0,	// sub_hi_then_sub_32
7043      0,	// sub_32_sub_hi_then_sub_32
7044    },
7045    {	// SP64
7046      64,	// sub_32 -> SP64
7047      0,	// sub_64
7048      0,	// sub_dsp16_19
7049      0,	// sub_dsp20
7050      0,	// sub_dsp21
7051      0,	// sub_dsp22
7052      0,	// sub_dsp23
7053      0,	// sub_hi
7054      0,	// sub_lo
7055      0,	// sub_hi_then_sub_32
7056      0,	// sub_32_sub_hi_then_sub_32
7057    },
7058    {	// MSA128B
7059      0,	// sub_32
7060      65,	// sub_64 -> MSA128B
7061      0,	// sub_dsp16_19
7062      0,	// sub_dsp20
7063      0,	// sub_dsp21
7064      0,	// sub_dsp22
7065      0,	// sub_dsp23
7066      65,	// sub_hi -> MSA128B
7067      65,	// sub_lo -> MSA128B
7068      0,	// sub_hi_then_sub_32
7069      0,	// sub_32_sub_hi_then_sub_32
7070    },
7071    {	// MSA128D
7072      0,	// sub_32
7073      66,	// sub_64 -> MSA128D
7074      0,	// sub_dsp16_19
7075      0,	// sub_dsp20
7076      0,	// sub_dsp21
7077      0,	// sub_dsp22
7078      0,	// sub_dsp23
7079      66,	// sub_hi -> MSA128D
7080      66,	// sub_lo -> MSA128D
7081      0,	// sub_hi_then_sub_32
7082      0,	// sub_32_sub_hi_then_sub_32
7083    },
7084    {	// MSA128H
7085      0,	// sub_32
7086      67,	// sub_64 -> MSA128H
7087      0,	// sub_dsp16_19
7088      0,	// sub_dsp20
7089      0,	// sub_dsp21
7090      0,	// sub_dsp22
7091      0,	// sub_dsp23
7092      67,	// sub_hi -> MSA128H
7093      67,	// sub_lo -> MSA128H
7094      0,	// sub_hi_then_sub_32
7095      0,	// sub_32_sub_hi_then_sub_32
7096    },
7097    {	// MSA128W
7098      0,	// sub_32
7099      68,	// sub_64 -> MSA128W
7100      0,	// sub_dsp16_19
7101      0,	// sub_dsp20
7102      0,	// sub_dsp21
7103      0,	// sub_dsp22
7104      0,	// sub_dsp23
7105      68,	// sub_hi -> MSA128W
7106      68,	// sub_lo -> MSA128W
7107      0,	// sub_hi_then_sub_32
7108      0,	// sub_32_sub_hi_then_sub_32
7109    },
7110    {	// MSA128WEvens
7111      0,	// sub_32
7112      69,	// sub_64 -> MSA128WEvens
7113      0,	// sub_dsp16_19
7114      0,	// sub_dsp20
7115      0,	// sub_dsp21
7116      0,	// sub_dsp22
7117      0,	// sub_dsp23
7118      69,	// sub_hi -> MSA128WEvens
7119      69,	// sub_lo -> MSA128WEvens
7120      0,	// sub_hi_then_sub_32
7121      0,	// sub_32_sub_hi_then_sub_32
7122    },
7123    {	// ACC128
7124      70,	// sub_32 -> ACC128
7125      0,	// sub_64
7126      0,	// sub_dsp16_19
7127      0,	// sub_dsp20
7128      0,	// sub_dsp21
7129      0,	// sub_dsp22
7130      0,	// sub_dsp23
7131      70,	// sub_hi -> ACC128
7132      70,	// sub_lo -> ACC128
7133      70,	// sub_hi_then_sub_32 -> ACC128
7134      70,	// sub_32_sub_hi_then_sub_32 -> ACC128
7135    },
7136  };
7137  assert(RC && "Missing regclass");
7138  if (!Idx) return RC;
7139  --Idx;
7140  assert(Idx < 11 && "Bad subreg");
7141  unsigned TV = Table[RC->getID()][Idx];
7142  return TV ? getRegClass(TV - 1) : nullptr;
7143}
7144
7145/// Get the weight in units of pressure for this register class.
7146const RegClassWeight &MipsGenRegisterInfo::
7147getRegClassWeight(const TargetRegisterClass *RC) const {
7148  static const RegClassWeight RCWeightTable[] = {
7149    {2, 64},  	// MSA128F16
7150    {0, 0},  	// CCR
7151    {0, 0},  	// COP0
7152    {0, 0},  	// COP2
7153    {0, 0},  	// COP3
7154    {1, 32},  	// DSPR
7155    {1, 32},  	// FGR32
7156    {1, 32},  	// FGRCC
7157    {1, 32},  	// GPR32
7158    {0, 0},  	// HWRegs
7159    {0, 0},  	// MSACtrl
7160    {1, 31},  	// GPR32NONZERO
7161    {1, 9},  	// CPU16RegsPlusSP
7162    {1, 8},  	// CPU16Regs
7163    {0, 0},  	// FCC
7164    {1, 8},  	// GPRMM16
7165    {1, 8},  	// GPRMM16MoveP
7166    {1, 8},  	// GPRMM16Zero
7167    {1, 7},  	// CPU16Regs_and_GPRMM16Zero
7168    {1, 7},  	// GPR32NONZERO_and_GPRMM16MoveP
7169    {1, 5},  	// GPRMM16MovePPairSecond
7170    {1, 4},  	// CPU16Regs_and_GPRMM16MoveP
7171    {1, 4},  	// GPRMM16MoveP_and_GPRMM16Zero
7172    {1, 4},  	// HI32DSP
7173    {1, 4},  	// LO32DSP
7174    {1, 3},  	// CPU16Regs_and_GPRMM16MovePPairSecond
7175    {1, 3},  	// GPRMM16MovePPairFirst
7176    {1, 3},  	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7177    {1, 2},  	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7178    {1, 1},  	// CPURAReg
7179    {1, 1},  	// CPUSPReg
7180    {1, 1},  	// DSPCC
7181    {1, 1},  	// GP32
7182    {1, 1},  	// GPR32ZERO
7183    {1, 1},  	// HI32
7184    {1, 1},  	// LO32
7185    {1, 1},  	// SP32
7186    {2, 64},  	// FGR64
7187    {1, 32},  	// GPR64
7188    {1, 31},  	// GPR64_with_sub_32_in_GPR32NONZERO
7189    {2, 32},  	// AFGR64
7190    {1, 9},  	// GPR64_with_sub_32_in_CPU16RegsPlusSP
7191    {1, 8},  	// GPR64_with_sub_32_in_CPU16Regs
7192    {1, 8},  	// GPR64_with_sub_32_in_GPRMM16MoveP
7193    {1, 8},  	// GPR64_with_sub_32_in_GPRMM16Zero
7194    {1, 7},  	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
7195    {1, 7},  	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
7196    {1, 5},  	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond
7197    {2, 8},  	// ACC64DSP
7198    {1, 4},  	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
7199    {1, 4},  	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
7200    {1, 3},  	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
7201    {1, 3},  	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst
7202    {1, 3},  	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7203    {0, 0},  	// OCTEON_MPL
7204    {0, 0},  	// OCTEON_P
7205    {1, 2},  	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7206    {2, 2},  	// ACC64
7207    {1, 1},  	// GP64
7208    {1, 1},  	// GPR64_with_sub_32_in_CPURAReg
7209    {1, 1},  	// GPR64_with_sub_32_in_GPR32ZERO
7210    {1, 1},  	// HI64
7211    {1, 1},  	// LO64
7212    {1, 1},  	// SP64
7213    {2, 64},  	// MSA128B
7214    {2, 64},  	// MSA128D
7215    {2, 64},  	// MSA128H
7216    {2, 64},  	// MSA128W
7217    {2, 32},  	// MSA128WEvens
7218    {2, 2},  	// ACC128
7219  };
7220  return RCWeightTable[RC->getID()];
7221}
7222
7223/// Get the weight in units of pressure for this register unit.
7224unsigned MipsGenRegisterInfo::
7225getRegUnitWeight(unsigned RegUnit) const {
7226  assert(RegUnit < 321 && "invalid register unit");
7227  // All register units have unit weight.
7228  return 1;
7229}
7230
7231
7232// Get the number of dimensions of register pressure.
7233unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {
7234  return 20;
7235}
7236
7237// Get the name of this register unit pressure set.
7238const char *MipsGenRegisterInfo::
7239getRegPressureSetName(unsigned Idx) const {
7240  static const char *const PressureNameTable[] = {
7241    "DSPCC",
7242    "GPR32ZERO",
7243    "GPR64_with_sub_32_in_CPURAReg",
7244    "HI32",
7245    "GPRMM16MovePPairFirst",
7246    "CPU16Regs_and_GPRMM16MoveP",
7247    "HI32DSP",
7248    "LO32DSP",
7249    "GPRMM16MovePPairSecond",
7250    "GPRMM16MoveP",
7251    "ACC64DSP",
7252    "CPU16Regs",
7253    "GPRMM16Zero+GPRMM16MovePPairSecond",
7254    "CPU16Regs+GPRMM16MovePPairSecond",
7255    "CPU16Regs+GPRMM16MoveP",
7256    "DSPR",
7257    "FGR32",
7258    "MSA128WEvens",
7259    "FGR32+MSA128WEvens",
7260    "MSA128F16",
7261  };
7262  return PressureNameTable[Idx];
7263}
7264
7265// Get the register unit pressure limit for this dimension.
7266// This limit must be adjusted dynamically for reserved registers.
7267unsigned MipsGenRegisterInfo::
7268getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
7269  static const uint8_t PressureLimitTable[] = {
7270    1,  	// 0: DSPCC
7271    1,  	// 1: GPR32ZERO
7272    1,  	// 2: GPR64_with_sub_32_in_CPURAReg
7273    2,  	// 3: HI32
7274    3,  	// 4: GPRMM16MovePPairFirst
7275    5,  	// 5: CPU16Regs_and_GPRMM16MoveP
7276    5,  	// 6: HI32DSP
7277    5,  	// 7: LO32DSP
7278    6,  	// 8: GPRMM16MovePPairSecond
7279    8,  	// 9: GPRMM16MoveP
7280    8,  	// 10: ACC64DSP
7281    10,  	// 11: CPU16Regs
7282    10,  	// 12: GPRMM16Zero+GPRMM16MovePPairSecond
7283    11,  	// 13: CPU16Regs+GPRMM16MovePPairSecond
7284    13,  	// 14: CPU16Regs+GPRMM16MoveP
7285    32,  	// 15: DSPR
7286    32,  	// 16: FGR32
7287    32,  	// 17: MSA128WEvens
7288    48,  	// 18: FGR32+MSA128WEvens
7289    64,  	// 19: MSA128F16
7290  };
7291  return PressureLimitTable[Idx];
7292}
7293
7294/// Table of pressure sets per register class or unit.
7295static const int RCSetsTable[] = {
7296  /* 0 */ 0, -1,
7297  /* 2 */ 6, 10, -1,
7298  /* 5 */ 3, 6, 7, 10, -1,
7299  /* 10 */ 2, 15, -1,
7300  /* 13 */ 8, 12, 13, 15, -1,
7301  /* 18 */ 9, 14, 15, -1,
7302  /* 22 */ 1, 5, 9, 11, 12, 14, 15, -1,
7303  /* 30 */ 5, 9, 11, 13, 14, 15, -1,
7304  /* 37 */ 4, 8, 11, 12, 13, 14, 15, -1,
7305  /* 45 */ 5, 9, 11, 12, 13, 14, 15, -1,
7306  /* 53 */ 16, 18, 19, -1,
7307  /* 57 */ 16, 17, 18, 19, -1,
7308};
7309
7310/// Get the dimensions of register pressure impacted by this register class.
7311/// Returns a -1 terminated array of pressure set IDs
7312const int* MipsGenRegisterInfo::
7313getRegClassPressureSets(const TargetRegisterClass *RC) const {
7314  static const uint8_t RCSetStartTable[] = {
7315    55,1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,};
7316  return &RCSetsTable[RCSetStartTable[RC->getID()]];
7317}
7318
7319/// Get the dimensions of register pressure impacted by this register unit.
7320/// Returns a -1 terminated array of pressure set IDs
7321const int* MipsGenRegisterInfo::
7322getRegUnitPressureSets(unsigned RegUnit) const {
7323  assert(RegUnit < 321 && "invalid register unit");
7324  static const uint8_t RUSetStartTable[] = {
7325    11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,};
7326  return &RCSetsTable[RUSetStartTable[RegUnit]];
7327}
7328
7329extern const MCRegisterDesc MipsRegDesc[];
7330extern const MCPhysReg MipsRegDiffLists[];
7331extern const LaneBitmask MipsLaneMaskLists[];
7332extern const char MipsRegStrings[];
7333extern const char MipsRegClassStrings[];
7334extern const MCPhysReg MipsRegUnitRoots[][2];
7335extern const uint16_t MipsSubRegIdxLists[];
7336extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[];
7337extern const uint16_t MipsRegEncodingTable[];
7338// Mips Dwarf<->LLVM register mappings.
7339extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];
7340extern const unsigned MipsDwarfFlavour0Dwarf2LSize;
7341
7342extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];
7343extern const unsigned MipsEHFlavour0Dwarf2LSize;
7344
7345extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];
7346extern const unsigned MipsDwarfFlavour0L2DwarfSize;
7347
7348extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];
7349extern const unsigned MipsEHFlavour0L2DwarfSize;
7350
7351MipsGenRegisterInfo::
7352MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
7353      unsigned PC, unsigned HwMode)
7354  : TargetRegisterInfo(MipsRegInfoDesc, RegisterClasses, RegisterClasses+70,
7355             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
7356             LaneBitmask(0xFFFFFF80), RegClassInfos, HwMode) {
7357  InitMCRegisterInfo(MipsRegDesc, 442, RA, PC,
7358                     MipsMCRegisterClasses, 70,
7359                     MipsRegUnitRoots,
7360                     321,
7361                     MipsRegDiffLists,
7362                     MipsLaneMaskLists,
7363                     MipsRegStrings,
7364                     MipsRegClassStrings,
7365                     MipsSubRegIdxLists,
7366                     12,
7367                     MipsSubRegIdxRanges,
7368                     MipsRegEncodingTable);
7369
7370  switch (DwarfFlavour) {
7371  default:
7372    llvm_unreachable("Unknown DWARF flavour");
7373  case 0:
7374    mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
7375    break;
7376  }
7377  switch (EHFlavour) {
7378  default:
7379    llvm_unreachable("Unknown DWARF flavour");
7380  case 0:
7381    mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
7382    break;
7383  }
7384  switch (DwarfFlavour) {
7385  default:
7386    llvm_unreachable("Unknown DWARF flavour");
7387  case 0:
7388    mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
7389    break;
7390  }
7391  switch (EHFlavour) {
7392  default:
7393    llvm_unreachable("Unknown DWARF flavour");
7394  case 0:
7395    mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
7396    break;
7397  }
7398}
7399
7400static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };
7401static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x00000000, 0x00000000, 0x00000000, };
7402static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };
7403static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x00000000, 0x00000000, 0x00000000, };
7404static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };
7405static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf0000000, 0x00000001, 0x03ffffe4, };
7406static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };
7407static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf0000000, 0x00000000, 0x03ffffc0, };
7408static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };
7409static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03c00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x00000000, 0x00000000, 0x00000000, };
7410static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
7411static const uint32_t CSR_N32_RegMask[] = { 0x00080300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x00000000, 0xaaa00000, 0x00003fc0, };
7412static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
7413static const uint32_t CSR_N64_RegMask[] = { 0x00080300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x00000000, 0xfe000000, 0x00003fc1, };
7414static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
7415static const uint32_t CSR_O32_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x00000000, 0x00000000, 0x00000000, };
7416static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
7417static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x00000000, 0xaaa00000, 0x00000000, };
7418static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
7419static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x00000000, 0x00000000, 0x00000000, };
7420static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
7421static const uint32_t CSR_SingleFloatOnly_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x00000000, 0x00000000, 0x00000000, };
7422
7423
7424ArrayRef<const uint32_t *> MipsGenRegisterInfo::getRegMasks() const {
7425  static const uint32_t *const Masks[] = {
7426    CSR_Interrupt_32_RegMask,
7427    CSR_Interrupt_32R6_RegMask,
7428    CSR_Interrupt_64_RegMask,
7429    CSR_Interrupt_64R6_RegMask,
7430    CSR_Mips16RetHelper_RegMask,
7431    CSR_N32_RegMask,
7432    CSR_N64_RegMask,
7433    CSR_O32_RegMask,
7434    CSR_O32_FP64_RegMask,
7435    CSR_O32_FPXX_RegMask,
7436    CSR_SingleFloatOnly_RegMask,
7437  };
7438  return makeArrayRef(Masks);
7439}
7440
7441ArrayRef<const char *> MipsGenRegisterInfo::getRegMaskNames() const {
7442  static const char *const Names[] = {
7443    "CSR_Interrupt_32",
7444    "CSR_Interrupt_32R6",
7445    "CSR_Interrupt_64",
7446    "CSR_Interrupt_64R6",
7447    "CSR_Mips16RetHelper",
7448    "CSR_N32",
7449    "CSR_N64",
7450    "CSR_O32",
7451    "CSR_O32_FP64",
7452    "CSR_O32_FPXX",
7453    "CSR_SingleFloatOnly",
7454  };
7455  return makeArrayRef(Names);
7456}
7457
7458const MipsFrameLowering *
7459MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
7460  return static_cast<const MipsFrameLowering *>(
7461      MF.getSubtarget().getFrameLowering());
7462}
7463
7464} // end namespace llvm
7465
7466#endif // GET_REGINFO_TARGET_DESC
7467
7468