1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Calling Convention Implementation Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT, 10 MVT LocVT, CCValAssign::LocInfo LocInfo, 11 ISD::ArgFlagsTy ArgFlags, CCState &State); 12bool llvm::CC_X86(unsigned ValNo, MVT ValVT, 13 MVT LocVT, CCValAssign::LocInfo LocInfo, 14 ISD::ArgFlagsTy ArgFlags, CCState &State); 15static bool CC_X86_32(unsigned ValNo, MVT ValVT, 16 MVT LocVT, CCValAssign::LocInfo LocInfo, 17 ISD::ArgFlagsTy ArgFlags, CCState &State); 18static bool CC_X86_32_C(unsigned ValNo, MVT ValVT, 19 MVT LocVT, CCValAssign::LocInfo LocInfo, 20 ISD::ArgFlagsTy ArgFlags, CCState &State); 21static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT, 22 MVT LocVT, CCValAssign::LocInfo LocInfo, 23 ISD::ArgFlagsTy ArgFlags, CCState &State); 24static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT, 25 MVT LocVT, CCValAssign::LocInfo LocInfo, 26 ISD::ArgFlagsTy ArgFlags, CCState &State); 27static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT, 28 MVT LocVT, CCValAssign::LocInfo LocInfo, 29 ISD::ArgFlagsTy ArgFlags, CCState &State); 30static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT, 31 MVT LocVT, CCValAssign::LocInfo LocInfo, 32 ISD::ArgFlagsTy ArgFlags, CCState &State); 33static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT, 34 MVT LocVT, CCValAssign::LocInfo LocInfo, 35 ISD::ArgFlagsTy ArgFlags, CCState &State); 36static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT, 37 MVT LocVT, CCValAssign::LocInfo LocInfo, 38 ISD::ArgFlagsTy ArgFlags, CCState &State); 39static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT, 40 MVT LocVT, CCValAssign::LocInfo LocInfo, 41 ISD::ArgFlagsTy ArgFlags, CCState &State); 42static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT, 43 MVT LocVT, CCValAssign::LocInfo LocInfo, 44 ISD::ArgFlagsTy ArgFlags, CCState &State); 45static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT, 46 MVT LocVT, CCValAssign::LocInfo LocInfo, 47 ISD::ArgFlagsTy ArgFlags, CCState &State); 48static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT, 49 MVT LocVT, CCValAssign::LocInfo LocInfo, 50 ISD::ArgFlagsTy ArgFlags, CCState &State); 51static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT, 52 MVT LocVT, CCValAssign::LocInfo LocInfo, 53 ISD::ArgFlagsTy ArgFlags, CCState &State); 54static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT, 55 MVT LocVT, CCValAssign::LocInfo LocInfo, 56 ISD::ArgFlagsTy ArgFlags, CCState &State); 57static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT, 58 MVT LocVT, CCValAssign::LocInfo LocInfo, 59 ISD::ArgFlagsTy ArgFlags, CCState &State); 60static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT, 61 MVT LocVT, CCValAssign::LocInfo LocInfo, 62 ISD::ArgFlagsTy ArgFlags, CCState &State); 63static bool CC_X86_64(unsigned ValNo, MVT ValVT, 64 MVT LocVT, CCValAssign::LocInfo LocInfo, 65 ISD::ArgFlagsTy ArgFlags, CCState &State); 66static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT, 67 MVT LocVT, CCValAssign::LocInfo LocInfo, 68 ISD::ArgFlagsTy ArgFlags, CCState &State); 69static bool CC_X86_64_C(unsigned ValNo, MVT ValVT, 70 MVT LocVT, CCValAssign::LocInfo LocInfo, 71 ISD::ArgFlagsTy ArgFlags, CCState &State); 72static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT, 73 MVT LocVT, CCValAssign::LocInfo LocInfo, 74 ISD::ArgFlagsTy ArgFlags, CCState &State); 75static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT, 76 MVT LocVT, CCValAssign::LocInfo LocInfo, 77 ISD::ArgFlagsTy ArgFlags, CCState &State); 78static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT, 79 MVT LocVT, CCValAssign::LocInfo LocInfo, 80 ISD::ArgFlagsTy ArgFlags, CCState &State); 81static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT, 82 MVT LocVT, CCValAssign::LocInfo LocInfo, 83 ISD::ArgFlagsTy ArgFlags, CCState &State); 84static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT, 85 MVT LocVT, CCValAssign::LocInfo LocInfo, 86 ISD::ArgFlagsTy ArgFlags, CCState &State); 87static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT, 88 MVT LocVT, CCValAssign::LocInfo LocInfo, 89 ISD::ArgFlagsTy ArgFlags, CCState &State); 90static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT, 91 MVT LocVT, CCValAssign::LocInfo LocInfo, 92 ISD::ArgFlagsTy ArgFlags, CCState &State); 93static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT, 94 MVT LocVT, CCValAssign::LocInfo LocInfo, 95 ISD::ArgFlagsTy ArgFlags, CCState &State); 96static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT, 97 MVT LocVT, CCValAssign::LocInfo LocInfo, 98 ISD::ArgFlagsTy ArgFlags, CCState &State); 99static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT, 100 MVT LocVT, CCValAssign::LocInfo LocInfo, 101 ISD::ArgFlagsTy ArgFlags, CCState &State); 102static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT, 103 MVT LocVT, CCValAssign::LocInfo LocInfo, 104 ISD::ArgFlagsTy ArgFlags, CCState &State); 105static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT, 106 MVT LocVT, CCValAssign::LocInfo LocInfo, 107 ISD::ArgFlagsTy ArgFlags, CCState &State); 108bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT, 109 MVT LocVT, CCValAssign::LocInfo LocInfo, 110 ISD::ArgFlagsTy ArgFlags, CCState &State); 111static bool RetCC_X86Common(unsigned ValNo, MVT ValVT, 112 MVT LocVT, CCValAssign::LocInfo LocInfo, 113 ISD::ArgFlagsTy ArgFlags, CCState &State); 114static bool RetCC_X86_32(unsigned ValNo, MVT ValVT, 115 MVT LocVT, CCValAssign::LocInfo LocInfo, 116 ISD::ArgFlagsTy ArgFlags, CCState &State); 117static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT, 118 MVT LocVT, CCValAssign::LocInfo LocInfo, 119 ISD::ArgFlagsTy ArgFlags, CCState &State); 120static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT, 121 MVT LocVT, CCValAssign::LocInfo LocInfo, 122 ISD::ArgFlagsTy ArgFlags, CCState &State); 123static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT, 124 MVT LocVT, CCValAssign::LocInfo LocInfo, 125 ISD::ArgFlagsTy ArgFlags, CCState &State); 126static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT, 127 MVT LocVT, CCValAssign::LocInfo LocInfo, 128 ISD::ArgFlagsTy ArgFlags, CCState &State); 129static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT, 130 MVT LocVT, CCValAssign::LocInfo LocInfo, 131 ISD::ArgFlagsTy ArgFlags, CCState &State); 132static bool RetCC_X86_64(unsigned ValNo, MVT ValVT, 133 MVT LocVT, CCValAssign::LocInfo LocInfo, 134 ISD::ArgFlagsTy ArgFlags, CCState &State); 135static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT, 136 MVT LocVT, CCValAssign::LocInfo LocInfo, 137 ISD::ArgFlagsTy ArgFlags, CCState &State); 138static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT, 139 MVT LocVT, CCValAssign::LocInfo LocInfo, 140 ISD::ArgFlagsTy ArgFlags, CCState &State); 141static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT, 142 MVT LocVT, CCValAssign::LocInfo LocInfo, 143 ISD::ArgFlagsTy ArgFlags, CCState &State); 144static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT, 145 MVT LocVT, CCValAssign::LocInfo LocInfo, 146 ISD::ArgFlagsTy ArgFlags, CCState &State); 147static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT, 148 MVT LocVT, CCValAssign::LocInfo LocInfo, 149 ISD::ArgFlagsTy ArgFlags, CCState &State); 150static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT, 151 MVT LocVT, CCValAssign::LocInfo LocInfo, 152 ISD::ArgFlagsTy ArgFlags, CCState &State); 153static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT, 154 MVT LocVT, CCValAssign::LocInfo LocInfo, 155 ISD::ArgFlagsTy ArgFlags, CCState &State); 156static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT, 157 MVT LocVT, CCValAssign::LocInfo LocInfo, 158 ISD::ArgFlagsTy ArgFlags, CCState &State); 159static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT, 160 MVT LocVT, CCValAssign::LocInfo LocInfo, 161 ISD::ArgFlagsTy ArgFlags, CCState &State); 162static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT, 163 MVT LocVT, CCValAssign::LocInfo LocInfo, 164 ISD::ArgFlagsTy ArgFlags, CCState &State); 165 166 167static bool CC_Intel_OCL_BI(unsigned ValNo, MVT ValVT, 168 MVT LocVT, CCValAssign::LocInfo LocInfo, 169 ISD::ArgFlagsTy ArgFlags, CCState &State) { 170 171 if (LocVT == MVT::i32) { 172 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 173 static const MCPhysReg RegList1[] = { 174 X86::ECX, X86::EDX, X86::R8D, X86::R9D 175 }; 176 if (unsigned Reg = State.AllocateReg(RegList1)) { 177 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 178 return false; 179 } 180 } 181 } 182 183 if (LocVT == MVT::i64) { 184 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 185 static const MCPhysReg RegList2[] = { 186 X86::RCX, X86::RDX, X86::R8, X86::R9 187 }; 188 if (unsigned Reg = State.AllocateReg(RegList2)) { 189 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 190 return false; 191 } 192 } 193 } 194 195 if (LocVT == MVT::i32) { 196 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 197 static const MCPhysReg RegList3[] = { 198 X86::EDI, X86::ESI, X86::EDX, X86::ECX 199 }; 200 if (unsigned Reg = State.AllocateReg(RegList3)) { 201 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 202 return false; 203 } 204 } 205 } 206 207 if (LocVT == MVT::i64) { 208 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 209 static const MCPhysReg RegList4[] = { 210 X86::RDI, X86::RSI, X86::RDX, X86::RCX 211 }; 212 if (unsigned Reg = State.AllocateReg(RegList4)) { 213 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 214 return false; 215 } 216 } 217 } 218 219 if (LocVT == MVT::i32) { 220 unsigned Offset5 = State.AllocateStack(4, 4); 221 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo)); 222 return false; 223 } 224 225 if (LocVT == MVT::f32 || 226 LocVT == MVT::f64 || 227 LocVT == MVT::v4i32 || 228 LocVT == MVT::v2i64 || 229 LocVT == MVT::v4f32 || 230 LocVT == MVT::v2f64) { 231 static const MCPhysReg RegList6[] = { 232 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 233 }; 234 if (unsigned Reg = State.AllocateReg(RegList6)) { 235 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 236 return false; 237 } 238 } 239 240 if (LocVT == MVT::v8f32 || 241 LocVT == MVT::v4f64 || 242 LocVT == MVT::v8i32 || 243 LocVT == MVT::v4i64) { 244 static const MCPhysReg RegList7[] = { 245 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3 246 }; 247 if (unsigned Reg = State.AllocateReg(RegList7)) { 248 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 249 return false; 250 } 251 } 252 253 if (LocVT == MVT::v16f32 || 254 LocVT == MVT::v8f64 || 255 LocVT == MVT::v16i32 || 256 LocVT == MVT::v8i64) { 257 static const MCPhysReg RegList8[] = { 258 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 259 }; 260 if (unsigned Reg = State.AllocateReg(RegList8)) { 261 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 262 return false; 263 } 264 } 265 266 if (LocVT == MVT::v16i1 || 267 LocVT == MVT::v8i1) { 268 if (unsigned Reg = State.AllocateReg(X86::K1)) { 269 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 270 return false; 271 } 272 } 273 274 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 275 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 276 return false; 277 } 278 279 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 280 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 281 return false; 282 } 283 284 if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 285 return false; 286 287 return true; // CC didn't match. 288} 289 290 291bool llvm::CC_X86(unsigned ValNo, MVT ValVT, 292 MVT LocVT, CCValAssign::LocInfo LocInfo, 293 ISD::ArgFlagsTy ArgFlags, CCState &State) { 294 295 if (State.getCallingConv() == CallingConv::Intel_OCL_BI) { 296 if (!CC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 297 return false; 298 } 299 300 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 301 if (!CC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 302 return false; 303 } 304 305 if (!CC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 306 return false; 307 308 return true; // CC didn't match. 309} 310 311 312static bool CC_X86_32(unsigned ValNo, MVT ValVT, 313 MVT LocVT, CCValAssign::LocInfo LocInfo, 314 ISD::ArgFlagsTy ArgFlags, CCState &State) { 315 316 if (State.getCallingConv() == CallingConv::X86_INTR) { 317 if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 318 return false; 319 } 320 321 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetMCU()) { 322 if (!CC_X86_32_MCU(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 323 return false; 324 } 325 326 if (State.getCallingConv() == CallingConv::X86_FastCall) { 327 if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 328 return false; 329 } 330 331 if (State.getCallingConv() == CallingConv::X86_VectorCall) { 332 if (!CC_X86_Win32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 333 return false; 334 } 335 336 if (State.getCallingConv() == CallingConv::X86_ThisCall) { 337 if (!CC_X86_32_ThisCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 338 return false; 339 } 340 341 if (State.getCallingConv() == CallingConv::CFGuard_Check) { 342 if (!CC_X86_Win32_CFGuard_Check(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 343 return false; 344 } 345 346 if (State.getCallingConv() == CallingConv::Fast) { 347 if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 348 return false; 349 } 350 351 if (State.getCallingConv() == CallingConv::Tail) { 352 if (!CC_X86_32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 353 return false; 354 } 355 356 if (State.getCallingConv() == CallingConv::GHC) { 357 if (!CC_X86_32_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 358 return false; 359 } 360 361 if (State.getCallingConv() == CallingConv::HiPE) { 362 if (!CC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 363 return false; 364 } 365 366 if (State.getCallingConv() == CallingConv::X86_RegCall) { 367 if (!CC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 368 return false; 369 } 370 371 if (!CC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 372 return false; 373 374 return true; // CC didn't match. 375} 376 377 378static bool CC_X86_32_C(unsigned ValNo, MVT ValVT, 379 MVT LocVT, CCValAssign::LocInfo LocInfo, 380 ISD::ArgFlagsTy ArgFlags, CCState &State) { 381 382 if (LocVT == MVT::i1 || 383 LocVT == MVT::i8 || 384 LocVT == MVT::i16 || 385 LocVT == MVT::v1i1) { 386 LocVT = MVT::i32; 387 if (ArgFlags.isSExt()) 388 LocInfo = CCValAssign::SExt; 389 else if (ArgFlags.isZExt()) 390 LocInfo = CCValAssign::ZExt; 391 else 392 LocInfo = CCValAssign::AExt; 393 } 394 395 if (ArgFlags.isNest()) { 396 if (unsigned Reg = State.AllocateReg(X86::ECX)) { 397 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 398 return false; 399 } 400 } 401 402 if (!State.isVarArg()) { 403 if (ArgFlags.isInReg()) { 404 if (LocVT == MVT::i32) { 405 static const MCPhysReg RegList1[] = { 406 X86::EAX, X86::EDX, X86::ECX 407 }; 408 if (unsigned Reg = State.AllocateReg(RegList1)) { 409 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 410 return false; 411 } 412 } 413 } 414 } 415 416 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 417 return false; 418 419 return true; // CC didn't match. 420} 421 422 423static bool CC_X86_32_Common(unsigned ValNo, MVT ValVT, 424 MVT LocVT, CCValAssign::LocInfo LocInfo, 425 ISD::ArgFlagsTy ArgFlags, CCState &State) { 426 427 if (ArgFlags.isByVal()) { 428 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags); 429 return false; 430 } 431 432 if (!State.isVarArg()) { 433 if (ArgFlags.isInReg()) { 434 if (LocVT == MVT::f32 || 435 LocVT == MVT::f64) { 436 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { 437 static const MCPhysReg RegList1[] = { 438 X86::XMM0, X86::XMM1, X86::XMM2 439 }; 440 if (unsigned Reg = State.AllocateReg(RegList1)) { 441 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 442 return false; 443 } 444 } 445 } 446 } 447 } 448 449 if (!State.isVarArg()) { 450 if (LocVT == MVT::x86mmx) { 451 static const MCPhysReg RegList2[] = { 452 X86::MM0, X86::MM1, X86::MM2 453 }; 454 if (unsigned Reg = State.AllocateReg(RegList2)) { 455 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 456 return false; 457 } 458 } 459 } 460 461 if (LocVT == MVT::i32 || 462 LocVT == MVT::f32) { 463 unsigned Offset3 = State.AllocateStack(4, 4); 464 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); 465 return false; 466 } 467 468 if (LocVT == MVT::f64) { 469 unsigned Offset4 = State.AllocateStack(8, 4); 470 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo)); 471 return false; 472 } 473 474 if (LocVT == MVT::f80) { 475 unsigned Offset5 = State.AllocateStack( 476 State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 4); 477 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo)); 478 return false; 479 } 480 481 if (LocVT == MVT::v2i1) { 482 LocVT = MVT::v2i64; 483 if (ArgFlags.isSExt()) 484 LocInfo = CCValAssign::SExt; 485 else if (ArgFlags.isZExt()) 486 LocInfo = CCValAssign::ZExt; 487 else 488 LocInfo = CCValAssign::AExt; 489 } 490 491 if (LocVT == MVT::v4i1) { 492 LocVT = MVT::v4i32; 493 if (ArgFlags.isSExt()) 494 LocInfo = CCValAssign::SExt; 495 else if (ArgFlags.isZExt()) 496 LocInfo = CCValAssign::ZExt; 497 else 498 LocInfo = CCValAssign::AExt; 499 } 500 501 if (LocVT == MVT::v8i1) { 502 LocVT = MVT::v8i16; 503 if (ArgFlags.isSExt()) 504 LocInfo = CCValAssign::SExt; 505 else if (ArgFlags.isZExt()) 506 LocInfo = CCValAssign::ZExt; 507 else 508 LocInfo = CCValAssign::AExt; 509 } 510 511 if (LocVT == MVT::v16i1) { 512 LocVT = MVT::v16i8; 513 if (ArgFlags.isSExt()) 514 LocInfo = CCValAssign::SExt; 515 else if (ArgFlags.isZExt()) 516 LocInfo = CCValAssign::ZExt; 517 else 518 LocInfo = CCValAssign::AExt; 519 } 520 521 if (LocVT == MVT::v32i1) { 522 LocVT = MVT::v32i8; 523 if (ArgFlags.isSExt()) 524 LocInfo = CCValAssign::SExt; 525 else if (ArgFlags.isZExt()) 526 LocInfo = CCValAssign::ZExt; 527 else 528 LocInfo = CCValAssign::AExt; 529 } 530 531 if (LocVT == MVT::v64i1) { 532 LocVT = MVT::v64i8; 533 if (ArgFlags.isSExt()) 534 LocInfo = CCValAssign::SExt; 535 else if (ArgFlags.isZExt()) 536 LocInfo = CCValAssign::ZExt; 537 else 538 LocInfo = CCValAssign::AExt; 539 } 540 541 if (LocVT == MVT::x86mmx) { 542 unsigned Offset6 = State.AllocateStack(8, 4); 543 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); 544 return false; 545 } 546 547 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) { 548 if (!CC_X86_32_Vector_Darwin(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 549 return false; 550 } 551 552 if (!CC_X86_32_Vector_Standard(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 553 return false; 554 555 return true; // CC didn't match. 556} 557 558 559static bool CC_X86_32_FastCC(unsigned ValNo, MVT ValVT, 560 MVT LocVT, CCValAssign::LocInfo LocInfo, 561 ISD::ArgFlagsTy ArgFlags, CCState &State) { 562 563 if (ArgFlags.isByVal()) { 564 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags); 565 return false; 566 } 567 568 if (LocVT == MVT::i1 || 569 LocVT == MVT::i8 || 570 LocVT == MVT::i16 || 571 LocVT == MVT::v1i1) { 572 LocVT = MVT::i32; 573 if (ArgFlags.isSExt()) 574 LocInfo = CCValAssign::SExt; 575 else if (ArgFlags.isZExt()) 576 LocInfo = CCValAssign::ZExt; 577 else 578 LocInfo = CCValAssign::AExt; 579 } 580 581 if (ArgFlags.isNest()) { 582 if (unsigned Reg = State.AllocateReg(X86::EAX)) { 583 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 584 return false; 585 } 586 } 587 588 if (LocVT == MVT::i32) { 589 static const MCPhysReg RegList1[] = { 590 X86::ECX, X86::EDX 591 }; 592 if (unsigned Reg = State.AllocateReg(RegList1)) { 593 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 594 return false; 595 } 596 } 597 598 if (!State.isVarArg()) { 599 if (LocVT == MVT::f32 || 600 LocVT == MVT::f64) { 601 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { 602 static const MCPhysReg RegList2[] = { 603 X86::XMM0, X86::XMM1, X86::XMM2 604 }; 605 if (unsigned Reg = State.AllocateReg(RegList2)) { 606 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 607 return false; 608 } 609 } 610 } 611 } 612 613 if (LocVT == MVT::f64) { 614 unsigned Offset3 = State.AllocateStack(8, 8); 615 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); 616 return false; 617 } 618 619 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 620 return false; 621 622 return true; // CC didn't match. 623} 624 625 626static bool CC_X86_32_FastCall(unsigned ValNo, MVT ValVT, 627 MVT LocVT, CCValAssign::LocInfo LocInfo, 628 ISD::ArgFlagsTy ArgFlags, CCState &State) { 629 630 if (LocVT == MVT::i1) { 631 LocVT = MVT::i8; 632 if (ArgFlags.isSExt()) 633 LocInfo = CCValAssign::SExt; 634 else if (ArgFlags.isZExt()) 635 LocInfo = CCValAssign::ZExt; 636 else 637 LocInfo = CCValAssign::AExt; 638 } 639 640 if (ArgFlags.isNest()) { 641 if (unsigned Reg = State.AllocateReg(X86::EAX)) { 642 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 643 return false; 644 } 645 } 646 647 if (ArgFlags.isInReg()) { 648 if (LocVT == MVT::i8) { 649 static const MCPhysReg RegList1[] = { 650 X86::CL, X86::DL 651 }; 652 if (unsigned Reg = State.AllocateReg(RegList1)) { 653 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 654 return false; 655 } 656 } 657 } 658 659 if (ArgFlags.isInReg()) { 660 if (LocVT == MVT::i16) { 661 static const MCPhysReg RegList2[] = { 662 X86::CX, X86::DX 663 }; 664 if (unsigned Reg = State.AllocateReg(RegList2)) { 665 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 666 return false; 667 } 668 } 669 } 670 671 if (ArgFlags.isInReg()) { 672 if (LocVT == MVT::i32) { 673 static const MCPhysReg RegList3[] = { 674 X86::ECX, X86::EDX 675 }; 676 if (unsigned Reg = State.AllocateReg(RegList3)) { 677 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 678 return false; 679 } 680 } 681 } 682 683 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 684 return false; 685 686 return true; // CC didn't match. 687} 688 689 690static bool CC_X86_32_GHC(unsigned ValNo, MVT ValVT, 691 MVT LocVT, CCValAssign::LocInfo LocInfo, 692 ISD::ArgFlagsTy ArgFlags, CCState &State) { 693 694 if (LocVT == MVT::i8 || 695 LocVT == MVT::i16) { 696 LocVT = MVT::i32; 697 if (ArgFlags.isSExt()) 698 LocInfo = CCValAssign::SExt; 699 else if (ArgFlags.isZExt()) 700 LocInfo = CCValAssign::ZExt; 701 else 702 LocInfo = CCValAssign::AExt; 703 } 704 705 if (LocVT == MVT::i32) { 706 static const MCPhysReg RegList1[] = { 707 X86::EBX, X86::EBP, X86::EDI, X86::ESI 708 }; 709 if (unsigned Reg = State.AllocateReg(RegList1)) { 710 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 711 return false; 712 } 713 } 714 715 return true; // CC didn't match. 716} 717 718 719static bool CC_X86_32_HiPE(unsigned ValNo, MVT ValVT, 720 MVT LocVT, CCValAssign::LocInfo LocInfo, 721 ISD::ArgFlagsTy ArgFlags, CCState &State) { 722 723 if (LocVT == MVT::i8 || 724 LocVT == MVT::i16) { 725 LocVT = MVT::i32; 726 if (ArgFlags.isSExt()) 727 LocInfo = CCValAssign::SExt; 728 else if (ArgFlags.isZExt()) 729 LocInfo = CCValAssign::ZExt; 730 else 731 LocInfo = CCValAssign::AExt; 732 } 733 734 if (LocVT == MVT::i32) { 735 static const MCPhysReg RegList1[] = { 736 X86::ESI, X86::EBP, X86::EAX, X86::EDX, X86::ECX 737 }; 738 if (unsigned Reg = State.AllocateReg(RegList1)) { 739 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 740 return false; 741 } 742 } 743 744 if (LocVT == MVT::i32 || 745 LocVT == MVT::f32) { 746 unsigned Offset2 = State.AllocateStack(4, 4); 747 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); 748 return false; 749 } 750 751 return true; // CC didn't match. 752} 753 754 755static bool CC_X86_32_MCU(unsigned ValNo, MVT ValVT, 756 MVT LocVT, CCValAssign::LocInfo LocInfo, 757 ISD::ArgFlagsTy ArgFlags, CCState &State) { 758 759 if (ArgFlags.isByVal()) { 760 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags); 761 return false; 762 } 763 764 if (LocVT == MVT::i1 || 765 LocVT == MVT::i8 || 766 LocVT == MVT::i16 || 767 LocVT == MVT::v1i1) { 768 LocVT = MVT::i32; 769 if (ArgFlags.isSExt()) 770 LocInfo = CCValAssign::SExt; 771 else if (ArgFlags.isZExt()) 772 LocInfo = CCValAssign::ZExt; 773 else 774 LocInfo = CCValAssign::AExt; 775 } 776 777 if (!State.isVarArg()) { 778 if (LocVT == MVT::i32) { 779 if (CC_X86_32_MCUInReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 780 return false; 781 } 782 } 783 784 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 785 return false; 786 787 return true; // CC didn't match. 788} 789 790 791static bool CC_X86_32_RegCall(unsigned ValNo, MVT ValVT, 792 MVT LocVT, CCValAssign::LocInfo LocInfo, 793 ISD::ArgFlagsTy ArgFlags, CCState &State) { 794 795 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 796 if (ArgFlags.isByVal()) { 797 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); 798 return false; 799 } 800 } 801 802 if (ArgFlags.isByVal()) { 803 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags); 804 return false; 805 } 806 807 if (LocVT == MVT::i1 || 808 LocVT == MVT::i8 || 809 LocVT == MVT::i16 || 810 LocVT == MVT::v1i1) { 811 LocVT = MVT::i32; 812 if (ArgFlags.isSExt()) 813 LocInfo = CCValAssign::SExt; 814 else if (ArgFlags.isZExt()) 815 LocInfo = CCValAssign::ZExt; 816 else 817 LocInfo = CCValAssign::AExt; 818 } 819 820 if (LocVT == MVT::v8i1 || 821 LocVT == MVT::v16i1 || 822 LocVT == MVT::v32i1) { 823 LocVT = MVT::i32; 824 if (ArgFlags.isSExt()) 825 LocInfo = CCValAssign::SExt; 826 else if (ArgFlags.isZExt()) 827 LocInfo = CCValAssign::ZExt; 828 else 829 LocInfo = CCValAssign::AExt; 830 } 831 832 if (LocVT == MVT::i32) { 833 static const MCPhysReg RegList1[] = { 834 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI 835 }; 836 if (unsigned Reg = State.AllocateReg(RegList1)) { 837 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 838 return false; 839 } 840 } 841 842 if (LocVT == MVT::i64) { 843 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 844 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 845 return false; 846 } 847 } 848 849 if (LocVT == MVT::v64i1) { 850 LocVT = MVT::i64; 851 if (ArgFlags.isSExt()) 852 LocInfo = CCValAssign::SExt; 853 else if (ArgFlags.isZExt()) 854 LocInfo = CCValAssign::ZExt; 855 else 856 LocInfo = CCValAssign::AExt; 857 } 858 859 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 860 if (LocVT == MVT::i64) { 861 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 862 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 863 return false; 864 } 865 } 866 } 867 868 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { 869 if (LocVT == MVT::i64) { 870 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 871 return false; 872 } 873 } 874 875 if (LocVT == MVT::f32 || 876 LocVT == MVT::f64 || 877 LocVT == MVT::f128) { 878 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 879 static const MCPhysReg RegList2[] = { 880 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 881 }; 882 if (unsigned Reg = State.AllocateReg(RegList2)) { 883 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 884 return false; 885 } 886 } 887 } 888 889 if (LocVT == MVT::f80) { 890 if (unsigned Reg = State.AllocateReg(X86::FP0)) { 891 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 892 return false; 893 } 894 } 895 896 if (LocVT == MVT::v16i8 || 897 LocVT == MVT::v8i16 || 898 LocVT == MVT::v4i32 || 899 LocVT == MVT::v2i64 || 900 LocVT == MVT::v4f32 || 901 LocVT == MVT::v2f64) { 902 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 903 static const MCPhysReg RegList3[] = { 904 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 905 }; 906 if (unsigned Reg = State.AllocateReg(RegList3)) { 907 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 908 return false; 909 } 910 } 911 } 912 913 if (LocVT == MVT::v32i8 || 914 LocVT == MVT::v16i16 || 915 LocVT == MVT::v8i32 || 916 LocVT == MVT::v4i64 || 917 LocVT == MVT::v8f32 || 918 LocVT == MVT::v4f64) { 919 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 920 static const MCPhysReg RegList4[] = { 921 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7 922 }; 923 if (unsigned Reg = State.AllocateReg(RegList4)) { 924 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 925 return false; 926 } 927 } 928 } 929 930 if (LocVT == MVT::v64i8 || 931 LocVT == MVT::v32i16 || 932 LocVT == MVT::v16i32 || 933 LocVT == MVT::v8i64 || 934 LocVT == MVT::v16f32 || 935 LocVT == MVT::v8f64) { 936 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 937 static const MCPhysReg RegList5[] = { 938 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 939 }; 940 if (unsigned Reg = State.AllocateReg(RegList5)) { 941 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 942 return false; 943 } 944 } 945 } 946 947 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 948 if (LocVT == MVT::i32 || 949 LocVT == MVT::i64 || 950 LocVT == MVT::f32 || 951 LocVT == MVT::f64) { 952 unsigned Offset6 = State.AllocateStack(8, 8); 953 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); 954 return false; 955 } 956 } 957 958 if (LocVT == MVT::i32 || 959 LocVT == MVT::f32) { 960 unsigned Offset7 = State.AllocateStack(4, 4); 961 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo)); 962 return false; 963 } 964 965 if (LocVT == MVT::i64 || 966 LocVT == MVT::f64) { 967 unsigned Offset8 = State.AllocateStack(8, 4); 968 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); 969 return false; 970 } 971 972 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 973 if (LocVT == MVT::x86mmx) { 974 unsigned Offset9 = State.AllocateStack(8, 8); 975 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); 976 return false; 977 } 978 } 979 980 if (LocVT == MVT::x86mmx) { 981 unsigned Offset10 = State.AllocateStack(8, 4); 982 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); 983 return false; 984 } 985 986 if (LocVT == MVT::f80 || 987 LocVT == MVT::f128) { 988 unsigned Offset11 = State.AllocateStack( 989 State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 990 State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext()))); 991 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo)); 992 return false; 993 } 994 995 if (LocVT == MVT::v16i8 || 996 LocVT == MVT::v8i16 || 997 LocVT == MVT::v4i32 || 998 LocVT == MVT::v2i64 || 999 LocVT == MVT::v4f32 || 1000 LocVT == MVT::v2f64) { 1001 unsigned Offset12 = State.AllocateStack(16, 16); 1002 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo)); 1003 return false; 1004 } 1005 1006 if (LocVT == MVT::v32i8 || 1007 LocVT == MVT::v16i16 || 1008 LocVT == MVT::v8i32 || 1009 LocVT == MVT::v4i64 || 1010 LocVT == MVT::v8f32 || 1011 LocVT == MVT::v4f64) { 1012 unsigned Offset13 = State.AllocateStack(32, 32); 1013 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); 1014 return false; 1015 } 1016 1017 if (LocVT == MVT::v64i8 || 1018 LocVT == MVT::v32i16 || 1019 LocVT == MVT::v16i32 || 1020 LocVT == MVT::v8i64 || 1021 LocVT == MVT::v16f32 || 1022 LocVT == MVT::v8f64) { 1023 unsigned Offset14 = State.AllocateStack(64, 64); 1024 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo)); 1025 return false; 1026 } 1027 1028 return true; // CC didn't match. 1029} 1030 1031 1032static bool CC_X86_32_ThisCall(unsigned ValNo, MVT ValVT, 1033 MVT LocVT, CCValAssign::LocInfo LocInfo, 1034 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1035 1036 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetCygMing()) { 1037 if (!CC_X86_32_ThisCall_Mingw(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1038 return false; 1039 } 1040 1041 if (!CC_X86_32_ThisCall_Win(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1042 return false; 1043 1044 return true; // CC didn't match. 1045} 1046 1047 1048static bool CC_X86_32_ThisCall_Common(unsigned ValNo, MVT ValVT, 1049 MVT LocVT, CCValAssign::LocInfo LocInfo, 1050 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1051 1052 if (LocVT == MVT::i32) { 1053 if (unsigned Reg = State.AllocateReg(X86::ECX)) { 1054 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1055 return false; 1056 } 1057 } 1058 1059 if (!CC_X86_32_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1060 return false; 1061 1062 return true; // CC didn't match. 1063} 1064 1065 1066static bool CC_X86_32_ThisCall_Mingw(unsigned ValNo, MVT ValVT, 1067 MVT LocVT, CCValAssign::LocInfo LocInfo, 1068 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1069 1070 if (LocVT == MVT::i1 || 1071 LocVT == MVT::i8 || 1072 LocVT == MVT::i16 || 1073 LocVT == MVT::v1i1) { 1074 LocVT = MVT::i32; 1075 if (ArgFlags.isSExt()) 1076 LocInfo = CCValAssign::SExt; 1077 else if (ArgFlags.isZExt()) 1078 LocInfo = CCValAssign::ZExt; 1079 else 1080 LocInfo = CCValAssign::AExt; 1081 } 1082 1083 if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1084 return false; 1085 1086 return true; // CC didn't match. 1087} 1088 1089 1090static bool CC_X86_32_ThisCall_Win(unsigned ValNo, MVT ValVT, 1091 MVT LocVT, CCValAssign::LocInfo LocInfo, 1092 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1093 1094 if (LocVT == MVT::i1 || 1095 LocVT == MVT::i8 || 1096 LocVT == MVT::i16 || 1097 LocVT == MVT::v1i1) { 1098 LocVT = MVT::i32; 1099 if (ArgFlags.isSExt()) 1100 LocInfo = CCValAssign::SExt; 1101 else if (ArgFlags.isZExt()) 1102 LocInfo = CCValAssign::ZExt; 1103 else 1104 LocInfo = CCValAssign::AExt; 1105 } 1106 1107 if (ArgFlags.isSRet()) { 1108 unsigned Offset1 = State.AllocateStack(4, 4); 1109 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); 1110 return false; 1111 } 1112 1113 if (!CC_X86_32_ThisCall_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1114 return false; 1115 1116 return true; // CC didn't match. 1117} 1118 1119 1120static bool CC_X86_32_Vector_Common(unsigned ValNo, MVT ValVT, 1121 MVT LocVT, CCValAssign::LocInfo LocInfo, 1122 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1123 1124 if (LocVT == MVT::v16i8 || 1125 LocVT == MVT::v8i16 || 1126 LocVT == MVT::v4i32 || 1127 LocVT == MVT::v2i64 || 1128 LocVT == MVT::v4f32 || 1129 LocVT == MVT::v2f64) { 1130 unsigned Offset1 = State.AllocateStack(16, 16); 1131 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); 1132 return false; 1133 } 1134 1135 if (LocVT == MVT::v32i8 || 1136 LocVT == MVT::v16i16 || 1137 LocVT == MVT::v8i32 || 1138 LocVT == MVT::v4i64 || 1139 LocVT == MVT::v8f32 || 1140 LocVT == MVT::v4f64) { 1141 unsigned Offset2 = State.AllocateStack(32, 32); 1142 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); 1143 return false; 1144 } 1145 1146 if (LocVT == MVT::v64i8 || 1147 LocVT == MVT::v32i16 || 1148 LocVT == MVT::v16i32 || 1149 LocVT == MVT::v8i64 || 1150 LocVT == MVT::v16f32 || 1151 LocVT == MVT::v8f64) { 1152 unsigned Offset3 = State.AllocateStack(64, 64); 1153 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); 1154 return false; 1155 } 1156 1157 return true; // CC didn't match. 1158} 1159 1160 1161static bool CC_X86_32_Vector_Darwin(unsigned ValNo, MVT ValVT, 1162 MVT LocVT, CCValAssign::LocInfo LocInfo, 1163 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1164 1165 if (!State.isVarArg()) { 1166 if (LocVT == MVT::v16i8 || 1167 LocVT == MVT::v8i16 || 1168 LocVT == MVT::v4i32 || 1169 LocVT == MVT::v2i64 || 1170 LocVT == MVT::v4f32 || 1171 LocVT == MVT::v2f64) { 1172 static const MCPhysReg RegList1[] = { 1173 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 1174 }; 1175 if (unsigned Reg = State.AllocateReg(RegList1)) { 1176 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1177 return false; 1178 } 1179 } 1180 } 1181 1182 if (!State.isVarArg()) { 1183 if (LocVT == MVT::v32i8 || 1184 LocVT == MVT::v16i16 || 1185 LocVT == MVT::v8i32 || 1186 LocVT == MVT::v4i64 || 1187 LocVT == MVT::v8f32 || 1188 LocVT == MVT::v4f64) { 1189 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 1190 static const MCPhysReg RegList2[] = { 1191 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3 1192 }; 1193 if (unsigned Reg = State.AllocateReg(RegList2)) { 1194 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1195 return false; 1196 } 1197 } 1198 } 1199 } 1200 1201 if (!State.isVarArg()) { 1202 if (LocVT == MVT::v64i8 || 1203 LocVT == MVT::v32i16 || 1204 LocVT == MVT::v16i32 || 1205 LocVT == MVT::v8i64 || 1206 LocVT == MVT::v16f32 || 1207 LocVT == MVT::v8f64) { 1208 static const MCPhysReg RegList3[] = { 1209 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 1210 }; 1211 if (unsigned Reg = State.AllocateReg(RegList3)) { 1212 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1213 return false; 1214 } 1215 } 1216 } 1217 1218 if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1219 return false; 1220 1221 return true; // CC didn't match. 1222} 1223 1224 1225static bool CC_X86_32_Vector_Standard(unsigned ValNo, MVT ValVT, 1226 MVT LocVT, CCValAssign::LocInfo LocInfo, 1227 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1228 1229 if (!State.isVarArg()) { 1230 if (LocVT == MVT::v16i8 || 1231 LocVT == MVT::v8i16 || 1232 LocVT == MVT::v4i32 || 1233 LocVT == MVT::v2i64 || 1234 LocVT == MVT::v4f32 || 1235 LocVT == MVT::v2f64) { 1236 static const MCPhysReg RegList1[] = { 1237 X86::XMM0, X86::XMM1, X86::XMM2 1238 }; 1239 if (unsigned Reg = State.AllocateReg(RegList1)) { 1240 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1241 return false; 1242 } 1243 } 1244 } 1245 1246 if (!State.isVarArg()) { 1247 if (LocVT == MVT::v32i8 || 1248 LocVT == MVT::v16i16 || 1249 LocVT == MVT::v8i32 || 1250 LocVT == MVT::v4i64 || 1251 LocVT == MVT::v8f32 || 1252 LocVT == MVT::v4f64) { 1253 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 1254 static const MCPhysReg RegList2[] = { 1255 X86::YMM0, X86::YMM1, X86::YMM2 1256 }; 1257 if (unsigned Reg = State.AllocateReg(RegList2)) { 1258 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1259 return false; 1260 } 1261 } 1262 } 1263 } 1264 1265 if (!State.isVarArg()) { 1266 if (LocVT == MVT::v64i8 || 1267 LocVT == MVT::v32i16 || 1268 LocVT == MVT::v16i32 || 1269 LocVT == MVT::v8i64 || 1270 LocVT == MVT::v16f32 || 1271 LocVT == MVT::v8f64) { 1272 static const MCPhysReg RegList3[] = { 1273 X86::ZMM0, X86::ZMM1, X86::ZMM2 1274 }; 1275 if (unsigned Reg = State.AllocateReg(RegList3)) { 1276 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1277 return false; 1278 } 1279 } 1280 } 1281 1282 if (!CC_X86_32_Vector_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1283 return false; 1284 1285 return true; // CC didn't match. 1286} 1287 1288 1289static bool CC_X86_64(unsigned ValNo, MVT ValVT, 1290 MVT LocVT, CCValAssign::LocInfo LocInfo, 1291 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1292 1293 if (State.getCallingConv() == CallingConv::GHC) { 1294 if (!CC_X86_64_GHC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1295 return false; 1296 } 1297 1298 if (State.getCallingConv() == CallingConv::HiPE) { 1299 if (!CC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1300 return false; 1301 } 1302 1303 if (State.getCallingConv() == CallingConv::WebKit_JS) { 1304 if (!CC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1305 return false; 1306 } 1307 1308 if (State.getCallingConv() == CallingConv::AnyReg) { 1309 if (!CC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1310 return false; 1311 } 1312 1313 if (State.getCallingConv() == CallingConv::Win64) { 1314 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1315 return false; 1316 } 1317 1318 if (State.getCallingConv() == CallingConv::X86_64_SysV) { 1319 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1320 return false; 1321 } 1322 1323 if (State.getCallingConv() == CallingConv::X86_VectorCall) { 1324 if (!CC_X86_Win64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1325 return false; 1326 } 1327 1328 if (State.getCallingConv() == CallingConv::HHVM) { 1329 if (!CC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1330 return false; 1331 } 1332 1333 if (State.getCallingConv() == CallingConv::HHVM_C) { 1334 if (!CC_X86_64_HHVM_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1335 return false; 1336 } 1337 1338 if (State.getCallingConv() == CallingConv::X86_RegCall) { 1339 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 1340 if (!CC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1341 return false; 1342 } 1343 } 1344 1345 if (State.getCallingConv() == CallingConv::X86_RegCall) { 1346 if (!CC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1347 return false; 1348 } 1349 1350 if (State.getCallingConv() == CallingConv::X86_INTR) { 1351 if (CC_X86_Intr(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1352 return false; 1353 } 1354 1355 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 1356 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1357 return false; 1358 } 1359 1360 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1361 return false; 1362 1363 return true; // CC didn't match. 1364} 1365 1366 1367static bool CC_X86_64_AnyReg(unsigned ValNo, MVT ValVT, 1368 MVT LocVT, CCValAssign::LocInfo LocInfo, 1369 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1370 1371 if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1372 return false; 1373 1374 return true; // CC didn't match. 1375} 1376 1377 1378static bool CC_X86_64_C(unsigned ValNo, MVT ValVT, 1379 MVT LocVT, CCValAssign::LocInfo LocInfo, 1380 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1381 1382 if (ArgFlags.isByVal()) { 1383 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); 1384 return false; 1385 } 1386 1387 if (LocVT == MVT::i1 || 1388 LocVT == MVT::i8 || 1389 LocVT == MVT::i16 || 1390 LocVT == MVT::v1i1) { 1391 LocVT = MVT::i32; 1392 if (ArgFlags.isSExt()) 1393 LocInfo = CCValAssign::SExt; 1394 else if (ArgFlags.isZExt()) 1395 LocInfo = CCValAssign::ZExt; 1396 else 1397 LocInfo = CCValAssign::AExt; 1398 } 1399 1400 if (ArgFlags.isNest()) { 1401 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTarget64BitILP32()) { 1402 if (unsigned Reg = State.AllocateReg(X86::R10D)) { 1403 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1404 return false; 1405 } 1406 } 1407 } 1408 1409 if (ArgFlags.isNest()) { 1410 if (unsigned Reg = State.AllocateReg(X86::R10)) { 1411 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1412 return false; 1413 } 1414 } 1415 1416 if (ArgFlags.isSwiftSelf()) { 1417 if (LocVT == MVT::i64) { 1418 if (unsigned Reg = State.AllocateReg(X86::R13)) { 1419 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1420 return false; 1421 } 1422 } 1423 } 1424 1425 if (ArgFlags.isSwiftError()) { 1426 if (LocVT == MVT::i64) { 1427 if (unsigned Reg = State.AllocateReg(X86::R12)) { 1428 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1429 return false; 1430 } 1431 } 1432 } 1433 1434 if (State.getCallingConv() == CallingConv::Swift) { 1435 if (ArgFlags.isSRet()) { 1436 if (LocVT == MVT::i64) { 1437 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 1438 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1439 return false; 1440 } 1441 } 1442 } 1443 } 1444 1445 if (LocVT == MVT::i32) { 1446 static const MCPhysReg RegList1[] = { 1447 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D 1448 }; 1449 if (unsigned Reg = State.AllocateReg(RegList1)) { 1450 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1451 return false; 1452 } 1453 } 1454 1455 if (LocVT == MVT::i64) { 1456 static const MCPhysReg RegList2[] = { 1457 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1458 }; 1459 if (unsigned Reg = State.AllocateReg(RegList2)) { 1460 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1461 return false; 1462 } 1463 } 1464 1465 if (LocVT == MVT::x86mmx) { 1466 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetDarwin()) { 1467 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { 1468 LocVT = MVT::v2i64; 1469 if (ArgFlags.isSExt()) 1470 LocInfo = CCValAssign::SExt; 1471 else if (ArgFlags.isZExt()) 1472 LocInfo = CCValAssign::ZExt; 1473 else 1474 LocInfo = CCValAssign::AExt; 1475 } 1476 } 1477 } 1478 1479 if (LocVT == MVT::v2i1) { 1480 LocVT = MVT::v2i64; 1481 if (ArgFlags.isSExt()) 1482 LocInfo = CCValAssign::SExt; 1483 else if (ArgFlags.isZExt()) 1484 LocInfo = CCValAssign::ZExt; 1485 else 1486 LocInfo = CCValAssign::AExt; 1487 } 1488 1489 if (LocVT == MVT::v4i1) { 1490 LocVT = MVT::v4i32; 1491 if (ArgFlags.isSExt()) 1492 LocInfo = CCValAssign::SExt; 1493 else if (ArgFlags.isZExt()) 1494 LocInfo = CCValAssign::ZExt; 1495 else 1496 LocInfo = CCValAssign::AExt; 1497 } 1498 1499 if (LocVT == MVT::v8i1) { 1500 LocVT = MVT::v8i16; 1501 if (ArgFlags.isSExt()) 1502 LocInfo = CCValAssign::SExt; 1503 else if (ArgFlags.isZExt()) 1504 LocInfo = CCValAssign::ZExt; 1505 else 1506 LocInfo = CCValAssign::AExt; 1507 } 1508 1509 if (LocVT == MVT::v16i1) { 1510 LocVT = MVT::v16i8; 1511 if (ArgFlags.isSExt()) 1512 LocInfo = CCValAssign::SExt; 1513 else if (ArgFlags.isZExt()) 1514 LocInfo = CCValAssign::ZExt; 1515 else 1516 LocInfo = CCValAssign::AExt; 1517 } 1518 1519 if (LocVT == MVT::v32i1) { 1520 LocVT = MVT::v32i8; 1521 if (ArgFlags.isSExt()) 1522 LocInfo = CCValAssign::SExt; 1523 else if (ArgFlags.isZExt()) 1524 LocInfo = CCValAssign::ZExt; 1525 else 1526 LocInfo = CCValAssign::AExt; 1527 } 1528 1529 if (LocVT == MVT::v64i1) { 1530 LocVT = MVT::v64i8; 1531 if (ArgFlags.isSExt()) 1532 LocInfo = CCValAssign::SExt; 1533 else if (ArgFlags.isZExt()) 1534 LocInfo = CCValAssign::ZExt; 1535 else 1536 LocInfo = CCValAssign::AExt; 1537 } 1538 1539 if (LocVT == MVT::f32 || 1540 LocVT == MVT::f64 || 1541 LocVT == MVT::f128 || 1542 LocVT == MVT::v16i8 || 1543 LocVT == MVT::v8i16 || 1544 LocVT == MVT::v4i32 || 1545 LocVT == MVT::v2i64 || 1546 LocVT == MVT::v4f32 || 1547 LocVT == MVT::v2f64) { 1548 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 1549 static const MCPhysReg RegList3[] = { 1550 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1551 }; 1552 if (unsigned Reg = State.AllocateReg(RegList3)) { 1553 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1554 return false; 1555 } 1556 } 1557 } 1558 1559 if (!State.isVarArg()) { 1560 if (LocVT == MVT::v32i8 || 1561 LocVT == MVT::v16i16 || 1562 LocVT == MVT::v8i32 || 1563 LocVT == MVT::v4i64 || 1564 LocVT == MVT::v8f32 || 1565 LocVT == MVT::v4f64) { 1566 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 1567 static const MCPhysReg RegList4[] = { 1568 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7 1569 }; 1570 if (unsigned Reg = State.AllocateReg(RegList4)) { 1571 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1572 return false; 1573 } 1574 } 1575 } 1576 } 1577 1578 if (!State.isVarArg()) { 1579 if (LocVT == MVT::v64i8 || 1580 LocVT == MVT::v32i16 || 1581 LocVT == MVT::v16i32 || 1582 LocVT == MVT::v8i64 || 1583 LocVT == MVT::v16f32 || 1584 LocVT == MVT::v8f64) { 1585 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 1586 static const MCPhysReg RegList5[] = { 1587 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 1588 }; 1589 if (unsigned Reg = State.AllocateReg(RegList5)) { 1590 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1591 return false; 1592 } 1593 } 1594 } 1595 } 1596 1597 if (LocVT == MVT::i32 || 1598 LocVT == MVT::i64 || 1599 LocVT == MVT::f32 || 1600 LocVT == MVT::f64) { 1601 unsigned Offset6 = State.AllocateStack(8, 8); 1602 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); 1603 return false; 1604 } 1605 1606 if (LocVT == MVT::f80 || 1607 LocVT == MVT::f128) { 1608 unsigned Offset7 = State.AllocateStack( 1609 State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 1610 State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext()))); 1611 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo)); 1612 return false; 1613 } 1614 1615 if (LocVT == MVT::v16i8 || 1616 LocVT == MVT::v8i16 || 1617 LocVT == MVT::v4i32 || 1618 LocVT == MVT::v2i64 || 1619 LocVT == MVT::v4f32 || 1620 LocVT == MVT::v2f64) { 1621 unsigned Offset8 = State.AllocateStack(16, 16); 1622 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); 1623 return false; 1624 } 1625 1626 if (LocVT == MVT::v32i8 || 1627 LocVT == MVT::v16i16 || 1628 LocVT == MVT::v8i32 || 1629 LocVT == MVT::v4i64 || 1630 LocVT == MVT::v8f32 || 1631 LocVT == MVT::v4f64) { 1632 unsigned Offset9 = State.AllocateStack(32, 32); 1633 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); 1634 return false; 1635 } 1636 1637 if (LocVT == MVT::v64i8 || 1638 LocVT == MVT::v32i16 || 1639 LocVT == MVT::v16i32 || 1640 LocVT == MVT::v8i64 || 1641 LocVT == MVT::v16f32 || 1642 LocVT == MVT::v8f64) { 1643 unsigned Offset10 = State.AllocateStack(64, 64); 1644 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); 1645 return false; 1646 } 1647 1648 return true; // CC didn't match. 1649} 1650 1651 1652static bool CC_X86_64_GHC(unsigned ValNo, MVT ValVT, 1653 MVT LocVT, CCValAssign::LocInfo LocInfo, 1654 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1655 1656 if (LocVT == MVT::i8 || 1657 LocVT == MVT::i16 || 1658 LocVT == MVT::i32) { 1659 LocVT = MVT::i64; 1660 if (ArgFlags.isSExt()) 1661 LocInfo = CCValAssign::SExt; 1662 else if (ArgFlags.isZExt()) 1663 LocInfo = CCValAssign::ZExt; 1664 else 1665 LocInfo = CCValAssign::AExt; 1666 } 1667 1668 if (LocVT == MVT::i64) { 1669 static const MCPhysReg RegList1[] = { 1670 X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15 1671 }; 1672 if (unsigned Reg = State.AllocateReg(RegList1)) { 1673 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1674 return false; 1675 } 1676 } 1677 1678 if (LocVT == MVT::f32 || 1679 LocVT == MVT::f64 || 1680 LocVT == MVT::v16i8 || 1681 LocVT == MVT::v8i16 || 1682 LocVT == MVT::v4i32 || 1683 LocVT == MVT::v2i64 || 1684 LocVT == MVT::v4f32 || 1685 LocVT == MVT::v2f64) { 1686 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 1687 static const MCPhysReg RegList2[] = { 1688 X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6 1689 }; 1690 if (unsigned Reg = State.AllocateReg(RegList2)) { 1691 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1692 return false; 1693 } 1694 } 1695 } 1696 1697 if (LocVT == MVT::v32i8 || 1698 LocVT == MVT::v16i16 || 1699 LocVT == MVT::v8i32 || 1700 LocVT == MVT::v4i64 || 1701 LocVT == MVT::v8f32 || 1702 LocVT == MVT::v4f64) { 1703 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 1704 static const MCPhysReg RegList3[] = { 1705 X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6 1706 }; 1707 if (unsigned Reg = State.AllocateReg(RegList3)) { 1708 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1709 return false; 1710 } 1711 } 1712 } 1713 1714 if (LocVT == MVT::v64i8 || 1715 LocVT == MVT::v32i16 || 1716 LocVT == MVT::v16i32 || 1717 LocVT == MVT::v8i64 || 1718 LocVT == MVT::v16f32 || 1719 LocVT == MVT::v8f64) { 1720 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 1721 static const MCPhysReg RegList4[] = { 1722 X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6 1723 }; 1724 if (unsigned Reg = State.AllocateReg(RegList4)) { 1725 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1726 return false; 1727 } 1728 } 1729 } 1730 1731 return true; // CC didn't match. 1732} 1733 1734 1735static bool CC_X86_64_HHVM(unsigned ValNo, MVT ValVT, 1736 MVT LocVT, CCValAssign::LocInfo LocInfo, 1737 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1738 1739 if (LocVT == MVT::i64) { 1740 static const MCPhysReg RegList1[] = { 1741 X86::RBX, X86::R12, X86::RBP, X86::R15, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14 1742 }; 1743 if (unsigned Reg = State.AllocateReg(RegList1)) { 1744 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1745 return false; 1746 } 1747 } 1748 1749 return true; // CC didn't match. 1750} 1751 1752 1753static bool CC_X86_64_HHVM_C(unsigned ValNo, MVT ValVT, 1754 MVT LocVT, CCValAssign::LocInfo LocInfo, 1755 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1756 1757 if (LocVT == MVT::i64) { 1758 if (unsigned Reg = State.AllocateReg(X86::RBP)) { 1759 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1760 return false; 1761 } 1762 } 1763 1764 if (!CC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1765 return false; 1766 1767 return true; // CC didn't match. 1768} 1769 1770 1771static bool CC_X86_64_HiPE(unsigned ValNo, MVT ValVT, 1772 MVT LocVT, CCValAssign::LocInfo LocInfo, 1773 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1774 1775 if (LocVT == MVT::i8 || 1776 LocVT == MVT::i16 || 1777 LocVT == MVT::i32) { 1778 LocVT = MVT::i64; 1779 if (ArgFlags.isSExt()) 1780 LocInfo = CCValAssign::SExt; 1781 else if (ArgFlags.isZExt()) 1782 LocInfo = CCValAssign::ZExt; 1783 else 1784 LocInfo = CCValAssign::AExt; 1785 } 1786 1787 if (LocVT == MVT::i64) { 1788 static const MCPhysReg RegList1[] = { 1789 X86::R15, X86::RBP, X86::RSI, X86::RDX, X86::RCX, X86::R8 1790 }; 1791 if (unsigned Reg = State.AllocateReg(RegList1)) { 1792 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1793 return false; 1794 } 1795 } 1796 1797 if (LocVT == MVT::i32 || 1798 LocVT == MVT::i64 || 1799 LocVT == MVT::f32 || 1800 LocVT == MVT::f64) { 1801 unsigned Offset2 = State.AllocateStack(8, 8); 1802 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); 1803 return false; 1804 } 1805 1806 return true; // CC didn't match. 1807} 1808 1809 1810static bool CC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT, 1811 MVT LocVT, CCValAssign::LocInfo LocInfo, 1812 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1813 1814 if (LocVT == MVT::i8 || 1815 LocVT == MVT::i16) { 1816 LocVT = MVT::i32; 1817 if (ArgFlags.isSExt()) 1818 LocInfo = CCValAssign::SExt; 1819 else if (ArgFlags.isZExt()) 1820 LocInfo = CCValAssign::ZExt; 1821 else 1822 LocInfo = CCValAssign::AExt; 1823 } 1824 1825 if (LocVT == MVT::i32) { 1826 if (unsigned Reg = State.AllocateReg(X86::EAX)) { 1827 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1828 return false; 1829 } 1830 } 1831 1832 if (LocVT == MVT::i64) { 1833 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 1834 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1835 return false; 1836 } 1837 } 1838 1839 if (LocVT == MVT::i32 || 1840 LocVT == MVT::f32) { 1841 unsigned Offset1 = State.AllocateStack(4, 4); 1842 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); 1843 return false; 1844 } 1845 1846 if (LocVT == MVT::i64 || 1847 LocVT == MVT::f64) { 1848 unsigned Offset2 = State.AllocateStack(8, 8); 1849 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); 1850 return false; 1851 } 1852 1853 return true; // CC didn't match. 1854} 1855 1856 1857static bool CC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT, 1858 MVT LocVT, CCValAssign::LocInfo LocInfo, 1859 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1860 1861 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 1862 if (ArgFlags.isByVal()) { 1863 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); 1864 return false; 1865 } 1866 } 1867 1868 if (ArgFlags.isByVal()) { 1869 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags); 1870 return false; 1871 } 1872 1873 if (LocVT == MVT::i1 || 1874 LocVT == MVT::i8 || 1875 LocVT == MVT::i16 || 1876 LocVT == MVT::v1i1) { 1877 LocVT = MVT::i32; 1878 if (ArgFlags.isSExt()) 1879 LocInfo = CCValAssign::SExt; 1880 else if (ArgFlags.isZExt()) 1881 LocInfo = CCValAssign::ZExt; 1882 else 1883 LocInfo = CCValAssign::AExt; 1884 } 1885 1886 if (LocVT == MVT::v8i1 || 1887 LocVT == MVT::v16i1 || 1888 LocVT == MVT::v32i1) { 1889 LocVT = MVT::i32; 1890 if (ArgFlags.isSExt()) 1891 LocInfo = CCValAssign::SExt; 1892 else if (ArgFlags.isZExt()) 1893 LocInfo = CCValAssign::ZExt; 1894 else 1895 LocInfo = CCValAssign::AExt; 1896 } 1897 1898 if (LocVT == MVT::i32) { 1899 static const MCPhysReg RegList1[] = { 1900 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D 1901 }; 1902 if (unsigned Reg = State.AllocateReg(RegList1)) { 1903 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1904 return false; 1905 } 1906 } 1907 1908 if (LocVT == MVT::i64) { 1909 static const MCPhysReg RegList2[] = { 1910 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15 1911 }; 1912 if (unsigned Reg = State.AllocateReg(RegList2)) { 1913 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1914 return false; 1915 } 1916 } 1917 1918 if (LocVT == MVT::v64i1) { 1919 LocVT = MVT::i64; 1920 if (ArgFlags.isSExt()) 1921 LocInfo = CCValAssign::SExt; 1922 else if (ArgFlags.isZExt()) 1923 LocInfo = CCValAssign::ZExt; 1924 else 1925 LocInfo = CCValAssign::AExt; 1926 } 1927 1928 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 1929 if (LocVT == MVT::i64) { 1930 static const MCPhysReg RegList3[] = { 1931 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15 1932 }; 1933 if (unsigned Reg = State.AllocateReg(RegList3)) { 1934 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1935 return false; 1936 } 1937 } 1938 } 1939 1940 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { 1941 if (LocVT == MVT::i64) { 1942 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 1943 return false; 1944 } 1945 } 1946 1947 if (LocVT == MVT::f32 || 1948 LocVT == MVT::f64 || 1949 LocVT == MVT::f128) { 1950 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 1951 static const MCPhysReg RegList4[] = { 1952 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 1953 }; 1954 if (unsigned Reg = State.AllocateReg(RegList4)) { 1955 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1956 return false; 1957 } 1958 } 1959 } 1960 1961 if (LocVT == MVT::f80) { 1962 if (unsigned Reg = State.AllocateReg(X86::FP0)) { 1963 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1964 return false; 1965 } 1966 } 1967 1968 if (LocVT == MVT::v16i8 || 1969 LocVT == MVT::v8i16 || 1970 LocVT == MVT::v4i32 || 1971 LocVT == MVT::v2i64 || 1972 LocVT == MVT::v4f32 || 1973 LocVT == MVT::v2f64) { 1974 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 1975 static const MCPhysReg RegList5[] = { 1976 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 1977 }; 1978 if (unsigned Reg = State.AllocateReg(RegList5)) { 1979 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1980 return false; 1981 } 1982 } 1983 } 1984 1985 if (LocVT == MVT::v32i8 || 1986 LocVT == MVT::v16i16 || 1987 LocVT == MVT::v8i32 || 1988 LocVT == MVT::v4i64 || 1989 LocVT == MVT::v8f32 || 1990 LocVT == MVT::v4f64) { 1991 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 1992 static const MCPhysReg RegList6[] = { 1993 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 1994 }; 1995 if (unsigned Reg = State.AllocateReg(RegList6)) { 1996 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1997 return false; 1998 } 1999 } 2000 } 2001 2002 if (LocVT == MVT::v64i8 || 2003 LocVT == MVT::v32i16 || 2004 LocVT == MVT::v16i32 || 2005 LocVT == MVT::v8i64 || 2006 LocVT == MVT::v16f32 || 2007 LocVT == MVT::v8f64) { 2008 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 2009 static const MCPhysReg RegList7[] = { 2010 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15 2011 }; 2012 if (unsigned Reg = State.AllocateReg(RegList7)) { 2013 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2014 return false; 2015 } 2016 } 2017 } 2018 2019 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 2020 if (LocVT == MVT::i32 || 2021 LocVT == MVT::i64 || 2022 LocVT == MVT::f32 || 2023 LocVT == MVT::f64) { 2024 unsigned Offset8 = State.AllocateStack(8, 8); 2025 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); 2026 return false; 2027 } 2028 } 2029 2030 if (LocVT == MVT::i32 || 2031 LocVT == MVT::f32) { 2032 unsigned Offset9 = State.AllocateStack(4, 4); 2033 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); 2034 return false; 2035 } 2036 2037 if (LocVT == MVT::i64 || 2038 LocVT == MVT::f64) { 2039 unsigned Offset10 = State.AllocateStack(8, 4); 2040 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); 2041 return false; 2042 } 2043 2044 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 2045 if (LocVT == MVT::x86mmx) { 2046 unsigned Offset11 = State.AllocateStack(8, 8); 2047 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo)); 2048 return false; 2049 } 2050 } 2051 2052 if (LocVT == MVT::x86mmx) { 2053 unsigned Offset12 = State.AllocateStack(8, 4); 2054 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo)); 2055 return false; 2056 } 2057 2058 if (LocVT == MVT::f80 || 2059 LocVT == MVT::f128) { 2060 unsigned Offset13 = State.AllocateStack( 2061 State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 2062 State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext()))); 2063 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); 2064 return false; 2065 } 2066 2067 if (LocVT == MVT::v16i8 || 2068 LocVT == MVT::v8i16 || 2069 LocVT == MVT::v4i32 || 2070 LocVT == MVT::v2i64 || 2071 LocVT == MVT::v4f32 || 2072 LocVT == MVT::v2f64) { 2073 unsigned Offset14 = State.AllocateStack(16, 16); 2074 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo)); 2075 return false; 2076 } 2077 2078 if (LocVT == MVT::v32i8 || 2079 LocVT == MVT::v16i16 || 2080 LocVT == MVT::v8i32 || 2081 LocVT == MVT::v4i64 || 2082 LocVT == MVT::v8f32 || 2083 LocVT == MVT::v4f64) { 2084 unsigned Offset15 = State.AllocateStack(32, 32); 2085 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo)); 2086 return false; 2087 } 2088 2089 if (LocVT == MVT::v64i8 || 2090 LocVT == MVT::v32i16 || 2091 LocVT == MVT::v16i32 || 2092 LocVT == MVT::v8i64 || 2093 LocVT == MVT::v16f32 || 2094 LocVT == MVT::v8f64) { 2095 unsigned Offset16 = State.AllocateStack(64, 64); 2096 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo)); 2097 return false; 2098 } 2099 2100 return true; // CC didn't match. 2101} 2102 2103 2104static bool CC_X86_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT, 2105 MVT LocVT, CCValAssign::LocInfo LocInfo, 2106 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2107 2108 if (LocVT == MVT::i32) { 2109 if (unsigned Reg = State.AllocateReg(X86::ECX)) { 2110 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2111 return false; 2112 } 2113 } 2114 2115 return true; // CC didn't match. 2116} 2117 2118 2119static bool CC_X86_Win32_VectorCall(unsigned ValNo, MVT ValVT, 2120 MVT LocVT, CCValAssign::LocInfo LocInfo, 2121 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2122 2123 if (CC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2124 return false; 2125 2126 if (!CC_X86_32_FastCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2127 return false; 2128 2129 return true; // CC didn't match. 2130} 2131 2132 2133static bool CC_X86_Win64_C(unsigned ValNo, MVT ValVT, 2134 MVT LocVT, CCValAssign::LocInfo LocInfo, 2135 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2136 2137 if (ArgFlags.isByVal()) { 2138 LocVT = MVT::i64; 2139 LocInfo = CCValAssign::Indirect; 2140 } 2141 2142 if (LocVT == MVT::i1 || 2143 LocVT == MVT::v1i1) { 2144 LocVT = MVT::i8; 2145 if (ArgFlags.isSExt()) 2146 LocInfo = CCValAssign::SExt; 2147 else if (ArgFlags.isZExt()) 2148 LocInfo = CCValAssign::ZExt; 2149 else 2150 LocInfo = CCValAssign::AExt; 2151 } 2152 2153 if (ArgFlags.isNest()) { 2154 if (unsigned Reg = State.AllocateReg(X86::R10)) { 2155 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2156 return false; 2157 } 2158 } 2159 2160 if (ArgFlags.isSwiftError()) { 2161 if (LocVT == MVT::i64) { 2162 if (unsigned Reg = State.AllocateReg(X86::R12)) { 2163 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2164 return false; 2165 } 2166 } 2167 } 2168 2169 if (ArgFlags.isCFGuardTarget()) { 2170 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 2171 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2172 return false; 2173 } 2174 } 2175 2176 if (LocVT == MVT::v16i8 || 2177 LocVT == MVT::v8i16 || 2178 LocVT == MVT::v4i32 || 2179 LocVT == MVT::v2i64 || 2180 LocVT == MVT::v4f32 || 2181 LocVT == MVT::v2f64) { 2182 LocVT = MVT::i64; 2183 LocInfo = CCValAssign::Indirect; 2184 } 2185 2186 if (LocVT == MVT::v32i8 || 2187 LocVT == MVT::v16i16 || 2188 LocVT == MVT::v8i32 || 2189 LocVT == MVT::v4i64 || 2190 LocVT == MVT::v8f32 || 2191 LocVT == MVT::v4f64) { 2192 LocVT = MVT::i64; 2193 LocInfo = CCValAssign::Indirect; 2194 } 2195 2196 if (LocVT == MVT::v64i8 || 2197 LocVT == MVT::v32i16 || 2198 LocVT == MVT::v16i32 || 2199 LocVT == MVT::v16f32 || 2200 LocVT == MVT::v8f64 || 2201 LocVT == MVT::v8i64) { 2202 LocVT = MVT::i64; 2203 LocInfo = CCValAssign::Indirect; 2204 } 2205 2206 if (LocVT == MVT::f80) { 2207 LocVT = MVT::i64; 2208 LocInfo = CCValAssign::Indirect; 2209 } 2210 2211 if (LocVT == MVT::x86mmx) { 2212 LocVT = MVT::i64; 2213 LocInfo = CCValAssign::BCvt; 2214 } 2215 2216 if (LocVT == MVT::f32) { 2217 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 2218 LocVT = MVT::i32; 2219 LocInfo = CCValAssign::BCvt; 2220 } 2221 } 2222 2223 if (LocVT == MVT::f64) { 2224 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 2225 LocVT = MVT::i64; 2226 LocInfo = CCValAssign::BCvt; 2227 } 2228 } 2229 2230 if (LocVT == MVT::f32 || 2231 LocVT == MVT::f64) { 2232 static const MCPhysReg RegList1[] = { 2233 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 2234 }; 2235 static const MCPhysReg RegList2[] = { 2236 X86::RCX, X86::RDX, X86::R8, X86::R9 2237 }; 2238 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { 2239 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2240 return false; 2241 } 2242 } 2243 2244 if (LocVT == MVT::i8) { 2245 static const MCPhysReg RegList3[] = { 2246 X86::CL, X86::DL, X86::R8B, X86::R9B 2247 }; 2248 static const MCPhysReg RegList4[] = { 2249 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 2250 }; 2251 if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) { 2252 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2253 return false; 2254 } 2255 } 2256 2257 if (LocVT == MVT::i16) { 2258 static const MCPhysReg RegList5[] = { 2259 X86::CX, X86::DX, X86::R8W, X86::R9W 2260 }; 2261 static const MCPhysReg RegList6[] = { 2262 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 2263 }; 2264 if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) { 2265 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2266 return false; 2267 } 2268 } 2269 2270 if (LocVT == MVT::i32) { 2271 static const MCPhysReg RegList7[] = { 2272 X86::ECX, X86::EDX, X86::R8D, X86::R9D 2273 }; 2274 static const MCPhysReg RegList8[] = { 2275 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 2276 }; 2277 if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) { 2278 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2279 return false; 2280 } 2281 } 2282 2283 if (State.getCallingConv() == CallingConv::X86_ThisCall) { 2284 if (ArgFlags.isSRet()) { 2285 if (LocVT == MVT::i64) { 2286 static const MCPhysReg RegList9[] = { 2287 X86::RDX, X86::R8, X86::R9 2288 }; 2289 static const MCPhysReg RegList10[] = { 2290 X86::XMM1, X86::XMM2, X86::XMM3 2291 }; 2292 if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) { 2293 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2294 return false; 2295 } 2296 } 2297 } 2298 } 2299 2300 if (LocVT == MVT::i64) { 2301 static const MCPhysReg RegList11[] = { 2302 X86::RCX, X86::RDX, X86::R8, X86::R9 2303 }; 2304 static const MCPhysReg RegList12[] = { 2305 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 2306 }; 2307 if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) { 2308 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2309 return false; 2310 } 2311 } 2312 2313 if (LocVT == MVT::i8 || 2314 LocVT == MVT::i16 || 2315 LocVT == MVT::i32 || 2316 LocVT == MVT::i64 || 2317 LocVT == MVT::f32 || 2318 LocVT == MVT::f64) { 2319 unsigned Offset13 = State.AllocateStack(8, 8); 2320 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); 2321 return false; 2322 } 2323 2324 return true; // CC didn't match. 2325} 2326 2327 2328static bool CC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT, 2329 MVT LocVT, CCValAssign::LocInfo LocInfo, 2330 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2331 2332 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 2333 if (ArgFlags.isByVal()) { 2334 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags); 2335 return false; 2336 } 2337 } 2338 2339 if (ArgFlags.isByVal()) { 2340 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags); 2341 return false; 2342 } 2343 2344 if (LocVT == MVT::i1 || 2345 LocVT == MVT::i8 || 2346 LocVT == MVT::i16 || 2347 LocVT == MVT::v1i1) { 2348 LocVT = MVT::i32; 2349 if (ArgFlags.isSExt()) 2350 LocInfo = CCValAssign::SExt; 2351 else if (ArgFlags.isZExt()) 2352 LocInfo = CCValAssign::ZExt; 2353 else 2354 LocInfo = CCValAssign::AExt; 2355 } 2356 2357 if (LocVT == MVT::v8i1 || 2358 LocVT == MVT::v16i1 || 2359 LocVT == MVT::v32i1) { 2360 LocVT = MVT::i32; 2361 if (ArgFlags.isSExt()) 2362 LocInfo = CCValAssign::SExt; 2363 else if (ArgFlags.isZExt()) 2364 LocInfo = CCValAssign::ZExt; 2365 else 2366 LocInfo = CCValAssign::AExt; 2367 } 2368 2369 if (LocVT == MVT::i32) { 2370 static const MCPhysReg RegList1[] = { 2371 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D 2372 }; 2373 if (unsigned Reg = State.AllocateReg(RegList1)) { 2374 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2375 return false; 2376 } 2377 } 2378 2379 if (LocVT == MVT::i64) { 2380 static const MCPhysReg RegList2[] = { 2381 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15 2382 }; 2383 if (unsigned Reg = State.AllocateReg(RegList2)) { 2384 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2385 return false; 2386 } 2387 } 2388 2389 if (LocVT == MVT::v64i1) { 2390 LocVT = MVT::i64; 2391 if (ArgFlags.isSExt()) 2392 LocInfo = CCValAssign::SExt; 2393 else if (ArgFlags.isZExt()) 2394 LocInfo = CCValAssign::ZExt; 2395 else 2396 LocInfo = CCValAssign::AExt; 2397 } 2398 2399 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 2400 if (LocVT == MVT::i64) { 2401 static const MCPhysReg RegList3[] = { 2402 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15 2403 }; 2404 if (unsigned Reg = State.AllocateReg(RegList3)) { 2405 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2406 return false; 2407 } 2408 } 2409 } 2410 2411 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { 2412 if (LocVT == MVT::i64) { 2413 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2414 return false; 2415 } 2416 } 2417 2418 if (LocVT == MVT::f32 || 2419 LocVT == MVT::f64 || 2420 LocVT == MVT::f128) { 2421 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 2422 static const MCPhysReg RegList4[] = { 2423 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 2424 }; 2425 if (unsigned Reg = State.AllocateReg(RegList4)) { 2426 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2427 return false; 2428 } 2429 } 2430 } 2431 2432 if (LocVT == MVT::f80) { 2433 if (unsigned Reg = State.AllocateReg(X86::FP0)) { 2434 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2435 return false; 2436 } 2437 } 2438 2439 if (LocVT == MVT::v16i8 || 2440 LocVT == MVT::v8i16 || 2441 LocVT == MVT::v4i32 || 2442 LocVT == MVT::v2i64 || 2443 LocVT == MVT::v4f32 || 2444 LocVT == MVT::v2f64) { 2445 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 2446 static const MCPhysReg RegList5[] = { 2447 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 2448 }; 2449 if (unsigned Reg = State.AllocateReg(RegList5)) { 2450 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2451 return false; 2452 } 2453 } 2454 } 2455 2456 if (LocVT == MVT::v32i8 || 2457 LocVT == MVT::v16i16 || 2458 LocVT == MVT::v8i32 || 2459 LocVT == MVT::v4i64 || 2460 LocVT == MVT::v8f32 || 2461 LocVT == MVT::v4f64) { 2462 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 2463 static const MCPhysReg RegList6[] = { 2464 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 2465 }; 2466 if (unsigned Reg = State.AllocateReg(RegList6)) { 2467 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2468 return false; 2469 } 2470 } 2471 } 2472 2473 if (LocVT == MVT::v64i8 || 2474 LocVT == MVT::v32i16 || 2475 LocVT == MVT::v16i32 || 2476 LocVT == MVT::v8i64 || 2477 LocVT == MVT::v16f32 || 2478 LocVT == MVT::v8f64) { 2479 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 2480 static const MCPhysReg RegList7[] = { 2481 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15 2482 }; 2483 if (unsigned Reg = State.AllocateReg(RegList7)) { 2484 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2485 return false; 2486 } 2487 } 2488 } 2489 2490 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 2491 if (LocVT == MVT::i32 || 2492 LocVT == MVT::i64 || 2493 LocVT == MVT::f32 || 2494 LocVT == MVT::f64) { 2495 unsigned Offset8 = State.AllocateStack(8, 8); 2496 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); 2497 return false; 2498 } 2499 } 2500 2501 if (LocVT == MVT::i32 || 2502 LocVT == MVT::f32) { 2503 unsigned Offset9 = State.AllocateStack(4, 4); 2504 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); 2505 return false; 2506 } 2507 2508 if (LocVT == MVT::i64 || 2509 LocVT == MVT::f64) { 2510 unsigned Offset10 = State.AllocateStack(8, 4); 2511 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset10, LocVT, LocInfo)); 2512 return false; 2513 } 2514 2515 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 2516 if (LocVT == MVT::x86mmx) { 2517 unsigned Offset11 = State.AllocateStack(8, 8); 2518 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset11, LocVT, LocInfo)); 2519 return false; 2520 } 2521 } 2522 2523 if (LocVT == MVT::x86mmx) { 2524 unsigned Offset12 = State.AllocateStack(8, 4); 2525 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo)); 2526 return false; 2527 } 2528 2529 if (LocVT == MVT::f80 || 2530 LocVT == MVT::f128) { 2531 unsigned Offset13 = State.AllocateStack( 2532 State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), 2533 State.getMachineFunction().getDataLayout().getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext()))); 2534 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); 2535 return false; 2536 } 2537 2538 if (LocVT == MVT::v16i8 || 2539 LocVT == MVT::v8i16 || 2540 LocVT == MVT::v4i32 || 2541 LocVT == MVT::v2i64 || 2542 LocVT == MVT::v4f32 || 2543 LocVT == MVT::v2f64) { 2544 unsigned Offset14 = State.AllocateStack(16, 16); 2545 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo)); 2546 return false; 2547 } 2548 2549 if (LocVT == MVT::v32i8 || 2550 LocVT == MVT::v16i16 || 2551 LocVT == MVT::v8i32 || 2552 LocVT == MVT::v4i64 || 2553 LocVT == MVT::v8f32 || 2554 LocVT == MVT::v4f64) { 2555 unsigned Offset15 = State.AllocateStack(32, 32); 2556 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo)); 2557 return false; 2558 } 2559 2560 if (LocVT == MVT::v64i8 || 2561 LocVT == MVT::v32i16 || 2562 LocVT == MVT::v16i32 || 2563 LocVT == MVT::v8i64 || 2564 LocVT == MVT::v16f32 || 2565 LocVT == MVT::v8f64) { 2566 unsigned Offset16 = State.AllocateStack(64, 64); 2567 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo)); 2568 return false; 2569 } 2570 2571 return true; // CC didn't match. 2572} 2573 2574 2575static bool CC_X86_Win64_VectorCall(unsigned ValNo, MVT ValVT, 2576 MVT LocVT, CCValAssign::LocInfo LocInfo, 2577 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2578 2579 if (CC_X86_64_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2580 return false; 2581 2582 if (!CC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2583 return false; 2584 2585 return true; // CC didn't match. 2586} 2587 2588 2589static bool RetCC_Intel_OCL_BI(unsigned ValNo, MVT ValVT, 2590 MVT LocVT, CCValAssign::LocInfo LocInfo, 2591 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2592 2593 if (LocVT == MVT::f32 || 2594 LocVT == MVT::f64 || 2595 LocVT == MVT::v4i32 || 2596 LocVT == MVT::v2i64 || 2597 LocVT == MVT::v4f32 || 2598 LocVT == MVT::v2f64) { 2599 static const MCPhysReg RegList1[] = { 2600 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 2601 }; 2602 if (unsigned Reg = State.AllocateReg(RegList1)) { 2603 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2604 return false; 2605 } 2606 } 2607 2608 if (LocVT == MVT::v8f32 || 2609 LocVT == MVT::v4f64 || 2610 LocVT == MVT::v8i32 || 2611 LocVT == MVT::v4i64) { 2612 static const MCPhysReg RegList2[] = { 2613 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3 2614 }; 2615 if (unsigned Reg = State.AllocateReg(RegList2)) { 2616 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2617 return false; 2618 } 2619 } 2620 2621 if (LocVT == MVT::v16f32 || 2622 LocVT == MVT::v8f64 || 2623 LocVT == MVT::v16i32 || 2624 LocVT == MVT::v8i64) { 2625 static const MCPhysReg RegList3[] = { 2626 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 2627 }; 2628 if (unsigned Reg = State.AllocateReg(RegList3)) { 2629 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2630 return false; 2631 } 2632 } 2633 2634 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2635 return false; 2636 2637 return true; // CC didn't match. 2638} 2639 2640 2641bool llvm::RetCC_X86(unsigned ValNo, MVT ValVT, 2642 MVT LocVT, CCValAssign::LocInfo LocInfo, 2643 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2644 2645 if (State.getCallingConv() == CallingConv::Intel_OCL_BI) { 2646 if (!RetCC_Intel_OCL_BI(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2647 return false; 2648 } 2649 2650 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 2651 if (!RetCC_X86_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2652 return false; 2653 } 2654 2655 if (!RetCC_X86_32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2656 return false; 2657 2658 return true; // CC didn't match. 2659} 2660 2661 2662static bool RetCC_X86Common(unsigned ValNo, MVT ValVT, 2663 MVT LocVT, CCValAssign::LocInfo LocInfo, 2664 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2665 2666 if (LocVT == MVT::v1i1) { 2667 LocVT = MVT::i8; 2668 if (ArgFlags.isSExt()) 2669 LocInfo = CCValAssign::SExt; 2670 else if (ArgFlags.isZExt()) 2671 LocInfo = CCValAssign::ZExt; 2672 else 2673 LocInfo = CCValAssign::AExt; 2674 } 2675 2676 if (LocVT == MVT::i1) { 2677 LocVT = MVT::i8; 2678 if (ArgFlags.isSExt()) 2679 LocInfo = CCValAssign::SExt; 2680 else if (ArgFlags.isZExt()) 2681 LocInfo = CCValAssign::ZExt; 2682 else 2683 LocInfo = CCValAssign::AExt; 2684 } 2685 2686 if (LocVT == MVT::i8) { 2687 static const MCPhysReg RegList1[] = { 2688 X86::AL, X86::DL, X86::CL 2689 }; 2690 if (unsigned Reg = State.AllocateReg(RegList1)) { 2691 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2692 return false; 2693 } 2694 } 2695 2696 if (LocVT == MVT::i16) { 2697 static const MCPhysReg RegList2[] = { 2698 X86::AX, X86::DX, X86::CX 2699 }; 2700 if (unsigned Reg = State.AllocateReg(RegList2)) { 2701 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2702 return false; 2703 } 2704 } 2705 2706 if (LocVT == MVT::i32) { 2707 static const MCPhysReg RegList3[] = { 2708 X86::EAX, X86::EDX, X86::ECX 2709 }; 2710 if (unsigned Reg = State.AllocateReg(RegList3)) { 2711 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2712 return false; 2713 } 2714 } 2715 2716 if (LocVT == MVT::i64) { 2717 static const MCPhysReg RegList4[] = { 2718 X86::RAX, X86::RDX, X86::RCX 2719 }; 2720 if (unsigned Reg = State.AllocateReg(RegList4)) { 2721 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2722 return false; 2723 } 2724 } 2725 2726 if (LocVT == MVT::v2i1) { 2727 LocVT = MVT::v2i64; 2728 if (ArgFlags.isSExt()) 2729 LocInfo = CCValAssign::SExt; 2730 else if (ArgFlags.isZExt()) 2731 LocInfo = CCValAssign::ZExt; 2732 else 2733 LocInfo = CCValAssign::AExt; 2734 } 2735 2736 if (LocVT == MVT::v4i1) { 2737 LocVT = MVT::v4i32; 2738 if (ArgFlags.isSExt()) 2739 LocInfo = CCValAssign::SExt; 2740 else if (ArgFlags.isZExt()) 2741 LocInfo = CCValAssign::ZExt; 2742 else 2743 LocInfo = CCValAssign::AExt; 2744 } 2745 2746 if (LocVT == MVT::v8i1) { 2747 LocVT = MVT::v8i16; 2748 if (ArgFlags.isSExt()) 2749 LocInfo = CCValAssign::SExt; 2750 else if (ArgFlags.isZExt()) 2751 LocInfo = CCValAssign::ZExt; 2752 else 2753 LocInfo = CCValAssign::AExt; 2754 } 2755 2756 if (LocVT == MVT::v16i1) { 2757 LocVT = MVT::v16i8; 2758 if (ArgFlags.isSExt()) 2759 LocInfo = CCValAssign::SExt; 2760 else if (ArgFlags.isZExt()) 2761 LocInfo = CCValAssign::ZExt; 2762 else 2763 LocInfo = CCValAssign::AExt; 2764 } 2765 2766 if (LocVT == MVT::v32i1) { 2767 LocVT = MVT::v32i8; 2768 if (ArgFlags.isSExt()) 2769 LocInfo = CCValAssign::SExt; 2770 else if (ArgFlags.isZExt()) 2771 LocInfo = CCValAssign::ZExt; 2772 else 2773 LocInfo = CCValAssign::AExt; 2774 } 2775 2776 if (LocVT == MVT::v64i1) { 2777 LocVT = MVT::v64i8; 2778 if (ArgFlags.isSExt()) 2779 LocInfo = CCValAssign::SExt; 2780 else if (ArgFlags.isZExt()) 2781 LocInfo = CCValAssign::ZExt; 2782 else 2783 LocInfo = CCValAssign::AExt; 2784 } 2785 2786 if (LocVT == MVT::v16i8 || 2787 LocVT == MVT::v8i16 || 2788 LocVT == MVT::v4i32 || 2789 LocVT == MVT::v2i64 || 2790 LocVT == MVT::v4f32 || 2791 LocVT == MVT::v2f64) { 2792 static const MCPhysReg RegList5[] = { 2793 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 2794 }; 2795 if (unsigned Reg = State.AllocateReg(RegList5)) { 2796 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2797 return false; 2798 } 2799 } 2800 2801 if (LocVT == MVT::v32i8 || 2802 LocVT == MVT::v16i16 || 2803 LocVT == MVT::v8i32 || 2804 LocVT == MVT::v4i64 || 2805 LocVT == MVT::v8f32 || 2806 LocVT == MVT::v4f64) { 2807 static const MCPhysReg RegList6[] = { 2808 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3 2809 }; 2810 if (unsigned Reg = State.AllocateReg(RegList6)) { 2811 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2812 return false; 2813 } 2814 } 2815 2816 if (LocVT == MVT::v64i8 || 2817 LocVT == MVT::v32i16 || 2818 LocVT == MVT::v16i32 || 2819 LocVT == MVT::v8i64 || 2820 LocVT == MVT::v16f32 || 2821 LocVT == MVT::v8f64) { 2822 static const MCPhysReg RegList7[] = { 2823 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3 2824 }; 2825 if (unsigned Reg = State.AllocateReg(RegList7)) { 2826 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2827 return false; 2828 } 2829 } 2830 2831 if (LocVT == MVT::x86mmx) { 2832 if (unsigned Reg = State.AllocateReg(X86::MM0)) { 2833 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2834 return false; 2835 } 2836 } 2837 2838 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 2839 if (LocVT == MVT::f80) { 2840 static const MCPhysReg RegList8[] = { 2841 X86::FP0, X86::FP1 2842 }; 2843 if (unsigned Reg = State.AllocateReg(RegList8)) { 2844 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2845 return false; 2846 } 2847 } 2848 } 2849 2850 return true; // CC didn't match. 2851} 2852 2853 2854static bool RetCC_X86_32(unsigned ValNo, MVT ValVT, 2855 MVT LocVT, CCValAssign::LocInfo LocInfo, 2856 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2857 2858 if (State.getCallingConv() == CallingConv::Fast) { 2859 if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2860 return false; 2861 } 2862 2863 if (State.getCallingConv() == CallingConv::Tail) { 2864 if (!RetCC_X86_32_Fast(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2865 return false; 2866 } 2867 2868 if (State.getCallingConv() == CallingConv::HiPE) { 2869 if (!RetCC_X86_32_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2870 return false; 2871 } 2872 2873 if (State.getCallingConv() == CallingConv::X86_VectorCall) { 2874 if (!RetCC_X86_32_VectorCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2875 return false; 2876 } 2877 2878 if (State.getCallingConv() == CallingConv::X86_RegCall) { 2879 if (!RetCC_X86_32_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2880 return false; 2881 } 2882 2883 if (!RetCC_X86_32_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2884 return false; 2885 2886 return true; // CC didn't match. 2887} 2888 2889 2890static bool RetCC_X86_32_C(unsigned ValNo, MVT ValVT, 2891 MVT LocVT, CCValAssign::LocInfo LocInfo, 2892 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2893 2894 if (ArgFlags.isInReg()) { 2895 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { 2896 if (LocVT == MVT::f32 || 2897 LocVT == MVT::f64) { 2898 static const MCPhysReg RegList1[] = { 2899 X86::XMM0, X86::XMM1, X86::XMM2 2900 }; 2901 if (unsigned Reg = State.AllocateReg(RegList1)) { 2902 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2903 return false; 2904 } 2905 } 2906 } 2907 } 2908 2909 if (LocVT == MVT::f32 || 2910 LocVT == MVT::f64) { 2911 static const MCPhysReg RegList2[] = { 2912 X86::FP0, X86::FP1 2913 }; 2914 if (unsigned Reg = State.AllocateReg(RegList2)) { 2915 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2916 return false; 2917 } 2918 } 2919 2920 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2921 return false; 2922 2923 return true; // CC didn't match. 2924} 2925 2926 2927static bool RetCC_X86_32_Fast(unsigned ValNo, MVT ValVT, 2928 MVT LocVT, CCValAssign::LocInfo LocInfo, 2929 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2930 2931 if (LocVT == MVT::f32) { 2932 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { 2933 static const MCPhysReg RegList1[] = { 2934 X86::XMM0, X86::XMM1, X86::XMM2 2935 }; 2936 if (unsigned Reg = State.AllocateReg(RegList1)) { 2937 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2938 return false; 2939 } 2940 } 2941 } 2942 2943 if (LocVT == MVT::f64) { 2944 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE2()) { 2945 static const MCPhysReg RegList2[] = { 2946 X86::XMM0, X86::XMM1, X86::XMM2 2947 }; 2948 if (unsigned Reg = State.AllocateReg(RegList2)) { 2949 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2950 return false; 2951 } 2952 } 2953 } 2954 2955 if (LocVT == MVT::i8) { 2956 static const MCPhysReg RegList3[] = { 2957 X86::AL, X86::DL, X86::CL 2958 }; 2959 if (unsigned Reg = State.AllocateReg(RegList3)) { 2960 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2961 return false; 2962 } 2963 } 2964 2965 if (LocVT == MVT::i16) { 2966 static const MCPhysReg RegList4[] = { 2967 X86::AX, X86::DX, X86::CX 2968 }; 2969 if (unsigned Reg = State.AllocateReg(RegList4)) { 2970 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2971 return false; 2972 } 2973 } 2974 2975 if (LocVT == MVT::i32) { 2976 static const MCPhysReg RegList5[] = { 2977 X86::EAX, X86::EDX, X86::ECX 2978 }; 2979 if (unsigned Reg = State.AllocateReg(RegList5)) { 2980 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2981 return false; 2982 } 2983 } 2984 2985 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 2986 return false; 2987 2988 return true; // CC didn't match. 2989} 2990 2991 2992static bool RetCC_X86_32_HiPE(unsigned ValNo, MVT ValVT, 2993 MVT LocVT, CCValAssign::LocInfo LocInfo, 2994 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2995 2996 if (LocVT == MVT::i8 || 2997 LocVT == MVT::i16) { 2998 LocVT = MVT::i32; 2999 if (ArgFlags.isSExt()) 3000 LocInfo = CCValAssign::SExt; 3001 else if (ArgFlags.isZExt()) 3002 LocInfo = CCValAssign::ZExt; 3003 else 3004 LocInfo = CCValAssign::AExt; 3005 } 3006 3007 if (LocVT == MVT::i32) { 3008 static const MCPhysReg RegList1[] = { 3009 X86::ESI, X86::EBP, X86::EAX, X86::EDX 3010 }; 3011 if (unsigned Reg = State.AllocateReg(RegList1)) { 3012 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3013 return false; 3014 } 3015 } 3016 3017 return true; // CC didn't match. 3018} 3019 3020 3021static bool RetCC_X86_32_RegCall(unsigned ValNo, MVT ValVT, 3022 MVT LocVT, CCValAssign::LocInfo LocInfo, 3023 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3024 3025 if (LocVT == MVT::i1 || 3026 LocVT == MVT::v1i1 || 3027 LocVT == MVT::v8i1) { 3028 LocVT = MVT::i8; 3029 if (ArgFlags.isSExt()) 3030 LocInfo = CCValAssign::SExt; 3031 else if (ArgFlags.isZExt()) 3032 LocInfo = CCValAssign::ZExt; 3033 else 3034 LocInfo = CCValAssign::AExt; 3035 } 3036 3037 if (LocVT == MVT::v16i1) { 3038 LocVT = MVT::i16; 3039 if (ArgFlags.isSExt()) 3040 LocInfo = CCValAssign::SExt; 3041 else if (ArgFlags.isZExt()) 3042 LocInfo = CCValAssign::ZExt; 3043 else 3044 LocInfo = CCValAssign::AExt; 3045 } 3046 3047 if (LocVT == MVT::v32i1) { 3048 LocVT = MVT::i32; 3049 if (ArgFlags.isSExt()) 3050 LocInfo = CCValAssign::SExt; 3051 else if (ArgFlags.isZExt()) 3052 LocInfo = CCValAssign::ZExt; 3053 else 3054 LocInfo = CCValAssign::AExt; 3055 } 3056 3057 if (LocVT == MVT::i8) { 3058 static const MCPhysReg RegList1[] = { 3059 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL 3060 }; 3061 if (unsigned Reg = State.AllocateReg(RegList1)) { 3062 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3063 return false; 3064 } 3065 } 3066 3067 if (LocVT == MVT::i16) { 3068 static const MCPhysReg RegList2[] = { 3069 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI 3070 }; 3071 if (unsigned Reg = State.AllocateReg(RegList2)) { 3072 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3073 return false; 3074 } 3075 } 3076 3077 if (LocVT == MVT::i32) { 3078 static const MCPhysReg RegList3[] = { 3079 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI 3080 }; 3081 if (unsigned Reg = State.AllocateReg(RegList3)) { 3082 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3083 return false; 3084 } 3085 } 3086 3087 if (LocVT == MVT::i64) { 3088 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 3089 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3090 return false; 3091 } 3092 } 3093 3094 if (LocVT == MVT::v64i1) { 3095 LocVT = MVT::i64; 3096 if (ArgFlags.isSExt()) 3097 LocInfo = CCValAssign::SExt; 3098 else if (ArgFlags.isZExt()) 3099 LocInfo = CCValAssign::ZExt; 3100 else 3101 LocInfo = CCValAssign::AExt; 3102 } 3103 3104 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 3105 if (LocVT == MVT::i64) { 3106 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 3107 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3108 return false; 3109 } 3110 } 3111 } 3112 3113 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { 3114 if (LocVT == MVT::i64) { 3115 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3116 return false; 3117 } 3118 } 3119 3120 if (LocVT == MVT::f80) { 3121 static const MCPhysReg RegList4[] = { 3122 X86::FP0, X86::FP1 3123 }; 3124 if (unsigned Reg = State.AllocateReg(RegList4)) { 3125 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3126 return false; 3127 } 3128 } 3129 3130 if (LocVT == MVT::f32 || 3131 LocVT == MVT::f64 || 3132 LocVT == MVT::f128) { 3133 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 3134 static const MCPhysReg RegList5[] = { 3135 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 3136 }; 3137 if (unsigned Reg = State.AllocateReg(RegList5)) { 3138 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3139 return false; 3140 } 3141 } 3142 } 3143 3144 if (LocVT == MVT::v16i8 || 3145 LocVT == MVT::v8i16 || 3146 LocVT == MVT::v4i32 || 3147 LocVT == MVT::v2i64 || 3148 LocVT == MVT::v4f32 || 3149 LocVT == MVT::v2f64) { 3150 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 3151 static const MCPhysReg RegList6[] = { 3152 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 3153 }; 3154 if (unsigned Reg = State.AllocateReg(RegList6)) { 3155 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3156 return false; 3157 } 3158 } 3159 } 3160 3161 if (LocVT == MVT::v32i8 || 3162 LocVT == MVT::v16i16 || 3163 LocVT == MVT::v8i32 || 3164 LocVT == MVT::v4i64 || 3165 LocVT == MVT::v8f32 || 3166 LocVT == MVT::v4f64) { 3167 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 3168 static const MCPhysReg RegList7[] = { 3169 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7 3170 }; 3171 if (unsigned Reg = State.AllocateReg(RegList7)) { 3172 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3173 return false; 3174 } 3175 } 3176 } 3177 3178 if (LocVT == MVT::v64i8 || 3179 LocVT == MVT::v32i16 || 3180 LocVT == MVT::v16i32 || 3181 LocVT == MVT::v8i64 || 3182 LocVT == MVT::v16f32 || 3183 LocVT == MVT::v8f64) { 3184 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 3185 static const MCPhysReg RegList8[] = { 3186 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7 3187 }; 3188 if (unsigned Reg = State.AllocateReg(RegList8)) { 3189 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3190 return false; 3191 } 3192 } 3193 } 3194 3195 return true; // CC didn't match. 3196} 3197 3198 3199static bool RetCC_X86_32_VectorCall(unsigned ValNo, MVT ValVT, 3200 MVT LocVT, CCValAssign::LocInfo LocInfo, 3201 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3202 3203 if (LocVT == MVT::f32 || 3204 LocVT == MVT::f64 || 3205 LocVT == MVT::f128) { 3206 static const MCPhysReg RegList1[] = { 3207 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 3208 }; 3209 if (unsigned Reg = State.AllocateReg(RegList1)) { 3210 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3211 return false; 3212 } 3213 } 3214 3215 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3216 return false; 3217 3218 return true; // CC didn't match. 3219} 3220 3221 3222static bool RetCC_X86_64(unsigned ValNo, MVT ValVT, 3223 MVT LocVT, CCValAssign::LocInfo LocInfo, 3224 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3225 3226 if (State.getCallingConv() == CallingConv::HiPE) { 3227 if (!RetCC_X86_64_HiPE(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3228 return false; 3229 } 3230 3231 if (State.getCallingConv() == CallingConv::WebKit_JS) { 3232 if (!RetCC_X86_64_WebKit_JS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3233 return false; 3234 } 3235 3236 if (State.getCallingConv() == CallingConv::AnyReg) { 3237 if (!RetCC_X86_64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3238 return false; 3239 } 3240 3241 if (State.getCallingConv() == CallingConv::Swift) { 3242 if (!RetCC_X86_64_Swift(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3243 return false; 3244 } 3245 3246 if (State.getCallingConv() == CallingConv::Win64) { 3247 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3248 return false; 3249 } 3250 3251 if (State.getCallingConv() == CallingConv::X86_64_SysV) { 3252 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3253 return false; 3254 } 3255 3256 if (State.getCallingConv() == CallingConv::X86_VectorCall) { 3257 if (!RetCC_X86_64_Vectorcall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3258 return false; 3259 } 3260 3261 if (State.getCallingConv() == CallingConv::HHVM) { 3262 if (!RetCC_X86_64_HHVM(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3263 return false; 3264 } 3265 3266 if (State.getCallingConv() == CallingConv::X86_RegCall) { 3267 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 3268 if (!RetCC_X86_Win64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3269 return false; 3270 } 3271 } 3272 3273 if (State.getCallingConv() == CallingConv::X86_RegCall) { 3274 if (!RetCC_X86_SysV64_RegCall(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3275 return false; 3276 } 3277 3278 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).isTargetWin64()) { 3279 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3280 return false; 3281 } 3282 3283 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3284 return false; 3285 3286 return true; // CC didn't match. 3287} 3288 3289 3290static bool RetCC_X86_64_AnyReg(unsigned ValNo, MVT ValVT, 3291 MVT LocVT, CCValAssign::LocInfo LocInfo, 3292 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3293 3294 if (CC_X86_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3295 return false; 3296 3297 return true; // CC didn't match. 3298} 3299 3300 3301static bool RetCC_X86_64_C(unsigned ValNo, MVT ValVT, 3302 MVT LocVT, CCValAssign::LocInfo LocInfo, 3303 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3304 3305 if (LocVT == MVT::f32) { 3306 static const MCPhysReg RegList1[] = { 3307 X86::XMM0, X86::XMM1 3308 }; 3309 if (unsigned Reg = State.AllocateReg(RegList1)) { 3310 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3311 return false; 3312 } 3313 } 3314 3315 if (LocVT == MVT::f64) { 3316 static const MCPhysReg RegList2[] = { 3317 X86::XMM0, X86::XMM1 3318 }; 3319 if (unsigned Reg = State.AllocateReg(RegList2)) { 3320 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3321 return false; 3322 } 3323 } 3324 3325 if (LocVT == MVT::f128) { 3326 static const MCPhysReg RegList3[] = { 3327 X86::XMM0, X86::XMM1 3328 }; 3329 if (unsigned Reg = State.AllocateReg(RegList3)) { 3330 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3331 return false; 3332 } 3333 } 3334 3335 if (LocVT == MVT::x86mmx) { 3336 static const MCPhysReg RegList4[] = { 3337 X86::XMM0, X86::XMM1 3338 }; 3339 if (unsigned Reg = State.AllocateReg(RegList4)) { 3340 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3341 return false; 3342 } 3343 } 3344 3345 if (ArgFlags.isSwiftError()) { 3346 if (LocVT == MVT::i64) { 3347 if (unsigned Reg = State.AllocateReg(X86::R12)) { 3348 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3349 return false; 3350 } 3351 } 3352 } 3353 3354 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3355 return false; 3356 3357 return true; // CC didn't match. 3358} 3359 3360 3361static bool RetCC_X86_64_HHVM(unsigned ValNo, MVT ValVT, 3362 MVT LocVT, CCValAssign::LocInfo LocInfo, 3363 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3364 3365 if (LocVT == MVT::i8 || 3366 LocVT == MVT::i16 || 3367 LocVT == MVT::i32) { 3368 LocVT = MVT::i64; 3369 if (ArgFlags.isSExt()) 3370 LocInfo = CCValAssign::SExt; 3371 else if (ArgFlags.isZExt()) 3372 LocInfo = CCValAssign::ZExt; 3373 else 3374 LocInfo = CCValAssign::AExt; 3375 } 3376 3377 if (LocVT == MVT::i64) { 3378 static const MCPhysReg RegList1[] = { 3379 X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9, X86::RAX, X86::R10, X86::R11, X86::R13, X86::R14, X86::R15 3380 }; 3381 if (unsigned Reg = State.AllocateReg(RegList1)) { 3382 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3383 return false; 3384 } 3385 } 3386 3387 return true; // CC didn't match. 3388} 3389 3390 3391static bool RetCC_X86_64_HiPE(unsigned ValNo, MVT ValVT, 3392 MVT LocVT, CCValAssign::LocInfo LocInfo, 3393 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3394 3395 if (LocVT == MVT::i8 || 3396 LocVT == MVT::i16 || 3397 LocVT == MVT::i32) { 3398 LocVT = MVT::i64; 3399 if (ArgFlags.isSExt()) 3400 LocInfo = CCValAssign::SExt; 3401 else if (ArgFlags.isZExt()) 3402 LocInfo = CCValAssign::ZExt; 3403 else 3404 LocInfo = CCValAssign::AExt; 3405 } 3406 3407 if (LocVT == MVT::i64) { 3408 static const MCPhysReg RegList1[] = { 3409 X86::R15, X86::RBP, X86::RAX, X86::RDX 3410 }; 3411 if (unsigned Reg = State.AllocateReg(RegList1)) { 3412 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3413 return false; 3414 } 3415 } 3416 3417 return true; // CC didn't match. 3418} 3419 3420 3421static bool RetCC_X86_64_Swift(unsigned ValNo, MVT ValVT, 3422 MVT LocVT, CCValAssign::LocInfo LocInfo, 3423 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3424 3425 if (ArgFlags.isSwiftError()) { 3426 if (LocVT == MVT::i64) { 3427 if (unsigned Reg = State.AllocateReg(X86::R12)) { 3428 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3429 return false; 3430 } 3431 } 3432 } 3433 3434 if (LocVT == MVT::v1i1) { 3435 LocVT = MVT::i8; 3436 if (ArgFlags.isSExt()) 3437 LocInfo = CCValAssign::SExt; 3438 else if (ArgFlags.isZExt()) 3439 LocInfo = CCValAssign::ZExt; 3440 else 3441 LocInfo = CCValAssign::AExt; 3442 } 3443 3444 if (LocVT == MVT::i1) { 3445 LocVT = MVT::i8; 3446 if (ArgFlags.isSExt()) 3447 LocInfo = CCValAssign::SExt; 3448 else if (ArgFlags.isZExt()) 3449 LocInfo = CCValAssign::ZExt; 3450 else 3451 LocInfo = CCValAssign::AExt; 3452 } 3453 3454 if (LocVT == MVT::i8) { 3455 static const MCPhysReg RegList1[] = { 3456 X86::AL, X86::DL, X86::CL, X86::R8B 3457 }; 3458 if (unsigned Reg = State.AllocateReg(RegList1)) { 3459 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3460 return false; 3461 } 3462 } 3463 3464 if (LocVT == MVT::i16) { 3465 static const MCPhysReg RegList2[] = { 3466 X86::AX, X86::DX, X86::CX, X86::R8W 3467 }; 3468 if (unsigned Reg = State.AllocateReg(RegList2)) { 3469 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3470 return false; 3471 } 3472 } 3473 3474 if (LocVT == MVT::i32) { 3475 static const MCPhysReg RegList3[] = { 3476 X86::EAX, X86::EDX, X86::ECX, X86::R8D 3477 }; 3478 if (unsigned Reg = State.AllocateReg(RegList3)) { 3479 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3480 return false; 3481 } 3482 } 3483 3484 if (LocVT == MVT::i64) { 3485 static const MCPhysReg RegList4[] = { 3486 X86::RAX, X86::RDX, X86::RCX, X86::R8 3487 }; 3488 if (unsigned Reg = State.AllocateReg(RegList4)) { 3489 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3490 return false; 3491 } 3492 } 3493 3494 if (LocVT == MVT::f32) { 3495 static const MCPhysReg RegList5[] = { 3496 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 3497 }; 3498 if (unsigned Reg = State.AllocateReg(RegList5)) { 3499 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3500 return false; 3501 } 3502 } 3503 3504 if (LocVT == MVT::f64) { 3505 static const MCPhysReg RegList6[] = { 3506 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 3507 }; 3508 if (unsigned Reg = State.AllocateReg(RegList6)) { 3509 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3510 return false; 3511 } 3512 } 3513 3514 if (LocVT == MVT::f128) { 3515 static const MCPhysReg RegList7[] = { 3516 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 3517 }; 3518 if (unsigned Reg = State.AllocateReg(RegList7)) { 3519 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3520 return false; 3521 } 3522 } 3523 3524 if (LocVT == MVT::x86mmx) { 3525 static const MCPhysReg RegList8[] = { 3526 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 3527 }; 3528 if (unsigned Reg = State.AllocateReg(RegList8)) { 3529 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3530 return false; 3531 } 3532 } 3533 3534 if (!RetCC_X86Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3535 return false; 3536 3537 return true; // CC didn't match. 3538} 3539 3540 3541static bool RetCC_X86_64_Vectorcall(unsigned ValNo, MVT ValVT, 3542 MVT LocVT, CCValAssign::LocInfo LocInfo, 3543 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3544 3545 if (LocVT == MVT::f32 || 3546 LocVT == MVT::f64 || 3547 LocVT == MVT::f128) { 3548 static const MCPhysReg RegList1[] = { 3549 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3 3550 }; 3551 if (unsigned Reg = State.AllocateReg(RegList1)) { 3552 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3553 return false; 3554 } 3555 } 3556 3557 if (!RetCC_X86_Win64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3558 return false; 3559 3560 return true; // CC didn't match. 3561} 3562 3563 3564static bool RetCC_X86_64_WebKit_JS(unsigned ValNo, MVT ValVT, 3565 MVT LocVT, CCValAssign::LocInfo LocInfo, 3566 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3567 3568 if (LocVT == MVT::i8 || 3569 LocVT == MVT::i16 || 3570 LocVT == MVT::i32) { 3571 LocVT = MVT::i64; 3572 if (ArgFlags.isSExt()) 3573 LocInfo = CCValAssign::SExt; 3574 else if (ArgFlags.isZExt()) 3575 LocInfo = CCValAssign::ZExt; 3576 else 3577 LocInfo = CCValAssign::AExt; 3578 } 3579 3580 if (LocVT == MVT::i64) { 3581 if (unsigned Reg = State.AllocateReg(X86::RAX)) { 3582 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3583 return false; 3584 } 3585 } 3586 3587 return true; // CC didn't match. 3588} 3589 3590 3591static bool RetCC_X86_SysV64_RegCall(unsigned ValNo, MVT ValVT, 3592 MVT LocVT, CCValAssign::LocInfo LocInfo, 3593 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3594 3595 if (LocVT == MVT::i1 || 3596 LocVT == MVT::v1i1 || 3597 LocVT == MVT::v8i1) { 3598 LocVT = MVT::i8; 3599 if (ArgFlags.isSExt()) 3600 LocInfo = CCValAssign::SExt; 3601 else if (ArgFlags.isZExt()) 3602 LocInfo = CCValAssign::ZExt; 3603 else 3604 LocInfo = CCValAssign::AExt; 3605 } 3606 3607 if (LocVT == MVT::v16i1) { 3608 LocVT = MVT::i16; 3609 if (ArgFlags.isSExt()) 3610 LocInfo = CCValAssign::SExt; 3611 else if (ArgFlags.isZExt()) 3612 LocInfo = CCValAssign::ZExt; 3613 else 3614 LocInfo = CCValAssign::AExt; 3615 } 3616 3617 if (LocVT == MVT::v32i1) { 3618 LocVT = MVT::i32; 3619 if (ArgFlags.isSExt()) 3620 LocInfo = CCValAssign::SExt; 3621 else if (ArgFlags.isZExt()) 3622 LocInfo = CCValAssign::ZExt; 3623 else 3624 LocInfo = CCValAssign::AExt; 3625 } 3626 3627 if (LocVT == MVT::i8) { 3628 static const MCPhysReg RegList1[] = { 3629 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R12B, X86::R13B, X86::R14B, X86::R15B 3630 }; 3631 if (unsigned Reg = State.AllocateReg(RegList1)) { 3632 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3633 return false; 3634 } 3635 } 3636 3637 if (LocVT == MVT::i16) { 3638 static const MCPhysReg RegList2[] = { 3639 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R12W, X86::R13W, X86::R14W, X86::R15W 3640 }; 3641 if (unsigned Reg = State.AllocateReg(RegList2)) { 3642 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3643 return false; 3644 } 3645 } 3646 3647 if (LocVT == MVT::i32) { 3648 static const MCPhysReg RegList3[] = { 3649 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R12D, X86::R13D, X86::R14D, X86::R15D 3650 }; 3651 if (unsigned Reg = State.AllocateReg(RegList3)) { 3652 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3653 return false; 3654 } 3655 } 3656 3657 if (LocVT == MVT::i64) { 3658 static const MCPhysReg RegList4[] = { 3659 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15 3660 }; 3661 if (unsigned Reg = State.AllocateReg(RegList4)) { 3662 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3663 return false; 3664 } 3665 } 3666 3667 if (LocVT == MVT::v64i1) { 3668 LocVT = MVT::i64; 3669 if (ArgFlags.isSExt()) 3670 LocInfo = CCValAssign::SExt; 3671 else if (ArgFlags.isZExt()) 3672 LocInfo = CCValAssign::ZExt; 3673 else 3674 LocInfo = CCValAssign::AExt; 3675 } 3676 3677 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 3678 if (LocVT == MVT::i64) { 3679 static const MCPhysReg RegList5[] = { 3680 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R12, X86::R13, X86::R14, X86::R15 3681 }; 3682 if (unsigned Reg = State.AllocateReg(RegList5)) { 3683 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3684 return false; 3685 } 3686 } 3687 } 3688 3689 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { 3690 if (LocVT == MVT::i64) { 3691 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3692 return false; 3693 } 3694 } 3695 3696 if (LocVT == MVT::f80) { 3697 static const MCPhysReg RegList6[] = { 3698 X86::FP0, X86::FP1 3699 }; 3700 if (unsigned Reg = State.AllocateReg(RegList6)) { 3701 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3702 return false; 3703 } 3704 } 3705 3706 if (LocVT == MVT::f32 || 3707 LocVT == MVT::f64 || 3708 LocVT == MVT::f128) { 3709 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 3710 static const MCPhysReg RegList7[] = { 3711 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 3712 }; 3713 if (unsigned Reg = State.AllocateReg(RegList7)) { 3714 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3715 return false; 3716 } 3717 } 3718 } 3719 3720 if (LocVT == MVT::v16i8 || 3721 LocVT == MVT::v8i16 || 3722 LocVT == MVT::v4i32 || 3723 LocVT == MVT::v2i64 || 3724 LocVT == MVT::v4f32 || 3725 LocVT == MVT::v2f64) { 3726 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 3727 static const MCPhysReg RegList8[] = { 3728 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 3729 }; 3730 if (unsigned Reg = State.AllocateReg(RegList8)) { 3731 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3732 return false; 3733 } 3734 } 3735 } 3736 3737 if (LocVT == MVT::v32i8 || 3738 LocVT == MVT::v16i16 || 3739 LocVT == MVT::v8i32 || 3740 LocVT == MVT::v4i64 || 3741 LocVT == MVT::v8f32 || 3742 LocVT == MVT::v4f64) { 3743 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 3744 static const MCPhysReg RegList9[] = { 3745 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 3746 }; 3747 if (unsigned Reg = State.AllocateReg(RegList9)) { 3748 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3749 return false; 3750 } 3751 } 3752 } 3753 3754 if (LocVT == MVT::v64i8 || 3755 LocVT == MVT::v32i16 || 3756 LocVT == MVT::v16i32 || 3757 LocVT == MVT::v8i64 || 3758 LocVT == MVT::v16f32 || 3759 LocVT == MVT::v8f64) { 3760 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 3761 static const MCPhysReg RegList10[] = { 3762 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15 3763 }; 3764 if (unsigned Reg = State.AllocateReg(RegList10)) { 3765 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3766 return false; 3767 } 3768 } 3769 } 3770 3771 return true; // CC didn't match. 3772} 3773 3774 3775static bool RetCC_X86_Win64_C(unsigned ValNo, MVT ValVT, 3776 MVT LocVT, CCValAssign::LocInfo LocInfo, 3777 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3778 3779 if (LocVT == MVT::x86mmx) { 3780 LocVT = MVT::i64; 3781 LocInfo = CCValAssign::BCvt; 3782 } 3783 3784 if (LocVT == MVT::f32) { 3785 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 3786 LocVT = MVT::i32; 3787 LocInfo = CCValAssign::BCvt; 3788 } 3789 } 3790 3791 if (LocVT == MVT::f64) { 3792 if (!static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 3793 LocVT = MVT::i64; 3794 LocInfo = CCValAssign::BCvt; 3795 } 3796 } 3797 3798 if (!RetCC_X86_64_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3799 return false; 3800 3801 return true; // CC didn't match. 3802} 3803 3804 3805static bool RetCC_X86_Win64_RegCall(unsigned ValNo, MVT ValVT, 3806 MVT LocVT, CCValAssign::LocInfo LocInfo, 3807 ISD::ArgFlagsTy ArgFlags, CCState &State) { 3808 3809 if (LocVT == MVT::i1 || 3810 LocVT == MVT::v1i1 || 3811 LocVT == MVT::v8i1) { 3812 LocVT = MVT::i8; 3813 if (ArgFlags.isSExt()) 3814 LocInfo = CCValAssign::SExt; 3815 else if (ArgFlags.isZExt()) 3816 LocInfo = CCValAssign::ZExt; 3817 else 3818 LocInfo = CCValAssign::AExt; 3819 } 3820 3821 if (LocVT == MVT::v16i1) { 3822 LocVT = MVT::i16; 3823 if (ArgFlags.isSExt()) 3824 LocInfo = CCValAssign::SExt; 3825 else if (ArgFlags.isZExt()) 3826 LocInfo = CCValAssign::ZExt; 3827 else 3828 LocInfo = CCValAssign::AExt; 3829 } 3830 3831 if (LocVT == MVT::v32i1) { 3832 LocVT = MVT::i32; 3833 if (ArgFlags.isSExt()) 3834 LocInfo = CCValAssign::SExt; 3835 else if (ArgFlags.isZExt()) 3836 LocInfo = CCValAssign::ZExt; 3837 else 3838 LocInfo = CCValAssign::AExt; 3839 } 3840 3841 if (LocVT == MVT::i8) { 3842 static const MCPhysReg RegList1[] = { 3843 X86::AL, X86::CL, X86::DL, X86::DIL, X86::SIL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R12B, X86::R14B, X86::R15B 3844 }; 3845 if (unsigned Reg = State.AllocateReg(RegList1)) { 3846 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3847 return false; 3848 } 3849 } 3850 3851 if (LocVT == MVT::i16) { 3852 static const MCPhysReg RegList2[] = { 3853 X86::AX, X86::CX, X86::DX, X86::DI, X86::SI, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R12W, X86::R14W, X86::R15W 3854 }; 3855 if (unsigned Reg = State.AllocateReg(RegList2)) { 3856 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3857 return false; 3858 } 3859 } 3860 3861 if (LocVT == MVT::i32) { 3862 static const MCPhysReg RegList3[] = { 3863 X86::EAX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R14D, X86::R15D 3864 }; 3865 if (unsigned Reg = State.AllocateReg(RegList3)) { 3866 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3867 return false; 3868 } 3869 } 3870 3871 if (LocVT == MVT::i64) { 3872 static const MCPhysReg RegList4[] = { 3873 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15 3874 }; 3875 if (unsigned Reg = State.AllocateReg(RegList4)) { 3876 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3877 return false; 3878 } 3879 } 3880 3881 if (LocVT == MVT::v64i1) { 3882 LocVT = MVT::i64; 3883 if (ArgFlags.isSExt()) 3884 LocInfo = CCValAssign::SExt; 3885 else if (ArgFlags.isZExt()) 3886 LocInfo = CCValAssign::ZExt; 3887 else 3888 LocInfo = CCValAssign::AExt; 3889 } 3890 3891 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is64Bit()) { 3892 if (LocVT == MVT::i64) { 3893 static const MCPhysReg RegList5[] = { 3894 X86::RAX, X86::RCX, X86::RDX, X86::RDI, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R14, X86::R15 3895 }; 3896 if (unsigned Reg = State.AllocateReg(RegList5)) { 3897 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3898 return false; 3899 } 3900 } 3901 } 3902 3903 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).is32Bit()) { 3904 if (LocVT == MVT::i64) { 3905 if (CC_X86_32_RegCall_Assign2Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 3906 return false; 3907 } 3908 } 3909 3910 if (LocVT == MVT::f80) { 3911 static const MCPhysReg RegList6[] = { 3912 X86::FP0, X86::FP1 3913 }; 3914 if (unsigned Reg = State.AllocateReg(RegList6)) { 3915 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3916 return false; 3917 } 3918 } 3919 3920 if (LocVT == MVT::f32 || 3921 LocVT == MVT::f64 || 3922 LocVT == MVT::f128) { 3923 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 3924 static const MCPhysReg RegList7[] = { 3925 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 3926 }; 3927 if (unsigned Reg = State.AllocateReg(RegList7)) { 3928 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3929 return false; 3930 } 3931 } 3932 } 3933 3934 if (LocVT == MVT::v16i8 || 3935 LocVT == MVT::v8i16 || 3936 LocVT == MVT::v4i32 || 3937 LocVT == MVT::v2i64 || 3938 LocVT == MVT::v4f32 || 3939 LocVT == MVT::v2f64) { 3940 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasSSE1()) { 3941 static const MCPhysReg RegList8[] = { 3942 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15 3943 }; 3944 if (unsigned Reg = State.AllocateReg(RegList8)) { 3945 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3946 return false; 3947 } 3948 } 3949 } 3950 3951 if (LocVT == MVT::v32i8 || 3952 LocVT == MVT::v16i16 || 3953 LocVT == MVT::v8i32 || 3954 LocVT == MVT::v4i64 || 3955 LocVT == MVT::v8f32 || 3956 LocVT == MVT::v4f64) { 3957 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX()) { 3958 static const MCPhysReg RegList9[] = { 3959 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15 3960 }; 3961 if (unsigned Reg = State.AllocateReg(RegList9)) { 3962 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3963 return false; 3964 } 3965 } 3966 } 3967 3968 if (LocVT == MVT::v64i8 || 3969 LocVT == MVT::v32i16 || 3970 LocVT == MVT::v16i32 || 3971 LocVT == MVT::v8i64 || 3972 LocVT == MVT::v16f32 || 3973 LocVT == MVT::v8f64) { 3974 if (static_cast<const X86Subtarget&>(State.getMachineFunction().getSubtarget()).hasAVX512()) { 3975 static const MCPhysReg RegList10[] = { 3976 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15 3977 }; 3978 if (unsigned Reg = State.AllocateReg(RegList10)) { 3979 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 3980 return false; 3981 } 3982 } 3983 } 3984 3985 return true; // CC didn't match. 3986} 3987