1/* 2 * Copyright (C) 2022 Google LLC 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6 7#define PLACEHOLDER 0xffffffff 8#define PLACEHOLDER2 PLACEHOLDER PLACEHOLDER 9#define PLACEHOLDER4 PLACEHOLDER2 PLACEHOLDER2 10 11#define IRQ_BASE 4 12 13/dts-v1/; 14 15/ { 16 interrupt-parent = <&intc>; 17 compatible = "linux,dummy-virt"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { 22 stdout-path = "/uart@3f8"; 23 linux,pci-probe-only = <1>; 24 kaslr-seed = <PLACEHOLDER2>; 25 avf,strict-boot; 26 avf,new-instance; 27 }; 28 29 memory { 30 device_type = "memory"; 31 reg = <0x00 0x80000000 PLACEHOLDER2>; 32 }; 33 34 reserved-memory { 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges; 38 swiotlb: restricted_dma_reserved { 39 compatible = "restricted-dma-pool"; 40 size = <PLACEHOLDER2>; 41 alignment = <PLACEHOLDER2>; 42 }; 43 44 dice { 45 compatible = "google,open-dice"; 46 no-map; 47 reg = <PLACEHOLDER4>; 48 }; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 cpu@0 { 55 device_type = "cpu"; 56 compatible = "arm,arm-v8"; 57 enable-method = "psci"; 58 reg = <0>; 59 }; 60 cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,arm-v8"; 63 enable-method = "psci"; 64 reg = <1>; 65 }; 66 cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,arm-v8"; 69 enable-method = "psci"; 70 reg = <2>; 71 }; 72 cpu@3 { 73 device_type = "cpu"; 74 compatible = "arm,arm-v8"; 75 enable-method = "psci"; 76 reg = <3>; 77 }; 78 cpu@4 { 79 device_type = "cpu"; 80 compatible = "arm,arm-v8"; 81 enable-method = "psci"; 82 reg = <4>; 83 }; 84 cpu@5 { 85 device_type = "cpu"; 86 compatible = "arm,arm-v8"; 87 enable-method = "psci"; 88 reg = <5>; 89 }; 90 cpu@6 { 91 device_type = "cpu"; 92 compatible = "arm,arm-v8"; 93 enable-method = "psci"; 94 reg = <6>; 95 }; 96 cpu@7 { 97 device_type = "cpu"; 98 compatible = "arm,arm-v8"; 99 enable-method = "psci"; 100 reg = <7>; 101 }; 102 cpu@8 { 103 device_type = "cpu"; 104 compatible = "arm,arm-v8"; 105 enable-method = "psci"; 106 reg = <8>; 107 }; 108 cpu@9 { 109 device_type = "cpu"; 110 compatible = "arm,arm-v8"; 111 enable-method = "psci"; 112 reg = <9>; 113 }; 114 cpu@10 { 115 device_type = "cpu"; 116 compatible = "arm,arm-v8"; 117 enable-method = "psci"; 118 reg = <10>; 119 }; 120 cpu@11 { 121 device_type = "cpu"; 122 compatible = "arm,arm-v8"; 123 enable-method = "psci"; 124 reg = <11>; 125 }; 126 cpu@12 { 127 device_type = "cpu"; 128 compatible = "arm,arm-v8"; 129 enable-method = "psci"; 130 reg = <12>; 131 }; 132 cpu@13 { 133 device_type = "cpu"; 134 compatible = "arm,arm-v8"; 135 enable-method = "psci"; 136 reg = <13>; 137 }; 138 cpu@14 { 139 device_type = "cpu"; 140 compatible = "arm,arm-v8"; 141 enable-method = "psci"; 142 reg = <14>; 143 }; 144 cpu@15 { 145 device_type = "cpu"; 146 compatible = "arm,arm-v8"; 147 enable-method = "psci"; 148 reg = <15>; 149 }; 150 }; 151 152 intc: intc { 153 compatible = "arm,gic-v3"; 154 #address-cells = <2>; 155 #size-cells = <2>; 156 #interrupt-cells = <3>; 157 interrupt-controller; 158 reg = <0x00 0x3fff0000 0x00 0x10000>, <PLACEHOLDER4>; 159 }; 160 161 timer { 162 compatible = "arm,armv8-timer"; 163 always-on; 164 /* The IRQ type needs to be OR-ed with the CPU mask */ 165 interrupts = <GIC_PPI 0xd IRQ_TYPE_LEVEL_LOW 166 GIC_PPI 0xe IRQ_TYPE_LEVEL_LOW 167 GIC_PPI 0xb IRQ_TYPE_LEVEL_LOW 168 GIC_PPI 0xa IRQ_TYPE_LEVEL_LOW>; 169 }; 170 171 uart@2e8 { 172 compatible = "ns16550a"; 173 reg = <0x00 0x2e8 0x00 0x8>; 174 clock-frequency = <0x1c2000>; 175 interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; 176 }; 177 178 uart@2f8 { 179 compatible = "ns16550a"; 180 reg = <0x00 0x2f8 0x00 0x8>; 181 clock-frequency = <0x1c2000>; 182 interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; 183 }; 184 185 uart@3e8 { 186 compatible = "ns16550a"; 187 reg = <0x00 0x3e8 0x00 0x8>; 188 clock-frequency = <0x1c2000>; 189 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 190 }; 191 192 uart@3f8 { 193 compatible = "ns16550a"; 194 reg = <0x00 0x3f8 0x00 0x8>; 195 clock-frequency = <0x1c2000>; 196 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 197 }; 198 199 psci { 200 compatible = "arm,psci-1.0"; 201 method = "hvc"; 202 }; 203 204 pci { 205 compatible = "pci-host-cam-generic"; 206 device_type = "pci"; 207 #address-cells = <3>; 208 #size-cells = <2>; 209 #interrupt-cells = <1>; 210 dma-coherent; 211 memory-region = <&swiotlb>; 212 ranges = < 213 0x3000000 0x0 0x02000000 0x0 0x02000000 0x00 0x02000000 214 0x3000000 PLACEHOLDER2 PLACEHOLDER2 PLACEHOLDER2 215 >; 216 bus-range = <0x00 0x00>; 217 reg = <0x00 0x10000 0x00 0x1000000>; 218 interrupt-map = < 219 0x0800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 0) IRQ_TYPE_LEVEL_HIGH 220 0x1000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 1) IRQ_TYPE_LEVEL_HIGH 221 0x1800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 2) IRQ_TYPE_LEVEL_HIGH 222 0x2000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 3) IRQ_TYPE_LEVEL_HIGH 223 0x2800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 4) IRQ_TYPE_LEVEL_HIGH 224 0x3000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 5) IRQ_TYPE_LEVEL_HIGH 225 0x3800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 6) IRQ_TYPE_LEVEL_HIGH 226 0x4000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 7) IRQ_TYPE_LEVEL_HIGH 227 >; 228 interrupt-map-mask = <0xf800 0x0 0x0 0x7 229 0xf800 0x0 0x0 0x7 230 0xf800 0x0 0x0 0x7 231 0xf800 0x0 0x0 0x7 232 0xf800 0x0 0x0 0x7 233 0xf800 0x0 0x0 0x7 234 0xf800 0x0 0x0 0x7 235 0xf800 0x0 0x0 0x7>; 236 }; 237 238 clk: pclk@3M { 239 compatible = "fixed-clock"; 240 clock-frequency = <0x2fefd8>; 241 #clock-cells = <0>; 242 }; 243 244 rtc@2000 { 245 compatible = "arm,primecell"; 246 arm,primecell-periphid = <0x41030>; 247 reg = <0x00 0x2000 0x00 0x1000>; 248 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 249 clock-names = "apb_pclk"; 250 clocks = <&clk>; 251 }; 252 253 vmwdt@3000 { 254 compatible = "qemu,vcpu-stall-detector"; 255 reg = <0x00 0x3000 0x00 0x1000>; 256 clock-frequency = <10>; 257 timeout-sec = <8>; 258 }; 259}; 260