| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 991 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex, in calculateIndirectAddress()
1011 unsigned RegIndex = MI.getOperand(RegOpIdx).getImm(); in expandPostRAPseudo() local
1025 unsigned RegIndex = MI.getOperand(RegOpIdx).getImm(); in expandPostRAPseudo() local
1172 unsigned RegIndex; in getIndirectIndexBegin() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 1036 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex, in calculateIndirectAddress()
1056 unsigned RegIndex = MI.getOperand(RegOpIdx).getImm(); in expandPostRAPseudo() local
1070 unsigned RegIndex = MI.getOperand(RegOpIdx).getImm(); in expandPostRAPseudo() local
1221 unsigned RegIndex; in getIndirectIndexBegin() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 1017 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex, in calculateIndirectAddress()
1037 unsigned RegIndex = MI.getOperand(RegOpIdx).getImm(); in expandPostRAPseudo() local
1051 unsigned RegIndex = MI.getOperand(RegOpIdx).getImm(); in expandPostRAPseudo() local
1198 unsigned RegIndex; in getIndirectIndexBegin() local
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLowering.cpp | 184 for (int32_t RegIndex = 0; RegIndex < NumRegs; ++RegIndex) { in filterTypeToRegisterSet() local
206 const int32_t RegIndex = RegNameToIndex.at(RName); in filterTypeToRegisterSet() local
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| D | IceTargetLoweringX8664.cpp | 6622 Variable *RegIndex = nullptr; in legalize() local
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| D | IceTargetLoweringARM32.cpp | 6098 Variable *RegIndex = nullptr; in legalize() local
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| D | IceTargetLoweringX8632.cpp | 7360 Variable *RegIndex = nullptr; in legalize() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/M68k/AsmParser/ |
| D | M68kAsmParser.cpp | 596 unsigned RegIndex = (unsigned)(RegisterNameLower[1] - '0'); in parseRegisterName() local
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| /external/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 1168 SlotIndex RegIndex = Idx.getRegSlot(); in eliminateUndefCopy() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 1576 SlotIndex RegIndex = Idx.getRegSlot(); in eliminateUndefCopy() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 1644 SlotIndex RegIndex = Idx.getRegSlot(); in eliminateUndefCopy() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 3510 char RegIndex = '0' + (RegNo % 8); in getRegForInlineAsmConstraint() local
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3918 void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) { in warnIfRegIndexIsAT()
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 6118 void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) { in warnIfRegIndexIsAT()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5932 void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) { in warnIfRegIndexIsAT()
|