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/external/llvm/test/MC/Mips/mips64r2/
Dinvalid.s4 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r2 2>%t1
9 andi $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
10 andi $2, $3, 65536 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
11 cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
12 cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
13 # FIXME: Check various 'pos + size' constraints on dext*
14 dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
15 dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
16 dext $2, $3, 1, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32
17 dext $2, $3, 1, 33 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32
[all …]
/external/llvm/test/MC/Mips/mips64r5/
Dinvalid.s4 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r5 2>%t1
9 cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
10 cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
11 drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
12 drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
13 …jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be differe…
14 …jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be differe…
15 pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
16 pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
17 dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
[all …]
/external/llvm/test/MC/Mips/mips32r5/
Dinvalid.s4 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r5 2>%t1
9 cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
10 cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
11 jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
12 jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
13 pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
14 pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
15 mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
16 mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
17 mtc2 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
[all …]
/external/rust/crates/ryu/tests/
Dd2s_test.rs9 // (See accompanying file LICENSE-Apache or copy at
10 // http://www.apache.org/licenses/LICENSE-2.0)
14 // (See accompanying file LICENSE-Boost or copy at
36 fn pretty(f: f64) -> String { in pretty()
40 fn ieee_parts_to_double(sign: bool, ieee_exponent: u32, ieee_mantissa: u64) -> f64 { in ieee_parts_to_double()
42 assert!(ieee_mantissa <= (1u64 << 53) - 1); in ieee_parts_to_double()
48 check!(0.3); in test_ryu()
49 check!(1234000000000000.0); in test_ryu()
50 check!(1.234e16); in test_ryu()
51 check!(2.71828); in test_ryu()
[all …]
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid.s4 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r6 2>%t1
11 align $4, $2, $3, -1 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
12 align $4, $2, $3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
13 jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
14 jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
15 …ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature…
16 break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
17 break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
18 break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
19 break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
[all …]
/external/llvm/test/MC/Mips/mips32r2/
Dinvalid.s4 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 2>%t1
9 addiu $2, $3, -32769 # CHECK: :[[@LINE]]:23: error: expected 16-bit signed immediate
10 addiu $2, $3, 65536 # CHECK: :[[@LINE]]:23: error: expected 16-bit signed immediate
11 andi $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
12 andi $2, $3, 65536 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate
13 cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
14 cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
15 # FIXME: Check '0 < pos + size <= 32' constraint on ext
16 ext $2, $3, -1, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
17 ext $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
[all …]
/external/llvm/test/MC/Mips/micromips/
Dinvalid.s1 # RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1
4 …addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and mult…
5 …addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and mult…
6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
7 addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
8 addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
9 break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
10 break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
11 break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
12 break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
[all …]
/external/llvm/test/MC/Mips/msa/
Dinvalid.s3 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa \
4 # RUN: -show-encoding 2>%t1
8 addvi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
9 addvi.b $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
10 addvi.h $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
11 addvi.h $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
12 addvi.w $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
13 addvi.w $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
14 addvi.d $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
15 addvi.d $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
[all …]
/external/llvm/test/MC/Mips/micromips64r6/
Dinvalid.s1 # RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips64r6 -mattr=micromips 2>%t1
4 …addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and…
5 …addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and…
6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
7 addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
8 …addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran…
9 addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
10 addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
11 …addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran…
12 align $4, $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate
[all …]
Dinvalid-wrong-error.s2 # RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips64r6 -mattr=micromips 2>%t1
6 …# The LLD instruction with invalid memory operand should emit "expected memory with 12-bit signed …
7 …lld $31, 4096($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
8 …lld $31, 2048($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
9 …lld $31, -2049($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
10 …# The LWU instruction with invalid memory operand should emit "expected memory with 12-bit signed …
11 …lwu $31, 4096($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not …
12 …lwu $31, 2048($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not …
13 …lwu $31, -2049($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not …
14 # The 10-bit immediate supported by the standard encodings cause us to emit
[all …]
/external/llvm/test/MC/Mips/micromips32r6/
Dinvalid.s1 # RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1
4 …addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and…
5 …addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and…
6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
7 addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
8 …addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran…
9 addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
10 addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
11 …addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran…
12 align $4, $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate
[all …]
Dinvalid-wrong-error.s2 # RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1
6 # The 10-bit immediate supported by the standard encodings cause us to emit
7 # the diagnostic for the 10-bit form. This isn't exactly wrong but it is
10 teq $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
11 teq $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
12 …teq $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
13 tge $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
14 tge $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
15 …tge $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not curr…
16 tgeu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
[all …]
/external/llvm/test/MC/Mips/dsp/
Dinvalid.s1 # RUN: not llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mattr=dsp 2>%t1
4 extp $2, $ac1, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
5 extp $2, $ac1, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
6 extpdp $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
7 extpdp $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
8 extr.w $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
9 extr.w $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
10 extr_r.w $2, $ac1, -1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
11 extr_r.w $2, $ac1, 32 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
12 extr_rs.w $2, $ac1, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
[all …]
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid.s4 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 2>%t1
11 align $4, $2, $3, -1 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
12 align $4, $2, $3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
13 jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
14 jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
15 …swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature…
16 break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
17 break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
18 break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
19 break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
[all …]
/external/llvm/test/CodeGen/AArch64/
Dldst-unscaledimm.ll1 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
2 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck …
15 ; CHECK-LABEL: ldst_8bit:
17 ; No architectural support for loads to 16-bit or 8-bit since we
21 ; match a sign-extending load 8-bit -> 32-bit
22 %addr_sext32 = getelementptr i8, i8* %addr_8bit, i64 -256
26 ; CHECK: ldursb {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
28 ; match a zero-extending load volatile 8-bit -> 32-bit
29 %addr_zext32 = getelementptr i8, i8* %addr_8bit, i64 -12
33 ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-12]
[all …]
Dldst-unsignedimm.ll1 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
2 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck …
13 ; CHECK-LABEL: ldst_8bit:
15 ; No architectural support for loads to 16-bit or 8-bit since we
18 ; match a sign-extending load 8-bit -> 32-bit
22 ; CHECK: adrp {{x[0-9]+}}, var_8bit
23 ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
25 ; match a zero-extending load volatile 8-bit -> 32-bit
29 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
31 ; match an any-extending load volatile 8-bit -> 32-bit
[all …]
Darm64-movi.ll1 ; RUN: llc < %s -march=arm64 | FileCheck %s
3 ;==--------------------------------------------------------------------------==
4 ; Tests for MOV-immediate implemented with ORR-immediate.
5 ;==--------------------------------------------------------------------------==
7 ; 64-bit immed with 32-bit pattern size, rotated by 0.
9 ; CHECK-LABEL: test64_32_rot0:
10 ; CHECK: mov x0, #30064771079
14 ; 64-bit immed with 32-bit pattern size, rotated by 2.
16 ; CHECK-LABEL: test64_32_rot2:
17 ; CHECK: mov x0, #-4611686002321260541
[all …]
/external/llvm/test/MC/Mips/
Delf_basic.s1 // 32 bit big endian
2 // RUN: llvm-mc -filetype=obj -triple mips-unknown-linux %s -o - | llvm-readobj -h | FileCheck -che…
3 // 32 bit little endian
4 // RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux %s -o - | llvm-readobj -h | FileCheck -c…
5 // 64 bit big endian
6 // RUN: llvm-mc -filetype=obj -arch=mips64 -triple mips64-unknown-linux %s -o - | llvm-readobj -h |…
7 // 64 bit little endian
8 // RUN: llvm-mc -filetype=obj -arch=mips64el -triple mips64el-unknown-linux %s -o - | llvm-readobj …
10 // Check that we produce 32 bit with each endian.
12 // CHECK-BE32: ElfHeader {
[all …]
Dmips-expansions-bad.s1 # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
2 # RUN: FileCheck %s < %t1 --check-prefix=32-BIT
3 # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \
4 # RUN: FileCheck %s --check-prefixes=64-BIT,N32-ONLY
5 # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \
6 # RUN: FileCheck %s --check-prefixes=64-BIT,N64-ONLY
10 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
12 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
14 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
17 # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
[all …]
/external/llvm/test/CodeGen/Mips/
Delf_eflags.ll5 ; Non-shared (static) is the absence of pic and or cpic.
9 ; EF_MIPS_CPIC (0x00000004) - See note below
10 ; EF_MIPS_ABI2 (0x00000020) - n32 not tested yet
16 ; Note that EF_MIPS_CPIC is set by -mabicalls which is the default on Linux
17 ; TODO need to support -mno-abicalls
19 ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o - | FileCheck …
20 ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32 %s -o - | FileCheck -check-prefix=CHECK-LE32_…
21 ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32r2 -relocation-model=static %s -o - | FileChec…
22 ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32r2 %s -o - | FileCheck -check-prefix=CHECK-LE3…
23 …RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+micromips -relocation-model=static %…
[all …]
/external/llvm/test/MC/Mips/cnmips/
Dinvalid.s3 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=octeon 2>%t1
8 bbit0 $19, -1, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
9 bbit0 $19, 64, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
10 bbit032 $19, -1, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
11 bbit032 $19, 32, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
12 bbit1 $19, -1, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
13 bbit1 $19, 64, foo # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
14 bbit132 $19, -1, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
15 bbit132 $19, 32, foo # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
16 ins $2, $3, -1, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
[all …]
/external/llvm/test/MC/Mips/dspr2/
Dinvalid.s3 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mattr=+dspr2 -show-encoding 2>%t1
5 append $2, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
6 append $2, $3, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
7 balign $2, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
8 balign $2, $3, 4 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
9 precr_sra.ph.w $24, $25, -1 # CHECK: :[[@LINE]]:28: error: expected 5-bit unsigned immediate
10 precr_sra.ph.w $24, $25, 32 # CHECK: :[[@LINE]]:28: error: expected 5-bit unsigned immediate
11 precr_sra_r.ph.w $25 ,$26, -1 # CHECK: :[[@LINE]]:30: error: expected 5-bit unsigned immediate
12 precr_sra_r.ph.w $25 ,$26, 32 # CHECK: :[[@LINE]]:30: error: expected 5-bit unsigned immediate
13 prepend $2, $3, -1 # CHECK: :[[@LINE]]:19: error: expected 5-bit unsigned immediate
[all …]
/external/llvm/test/MC/X86/
Dret.s1 // RUN: not llvm-mc -triple x86_64-unknown-unknown --show-encoding %s 2> %t.err | FileCheck --check…
2 // RUN: FileCheck --check-prefix=ERR64 < %t.err %s
3 // RUN: not llvm-mc -triple i386-unknown-unknown --show-encoding %s 2> %t.err | FileCheck --check-p…
4 // RUN: FileCheck --check-prefix=ERR32 < %t.err %s
5 // RUN: not llvm-mc -triple i386-unknown-unknown-code16 --show-encoding %s 2> %t.err | FileCheck --…
6 // RUN: FileCheck --check-prefix=ERR16 < %t.err %s
11 // 32: retl
12 // 32: encoding: [0xc3]
18 // 32: retw
19 // 32: encoding: [0x66,0xc3]
[all …]
Derror-reloc.s1 // RUN: not llvm-mc -triple x86_64-pc-linux %s -o %t.o -filetype=obj 2>&1 | FileCheck %s
4 // CHECK: 32 bit reloc applied to a field with a different size
5 // CHECK-NEXT: .quad foo@gotpcrel
8 // CHECK: 32 bit reloc applied to a field with a different size
9 // CHECK-NEXT: .quad foo@plt
12 // CHECK: 32 bit reloc applied to a field with a different size
13 // CHECK-NEXT: .quad foo@tlsld
16 // CHECK: 32 bit reloc applied to a field with a different size
17 // CHECK-NEXT: .quad foo@gottpoff
20 // CHECK: 32 bit reloc applied to a field with a different size
[all …]
/external/llvm/test/MC/AMDGPU/
Dsopk-err.s1 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN %s
2 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=S…
3 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI…
6 // GCN: error: invalid immediate: only 16-bit values are legal
9 // GCN: error: invalid code of hardware register: only 6-bit values are legal
14 s_setreg_b32 hwreg(3,32,32), s2
15 // GCN: error: invalid bit offset: only 5-bit values are legal
18 // GCN: error: invalid bitfield width: only values from 1 to 32 are legal
21 // GCN: error: invalid immediate: only 16-bit values are legal
24 // GCN: error: invalid bitfield width: only values from 1 to 32 are legal
[all …]

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