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/external/llvm/test/CodeGen/ARM/
Dbuild-attributes.ll33 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 | FileCheck %s --check-prefix=CORTEX-A…
34 …cortex-a5 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math…
35 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-sign-dependent-rounding-fp-mat…
36 …llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-neon,+d16 | FileCheck %s --check-pre…
37 …N: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2 | FileCheck %s --check-prefi…
38 …cortex-a5 -mattr=-vfp2 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no…
39 … llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a8 -float-abi=soft | FileCheck %s --check-pref…
40 …cortex-a8 -float-abi=soft -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable…
41 … llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a8 -float-abi=hard | FileCheck %s --check-pref…
42 …cortex-a8 -float-abi=hard -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable…
[all …]
/external/trusty/arm-trusted-firmware/docs/design/
Dcpu-specific-build-macros.rst45 - `Cortex-A53 MPCore Software Developers Errata Notice`_
46 - `Cortex-A57 MPCore Software Developers Errata Notice`_
47 - `Cortex-A72 MPCore Software Developers Errata Notice`_
73 For Cortex-A9, the following errata build flags are defined :
75 - ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9
78 For Cortex-A15, the following errata build flags are defined :
80 - ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
83 - ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15
86 For Cortex-A17, the following errata build flags are defined :
88 - ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17
[all …]
/external/arm-trusted-firmware/docs/design/
Dcpu-specific-build-macros.rst41 - `Cortex-A53 MPCore Software Developers Errata Notice`_
42 - `Cortex-A57 MPCore Software Developers Errata Notice`_
43 - `Cortex-A72 MPCore Software Developers Errata Notice`_
69 For Cortex-A9, the following errata build flags are defined :
71 - ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9
74 For Cortex-A15, the following errata build flags are defined :
76 - ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
79 - ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15
82 For Cortex-A17, the following errata build flags are defined :
84 - ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17
[all …]
/external/clang/test/Driver/
Daarch64-cpus.c21 // RUN: %clang -target aarch64 -mcpu=cortex-a35 -### -c %s 2>&1 | FileCheck -check-prefix=CA35 %s
22 // RUN: %clang -target aarch64 -mlittle-endian -mcpu=cortex-a35 -### -c %s 2>&1 | FileCheck -check-…
23 // RUN: %clang -target aarch64_be -mlittle-endian -mcpu=cortex-a35 -### -c %s 2>&1 | FileCheck -che…
24 // RUN: %clang -target aarch64 -mtune=cortex-a35 -### -c %s 2>&1 | FileCheck -check-prefix=CA35 %s
25 // RUN: %clang -target aarch64 -mlittle-endian -mtune=cortex-a35 -### -c %s 2>&1 | FileCheck -check…
26 // RUN: %clang -target aarch64_be -mlittle-endian -mtune=cortex-a35 -### -c %s 2>&1 | FileCheck -ch…
27 // CA35: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a35"
29 // RUN: %clang -target arm64 -mcpu=cortex-a35 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-CA35 …
30 // RUN: %clang -target arm64 -mlittle-endian -mcpu=cortex-a35 -### -c %s 2>&1 | FileCheck -check-pr…
31 // RUN: %clang -target arm64 -mtune=cortex-a35 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-CA35…
[all …]
Darm-cortex-cpus.c94 // CHECK-V6M: "-cc1"{{.*}} "-triple" "thumbv6m-{{.*}} "-target-cpu" "cortex-m0"
98 // CHECK-V6M-BIG: "-cc1"{{.*}} "-triple" "thumbebv6m-{{.*}} "-target-cpu" "cortex-m0"
102 // CHECK-V7M: "-cc1"{{.*}} "-triple" "thumbv7m-{{.*}} "-target-cpu" "cortex-m3"
106 // CHECK-V7EM: "-cc1"{{.*}} "-triple" "thumbv7em-{{.*}} "-target-cpu" "cortex-m4"
110 // CHECK-V7EM-BIG: "-cc1"{{.*}} "-triple" "thumbebv7em-{{.*}} "-target-cpu" "cortex-m4"
113 // CHECK-V6M-DARWIN: "-cc1"{{.*}} "-triple" "thumbv6m-{{.*}} "-target-cpu" "cortex-m0"
116 // CHECK-V7M-DARWIN: "-cc1"{{.*}} "-triple" "thumbv7m-{{.*}} "-target-cpu" "cortex-m3"
119 // CHECK-V7EM-DARWIN: "-cc1"{{.*}} "-triple" "thumbv7em-{{.*}} "-target-cpu" "cortex-m4"
123 // CHECK-V7A: "-cc1"{{.*}} "-triple" "armv7-{{.*}} "-target-cpu" "cortex-a8"
127 // CHECK-V7A-THUMB: "-cc1"{{.*}} "-triple" "thumbv7-{{.*}} "-target-cpu" "cortex-a8"
[all …]
Dlinux-as.c8 // RUN: %clang -target arm-linux -mcpu=cortex-a8 -### \
11 // CHECK-ARM-MCPU: as{{(.exe)?}}" "-mfloat-abi=soft" "-mcpu=cortex-a8"
23 // RUN: %clang -target arm-linux -mcpu=cortex-a8 -mfpu=neon -march=armv7-a -### \
26 // CHECK-ARM-ALL: as{{(.exe)?}}" "-mfloat-abi=soft" "-march=armv7-a" "-mcpu=cortex-a8" "-mfpu=neon"
28 // RUN: %clang -target arm-linux -mcpu=cortex-a8 -mfpu=neon -march=armebv7-a -### \
31 // CHECK-ARMEB-ALL: as{{(.exe)?}}" "-mfloat-abi=soft" "-march=armebv7-a" "-mcpu=cortex-a8" "-mfpu=n…
33 // RUN: %clang -target thumb-linux -mcpu=cortex-a8 -mfpu=neon -march=thumbv7-a -### \
36 // CHECK-THUMB-ALL: as{{(.exe)?}}" "-mfloat-abi=soft" "-march=thumbv7-a" "-mcpu=cortex-a8" "-mfpu=n…
38 // RUN: %clang -target thumb-linux -mcpu=cortex-a8 -mfpu=neon -march=thumbebv7-a -### \
41 // CHECK-THUMBEB-ALL: as{{(.exe)?}}" "-mfloat-abi=soft" "-march=thumbebv7-a" "-mcpu=cortex-a8" "-mf…
[all …]
/external/pigweed/pw_toolchain/arm_gcc/
DBUILD.bazel124 name = "cortex-m0",
132 "-mcpu=cortex-m0",
138 name = "cortex-m3",
146 "-mcpu=cortex-m3",
152 name = "cortex-m4",
160 "-mcpu=cortex-m4",
166 name = "cortex-m4+nofp",
174 "-mcpu=cortex-m4+nofp",
180 name = "cortex-m7",
188 "-mcpu=cortex-m7",
[all …]
/external/trusty/arm-trusted-firmware/lib/cpus/
Dcpu-ops.mk10 # Cortex A57 specific optimisation to skip L1 cache flush when
48 # applies only to revision >= r3p0 of the Cortex A15 cpu.
52 # only to revision >= r3p0 of the Cortex A15 cpu.
56 # only to revision <= r1p2 of the Cortex A17 cpu.
60 # only to revision <= r1p2 of the Cortex A17 cpu.
64 # only to revision r0p0 of the Cortex A35 cpu.
68 # only to revision <= r0p1 of the Cortex A53 cpu.
72 # only to revision <= r0p2 of the Cortex A53 cpu.
76 # only to revision <= r0p2 of the Cortex A53 cpu.
80 # only to revision <= r0p2 of the Cortex A53 cpu.
[all …]
/external/OpenCSD/decoder/source/
Dtrc_core_arch_map.cpp44 { "Cortex-A77", { ARCH_V8r3, profile_CortexA } },
45 { "Cortex-A76", { ARCH_V8r3, profile_CortexA } },
46 { "Cortex-A75", { ARCH_V8r3, profile_CortexA } },
47 { "Cortex-A73", { ARCH_V8, profile_CortexA } },
48 { "Cortex-A72", { ARCH_V8, profile_CortexA } },
49 { "Cortex-A65", { ARCH_V8r3, profile_CortexA } },
50 { "Cortex-A57", { ARCH_V8, profile_CortexA } },
51 { "Cortex-A55", { ARCH_V8r3, profile_CortexA } },
52 { "Cortex-A53", { ARCH_V8, profile_CortexA } },
53 { "Cortex-A35", { ARCH_V8, profile_CortexA } },
[all …]
/external/cpuinfo/src/arm/linux/
Daarch32-isa.c59 * - Processors with Cortex-A55 cores in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
60 * - Processors with Cortex-A65 cores in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
61 * - Processors with Cortex-A75 cores in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
62 * - Processors with Cortex-A76 cores in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
63 * - Processors with Cortex-A77 cores in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
75 case UINT32_C(0x4100D050): /* Cortex-A55 */ in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
76 case UINT32_C(0x4100D060): /* Cortex-A65 */ in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
77 case UINT32_C(0x4100D0B0): /* Cortex-A76 */ in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
78 case UINT32_C(0x4100D0D0): /* Cortex-A77 */ in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
79 case UINT32_C(0x4100D0E0): /* Cortex-A76AE */ in cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo()
[all …]
Daarch64-isa.c36 * - Processors with Cortex-A55 cores in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
37 * - Processors with Cortex-A65 cores in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
38 * - Processors with Cortex-A75 cores in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
39 * - Processors with Cortex-A76 cores in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
40 * - Processors with Cortex-A77 cores in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
53 case UINT32_C(0x4100D050): /* Cortex-A55 */ in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
54 case UINT32_C(0x4100D060): /* Cortex-A65 */ in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
55 case UINT32_C(0x4100D0B0): /* Cortex-A76 */ in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
57 case UINT32_C(0x4100D0D0): /* Cortex-A77 */ in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
58 case UINT32_C(0x4100D0E0): /* Cortex-A76AE */ in cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo()
[all …]
Dmidr.c55 …* (i.e. 4x Cortex-A53 + 4x Cortex-A53 is out) and buggy kernels report MIDR information only about…
76 * MSM8916 (Snapdragon 410): 4x Cortex-A53
92 * MSM8939 (Snapdragon 615): 4x Cortex-A53 + 4x Cortex-A53
110 /* MSM8956 (Snapdragon 650): 2x Cortex-A72 + 4x Cortex-A53 */
125 /* MSM8976/MSM8976PRO (Snapdragon 652/653): 4x Cortex-A72 + 4x Cortex-A53 */
140 /* MSM8992 (Snapdragon 808): 2x Cortex-A57 + 4x Cortex-A53 */
155 /* MSM8994/MSM8994V (Snapdragon 810): 4x Cortex-A57 + 4x Cortex-A53 */
171 /* Exynos 5422: 4x Cortex-A15 + 4x Cortex-A7 */
186 /* Exynos 5430: 4x Cortex-A15 + 4x Cortex-A7 */
202 /* Exynos 5433: 4x Cortex-A57 + 4x Cortex-A53 */
[all …]
/external/clang/test/Preprocessor/
Darm-target-features.c132 // RUN: %clang -target armv7 -mcpu=cortex-a15 -x c -E -dM %s -o - | FileCheck -match-full-lines --c…
133 // RUN: %clang -target armv7 -mthumb -mcpu=cortex-a15 -x c -E -dM %s -o - | FileCheck -match-full-l…
134 // RUN: %clang -target armv7 -mcpu=cortex-a15 -mhwdiv=arm -x c -E -dM %s -o - | FileCheck -match-fu…
135 // RUN: %clang -target armv7 -mthumb -mcpu=cortex-a15 -mhwdiv=thumb -x c -E -dM %s -o - | FileCheck…
138 // RUN: %clang -target arm -mcpu=cortex-a15 -mhwdiv=thumb -x c -E -dM %s -o - | FileCheck -match-fu…
139 // RUN: %clang -target arm -mthumb -mcpu=cortex-a15 -mhwdiv=arm -x c -E -dM %s -o - | FileCheck -ma…
140 // RUN: %clang -target arm -mcpu=cortex-a15 -mhwdiv=none -x c -E -dM %s -o - | FileCheck -match-ful…
141 // RUN: %clang -target arm -mthumb -mcpu=cortex-a15 -mhwdiv=none -x c -E -dM %s -o - | FileCheck -m…
145 // Check that -mfpu works properly for Cortex-A7 (enabled by default).
146 // RUN: %clang -target armv7-none-linux-gnueabi -mcpu=cortex-a7 -x c -E -dM %s -o - | FileCheck -ma…
[all …]
/external/cpuinfo/src/arm/
Dmidr.h176 case UINT32_C(0x4100D440): /* Cortex-X1 */ in midr_score_core()
177 case UINT32_C(0x4100D480): /* Cortex-X2 */ in midr_score_core()
178 /* These cores are in big role w.r.t Cortex-A75/-A76/-A77/-A78/-A710 */ in midr_score_core()
180 case UINT32_C(0x4100D080): /* Cortex-A72 */ in midr_score_core()
181 case UINT32_C(0x4100D090): /* Cortex-A73 */ in midr_score_core()
182 case UINT32_C(0x4100D0A0): /* Cortex-A75 */ in midr_score_core()
183 case UINT32_C(0x4100D0B0): /* Cortex-A76 */ in midr_score_core()
184 case UINT32_C(0x4100D0D0): /* Cortex-A77 */ in midr_score_core()
185 case UINT32_C(0x4100D0E0): /* Cortex-A76AE */ in midr_score_core()
186 case UINT32_C(0x4100D410): /* Cortex-A78 */ in midr_score_core()
[all …]
/external/cpuinfo/tools/
Dcpu-info.c151 return "Cortex-A5"; in uarch_to_string()
153 return "Cortex-A7"; in uarch_to_string()
155 return "Cortex-A8"; in uarch_to_string()
157 return "Cortex-A9"; in uarch_to_string()
159 return "Cortex-A12"; in uarch_to_string()
161 return "Cortex-A15"; in uarch_to_string()
163 return "Cortex-A17"; in uarch_to_string()
165 return "Cortex-A32"; in uarch_to_string()
167 return "Cortex-A35"; in uarch_to_string()
169 return "Cortex-A53"; in uarch_to_string()
[all …]
/external/clang/test/CodeGen/
Darm-target-features.c3 // RUN: %clang_cc1 -triple thumbv7-linux-gnueabihf -target-cpu cortex-a8 -emit-llvm -o - %s | FileC…
7 // RUN: %clang_cc1 -triple thumbv7-linux-gnueabi -target-cpu cortex-a9 -emit-llvm -o - %s | FileChe…
11 // RUN: %clang_cc1 -triple thumbv7-linux-gnueabihf -target-cpu cortex-a5 -emit-llvm -o - %s | FileC…
15 // RUN: %clang_cc1 -triple thumbv7-linux-gnueabihf -target-cpu cortex-a7 -emit-llvm -o - %s | FileC…
16 // RUN: %clang_cc1 -triple thumbv7-linux-gnueabi -target-cpu cortex-a12 -emit-llvm -o - %s | FileCh…
17 // RUN: %clang_cc1 -triple armv7-linux-gnueabihf -target-cpu cortex-a15 -emit-llvm -o - %s | FileCh…
18 // RUN: %clang_cc1 -triple armv7-linux-gnueabihf -target-cpu cortex-a17 -emit-llvm -o - %s | FileCh…
25 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a32 -emit-llvm -o - %s | File…
26 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a35 -emit-llvm -o - %s | File…
27 // RUN: %clang_cc1 -triple armv8-linux-gnueabi -target-cpu cortex-a53 -emit-llvm -o - %s | FileChec…
[all …]
/external/arm-trusted-firmware/lib/cpus/
Dcpu-ops.mk8 # Cortex A57 specific optimisation to skip L1 cache flush when
76 # applies only to revision >= r3p0 of the Cortex A15 cpu.
80 # only to revision >= r3p0 of the Cortex A15 cpu.
84 # only to revision <= r1p2 of the Cortex A17 cpu.
88 # only to revision <= r1p2 of the Cortex A17 cpu.
92 # only to revision r0p0 of the Cortex A35 cpu.
96 # only to revision <= r0p1 of the Cortex A53 cpu.
100 # only to revision <= r0p2 of the Cortex A53 cpu.
104 # only to revision <= r0p2 of the Cortex A53 cpu.
108 # only to revision <= r0p2 of the Cortex A53 cpu.
[all …]
/external/arm-trusted-firmware/docs/plat/
Dimx8.rst6 dual-, and quad-core families based on the Arm® Cortex®
7 architecture—including combined Cortex-A72 + Cortex-A53,
8 Cortex-A35, and Cortex-M4 based solutions for advanced graphics,
12 The i.MX8QM is with 2 Cortex-A72 ARM core, 4 Cortex-A53 ARM core
13 and 1 Cortex-M4 system controller.
15 The i.MX8QX is with 4 Cortex-A35 ARM core and 1 Cortex-M4 system
20 controller is a Cortex-M4 that executes system controller firmware.
58 …rs/i.mx-applications-processors/i.mx-8-processors/i.mx-8-family-arm-cortex-a53-cortex-a72-virtuali…
/external/trusty/arm-trusted-firmware/docs/plat/
Dimx8.rst6 dual-, and quad-core families based on the Arm® Cortex®
7 architecture—including combined Cortex-A72 + Cortex-A53,
8 Cortex-A35, and Cortex-M4 based solutions for advanced graphics,
12 The i.MX8QM is with 2 Cortex-A72 ARM core, 4 Cortex-A53 ARM core
13 and 1 Cortex-M4 system controller.
15 The i.MX8QX is with 4 Cortex-A35 ARM core and 1 Cortex-M4 system
20 controller is a Cortex-M4 that executes system controller firmware.
58 …rs/i.mx-applications-processors/i.mx-8-processors/i.mx-8-family-arm-cortex-a53-cortex-a72-virtuali…
/external/bazelbuild-platforms/cpu/
DBUILD25 # implementation. For example, cortex-r52 is a 32 bit processor, and
26 # cortex-r82 is a 64 bit processor, but both are armv8-r architecture.
67 # Cortex-M0, Cortex-M0+, Cortex-M1
73 # Cortex-M3
79 # Cortex-M4, Cortex-M7
85 # Cortex-M4, Cortex-M7 with fpu
91 # Cortex-M23, Cortex-M33, Cortex-M35P
123 name = "cortex-r52",
128 name = "cortex-r82",
/external/trusty/arm-trusted-firmware/docs/plat/st/
Dstm32mp2.rst5 based on Arm Cortex-A35.
15 - STM32MP257: Dual Cortex-A35 cores, Cortex-M33 core - 3x Ethernet (2+1 switch) - 3x CAN FD – H264 …
16 - STM32MP255: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - H264 - 3D GPU – AI…
17 - STM32MP253: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - LVDS
18 - STM32MP251: Single Cortex-A35 core, Cortex-M33 core - 1x Ethernet
20 Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
22 - A Basic + Cortex-A35 @ 1GHz
23 - C Secure Boot + HW Crypto + Cortex-A35 @ 1GHz
24 - D Basic + Cortex-A35 @ 1.5GHz
25 - F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/
DARM.td260 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
272 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
297 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
303 // Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different
322 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
366 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
391 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
402 /// Enabled for Cortex-A57.
403 /// True if disable +1 predication cost for instructions updating CPSR. Enabled for Cortex-A57.
550 def FeatureFixCortexA57AES1742098 : SubtargetFeature<"fix-cortex-a57-aes-1742098",
[all …]
/external/trusty/arm-trusted-firmware/docs/security_advisories/
Dsecurity-advisory-tfv-9.rst51 revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2).
56 | Cortex-A72(from r1p0)|
58 | Cortex-A76 |
60 | Cortex-A76AE |
62 | Cortex-A77 |
64 | Cortex-A78 |
66 | Cortex-A78AE |
68 | Cortex-A78C |
70 | Cortex-X1 |
72 | Cortex-X2 |
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARM.td223 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
233 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
253 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
258 // Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different
274 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
310 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
332 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
340 /// Enabled for Cortex-A57.
544 "Cortex-A5 ARM processors", []>;
546 "Cortex-A7 ARM processors", []>;
[all …]
/external/llvm/lib/Target/ARM/
DARM.td125 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
135 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
148 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
161 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
190 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
200 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
315 "Cortex-A5 ARM processors", []>;
317 "Cortex-A7 ARM processors", []>;
319 "Cortex-A8 ARM processors", []>;
321 "Cortex-A9 ARM processors", []>;
[all …]

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