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/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/
DPPCBranchCoalescing.cpp1 //===-- CoalesceBranches.cpp - Coalesce blocks with the same condition ---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "ppc-branch-coalescing"
37 //===----------------------------------------------------------------------===//
39 //===----------------------------------------------------------------------===//
46 /// This pass does not handle implicit operands on branch statements. In order
47 /// to run on targets that use implicit operands, changes need to be made in the
53 /// %tmp1 = select i1 %test, double %a, double 2.000000e-03
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCBranchCoalescing.cpp1 //===-- CoalesceBranches.cpp - Coalesce blocks with the same condition ---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "ppc-branch-coalescing"
37 //===----------------------------------------------------------------------===//
39 //===----------------------------------------------------------------------===//
46 /// This pass does not handle implicit operands on branch statements. In order
47 /// to run on targets that use implicit operands, changes need to be made in the
53 /// %tmp1 = select i1 %test, double %a, double 2.000000e-03
[all …]
/external/dynamic_depth/internal/base/
Dmacros.h12 // The FALLTHROUGH_INTENDED macro can be used to annotate implicit fall-through
28 // followed by a semicolon. It is designed to mimic control-flow statements
35 // performing switch labels fall-through diagnostic ('-Wimplicit-fallthrough').
37 // http://clang.llvm.org/docs/AttributeReference.html#fallthrough-clang-fallthrough
45 #if __has_feature(cxx_attributes) && __has_warning("-Wimplicit-fallthrough")
/external/libtextclassifier/native/lang_id/common/lite_base/
Dmacros.h8 * http://www.apache.org/licenses/LICENSE-2.0
24 // The SAFTM_FALLTHROUGH_INTENDED macro can be used to annotate implicit
25 // fall-through between switch labels:
41 // be followed by a semicolon. It is designed to mimic control-flow statements
48 // switch labels fall-through diagnostic ('-Wimplicit-fallthrough'). See clang
50 // http://clang.llvm.org/docs/AttributeReference.html#fallthrough-clang-fallthrough
58 #if __has_feature(cxx_attributes) && __has_warning("-Wimplicit-fallthrough")
77 …//stackoverflow.com/questions/1597007/creating-c-macro-with-and-line-token-concatenation-with-posi…
/external/gflags/
DAndroid.bp5 // Added automatically by a large-scale-change
7 // large-scale-change included anything that looked like it might be a license
11 // See: http://go/android-license-faq
16 "SPDX-license-identifier-BSD",
38 "-D__STDC_FORMAT_MACROS",
39 "-DHAVE_INTTYPES_H",
40 "-DHAVE_SYS_STAT_H",
41 "-DHAVE_PTHREAD",
42 "-Wall",
43 "-Werror",
[all …]
/external/libtextclassifier/native/utils/base/
Dmacros.h8 * http://www.apache.org/licenses/LICENSE-2.0
41 // The TC3_FALLTHROUGH_INTENDED macro can be used to annotate implicit
42 // fall-through between switch labels:
58 // followed by a semicolon. It is designed to mimic control-flow statements
65 // performing switch labels fall-through diagnostic ('-Wimplicit-fallthrough').
67 // http://clang.llvm.org/docs/AttributeReference.html#fallthrough-clang-fallthrough
75 #if __has_feature(cxx_attributes) && __has_warning("-Wimplicit-fallthrough")
98 // -fprofile-arcs).
113 // A function-like feature checking macro that is a wrapper around
119 // GCC: https://gcc.gnu.org/gcc-5/changes.html
/external/icing/icing/text_classifier/lib3/utils/base/
Dmacros.h7 // http://www.apache.org/licenses/LICENSE-2.0
39 // The TC3_FALLTHROUGH_INTENDED macro can be used to annotate implicit
40 // fall-through between switch labels:
56 // followed by a semicolon. It is designed to mimic control-flow statements
63 // performing switch labels fall-through diagnostic ('-Wimplicit-fallthrough').
65 // http://clang.llvm.org/docs/AttributeReference.html#fallthrough-clang-fallthrough
73 #if __has_feature(cxx_attributes) && __has_warning("-Wimplicit-fallthrough")
96 // -fprofile-arcs).
111 // A function-like feature checking macro that is a wrapper around
117 // GCC: https://gcc.gnu.org/gcc-5/changes.html
/external/conscrypt/common/src/jni/main/include/conscrypt/
Dmacros.h8 * http://www.apache.org/licenses/LICENSE-2.0
29 // The FALLTHROUGH_INTENDED macro can be used to annotate implicit fall-through
45 // followed by a semicolon. It is designed to mimic control-flow statements
52 // performing switch labels fall-through diagnostic ('-Wimplicit-fallthrough').
62 #if __has_feature(cxx_attributes) && __has_warning("-Wimplicit-fallthrough")
117 * for the purposes of -Werror=unused-parameter. This can be needed when an
133 (len) > static_cast<ssize_t>((array).size()) - (offset))
140 (chunk_len) > static_cast<ssize_t>(array_len) - (chunk_offset))
/external/leveldb/util/
Dhash.cc2 // Use of this source code is governed by a BSD-style license that can be
11 // The FALLTHROUGH_INTENDED macro can be used to annotate implicit fall-through
39 switch (limit - data) { in Hash()
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp1 //===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
8 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
39 /// isLoadFromStackSlot - If the specified machine instruction is a direct
58 /// isStoreToStackSlot - If the specified machine instruction is a direct
121 case SPCC::CPCC_3: // Fall through in GetOppositeBranchCondition()
122 case SPCC::CPCC_2: // Fall through in GetOppositeBranchCondition()
123 case SPCC::CPCC_23: // Fall through in GetOppositeBranchCondition()
124 case SPCC::CPCC_1: // Fall through in GetOppositeBranchCondition()
125 case SPCC::CPCC_13: // Fall through in GetOppositeBranchCondition()
[all …]
/external/llvm/lib/CodeGen/
DMachineVerifier.cpp1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
8 //===----------------------------------------------------------------------===//
21 // command-line option -verify-machineinstrs, or by defining the environment
24 //===----------------------------------------------------------------------===//
90 // Add Reg and any sub-registers to RV
110 // Regs defined in MBB and live out. Note that vregs passing through may
114 // Vregs that pass through MBB untouched. This set is disjoint from
118 // Vregs that must pass through MBB because they are needed by a successor
169 if (addRequired(I->first)) in addRequired()
174 // Live-out registers are either in regsLiveOut or vregsPassed.
[all …]
DBranchFolding.cpp1 //===-- BranchFolding.cpp - Fold machine code branch instructions ---------===//
8 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
53 static cl::opt<cl::boolOrDefault> FlagEnableTailMerge("enable-tail-merge",
58 TailMergeThreshold("tail-merge-threshold",
65 TailMergeSize("tail-merge-size",
70 /// BranchFolderPass - Wrap branch folder in a machine function pass.
90 INITIALIZE_PASS(BranchFolderPass, "branch-folder",
101 PassConfig->getEnableTailMerge(); in runOnMachineFunction()
123 /// RemoveDeadBlock - Remove the specified dead machine basic block from the
[all …]
/external/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/
DRuntimeDyldMachOAArch64.h1 //===-- RuntimeDyldMachOAArch64.h -- MachO/AArch64 specific code. -*- C++ -*-=//
8 //===----------------------------------------------------------------------===//
73 // Get the 26 bit addend encoded in the branch instruction and sign-extend in decodeAddend()
74 // to 64 bit. The lower 2 bits are always zeros and are therefore implicit in decodeAddend()
86 // Get the 21 bit addend encoded in the adrp instruction and sign-extend in decodeAddend()
88 // therefore implicit (<< 12). in decodeAddend()
100 } // fall-through in decodeAddend()
112 // Check which instruction we are decoding to obtain the implicit shift in decodeAddend()
124 // Compensate for implicit shift. in decodeAddend()
199 } // fall-through in encodeAddend()
[all …]
/external/guava/android/guava/src/com/google/common/util/concurrent/
DAtomicLongMap.java7 * http://www.apache.org/licenses/LICENSE-2.0
38 * {@code K}. If a key has not yet been associated with a value, its implicit value is zero.
103 return addAndGet(key, -1); in decrementAndGet()
120 // atomic is now non-null; fall through in addAndGet()
156 return getAndAdd(key, -1); in getAndDecrement()
173 // atomic is now non-null; fall through in getAndAdd()
210 // atomic is now non-null; fall through in put()
334 /** Returns a live, read-only view of the map backing this {@code AtomicLongMap}. */
358 * Returns the number of key-value mappings in this map. If the map contains more than {@code
365 /** Returns {@code true} if this map contains no key-value mappings. */
[all …]
/external/mesa3d/docs/nir/
Dalu.rst17 and commutativity. The info structure for each opcode may be accessed through
21 a certain bit-pattern input to another bit-pattern output. The only concrete
23 of vector components and a bit-size. How that data is interpreted is entirely
25 and friends because they are implicit.
29 floating-point, boolean, integer, or unsigned integer. The ALU type mainly
30 helps back-ends which want to handle all conversion instructions, for instance,
31 in a single switch case. They're also important when a back-end requests the
36 ``~0`` (a.k.a ``-1``) for true even if it is not a 1-bit value. If an
39 Most of the common ALU ops in NIR operate per-component, meaning that the
42 like add, multiply, etc. fall into this category. Per-component operations
[all …]
/external/mesa3d/docs/relnotes/
D21.1.5.rst1 Mesa 21.1.5 Release Notes / 2021-07-14
18 ---------------
22 022c7293074aeeced2278c872db4fa693147c70f8595b076cf3f1ef81520766d mesa-21.1.5.tar.xz
26 ------------
28 - None
32 ---------
34 - [build error] macros.h:88:26: error: size of unnamed array is negative
35 - Game Issue: Nuclear Throne crashes in RadeonSI
36 - Crash in glLinkProgram while trying to craft the link error
37 - Shader compilation memory leaks
[all …]
/external/icu/android_icu4j/src/main/java/android/icu/text/
DLocaleDisplayNames.java6 * Copyright (C) 2009-2016, International Business Machines Corporation and *
83 // fall through in getInstance()
85 // fall through in getInstance()
109 // fall through in getInstance()
111 // fall through in getInstance()
279 …* Struct-like class used to return information for constructing a UI list, each corresponding to a…
283 * Returns the minimized locale for an input locale, such as sr-Cyrl → sr
287 …rns the modified locale for an input locale, such as sr → sr-Cyrl, where there is also an sr-Latn …
291 … the modified locale in the display locale, such as "Englisch (VS)" (for 'en-US', where the displa…
295 * Returns the name of the modified locale in itself, such as "English (US)" (for 'en-US').
[all …]
/external/icu/icu4j/main/core/src/main/java/com/ibm/icu/text/
DLocaleDisplayNames.java5 * Copyright (C) 2009-2016, International Business Machines Corporation and *
89 // fall through in getInstance()
91 // fall through in getInstance()
116 // fall through in getInstance()
118 // fall through in getInstance()
301 …* Struct-like class used to return information for constructing a UI list, each corresponding to a…
306 * Returns the minimized locale for an input locale, such as sr-Cyrl → sr
311 …rns the modified locale for an input locale, such as sr → sr-Cyrl, where there is also an sr-Latn …
316 … the modified locale in the display locale, such as "Englisch (VS)" (for 'en-US', where the displa…
321 * Returns the name of the modified locale in itself, such as "English (US)" (for 'en-US').
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMachineVerifier.cpp1 //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
20 // command-line option -verify-machineinstrs, or by defining the environment
23 //===----------------------------------------------------------------------===//
123 // Add Reg and any sub-registers to RV
127 for (const MCPhysReg &SubReg : TRI->subregs(Reg)) in addRegWithSubRegs()
143 // Regs defined in MBB and live out. Note that vregs passing through may
147 // Vregs that pass through MBB untouched. This set is disjoint from
151 // Vregs that must pass through MBB because they are needed by a successor
[all …]
/external/cronet/net/docs/
Dproxy.md3 This document establishes basic proxy terminology and describes Chrome-specific
18 auto-config](https://en.wikipedia.org/wiki/Proxy_auto-config) scripts. For
30 The port number is optional in both formats. When omitted, a per-scheme default
33 See the [Proxy server schemes](#Proxy-server-schemes) section for details on
38 are generally identified less precisely by just an address -- the proxy
55 identifiers](#Proxy-server-identifiers).
59 * [Manual proxy settings](#Manual-proxy-settings) - proxy resolution is defined
64 * PAC script - proxy resolution is defined using a JavaScript program, that is
68 * Auto-detect - the WPAD protocol is used to probe the network (using DHCP/DNS)
80 * What network traffic can be sent through the proxy?
[all …]
/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/
DMachineCSE.cpp1 //===- MachineCSE.cpp - Machine Common Subexpression Elimination Pass -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
51 #define DEBUG_TYPE "machine-cse"
60 "Number of cross-MBB physreg referencing CS eliminated");
65 CSUsesThreshold("csuses-threshold", cl::Hidden, cl::init(1024),
178 for (MachineOperand &MO : MI->operands()) { in INITIALIZE_PASS_DEPENDENCY()
184 bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg); in INITIALIZE_PASS_DEPENDENCY()
185 MachineInstr *DefMI = MRI->getVRegDef(Reg); in INITIALIZE_PASS_DEPENDENCY()
[all …]
/external/brotli/c/dec/
Ddecode.c43 - doing up to two 16-byte copies for fast backward copying
44 - inserting transformed dictionary word:
63 if (state->state != BROTLI_STATE_UNINITED) return BROTLI_FALSE; in BrotliDecoderSetParameter()
66 state->canny_ringbuffer_allocation = !!value ? 0 : 1; in BrotliDecoderSetParameter()
70 state->large_window = TO_BROTLI_BOOL(!!value); in BrotliDecoderSetParameter()
106 brotli_free_func free_func = state->free_func; in BrotliDecoderDestroyInstance()
107 void* opaque = state->memory_manager_opaque; in BrotliDecoderDestroyInstance()
116 s->error_code = (int)e; in SaveErrorCode()
132 /* Decodes WBITS by reading 1 - 7 bits, or 0x11 for "Large Window Brotli".
133 Precondition: bit-reader accumulator has at least 8 bits. */
[all …]
/external/arm-trusted-firmware/docs/components/
Dexception-handling.rst8 - Interrupts
9 - Synchronous External Aborts
10 - Asynchronous External Aborts
12 |TF-A|'s handling of synchronous ``SMC`` exceptions raised from lower ELs is
13 described in the :ref:`Firmware Design document <handling-an-smc>`. However, the
21 ------------
23 Through various control bits in the ``SCR_EL3`` register, the Arm architecture
26 interrupt routing model, TF-A appropriately sets the ``FIQ`` and ``IRQ`` bits of
34 - Starting with ARMv8.2 architecture extension, many RAS features have been
39 opportunity. Therefore, a *Firmware-first Handling* approach is generally
[all …]
/external/trusty/arm-trusted-firmware/docs/components/
Dexception-handling.rst8 - Interrupts
9 - Synchronous External Aborts
10 - Asynchronous External Aborts
12 |TF-A|'s handling of synchronous ``SMC`` exceptions raised from lower ELs is
13 described in the :ref:`Firmware Design document <handling-an-smc>`. However, the
21 ------------
23 Through various control bits in the ``SCR_EL3`` register, the Arm architecture
26 interrupt routing model, TF-A appropriately sets the ``FIQ`` and ``IRQ`` bits of
34 - Starting with ARMv8.2 architecture extension, many RAS features have been
39 opportunity. Therefore, a *Firmware-first Handling* approach is generally
[all …]
/external/cronet/third_party/brotli/dec/
Ddecode.c44 - doing up to two 16-byte copies for fast backward copying
45 - inserting transformed dictionary word:
64 if (state->state != BROTLI_STATE_UNINITED) return BROTLI_FALSE; in BrotliDecoderSetParameter()
67 state->canny_ringbuffer_allocation = !!value ? 0 : 1; in BrotliDecoderSetParameter()
71 state->large_window = TO_BROTLI_BOOL(!!value); in BrotliDecoderSetParameter()
107 brotli_free_func free_func = state->free_func; in BrotliDecoderDestroyInstance()
108 void* opaque = state->memory_manager_opaque; in BrotliDecoderDestroyInstance()
117 s->error_code = (int)e; in SaveErrorCode()
133 /* Decodes WBITS by reading 1 - 7 bits, or 0x11 for "Large Window Brotli".
134 Precondition: bit-reader accumulator has at least 8 bits. */
[all …]

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