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Searched refs:insn (Results 1 – 25 of 37) sorted by relevance

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/frameworks/compile/mclinker/lib/Target/AArch64/
DAArch64InsnHelpers.h25 static unsigned getBits(InsnType insn, int pos, int l) { in getBits() argument
26 return (insn >> pos) & ((1 << l) - 1); in getBits()
29 static unsigned getRt(InsnType insn) { in getRt() argument
30 return getBits(insn, 0, 5); in getRt()
33 static unsigned getRt2(InsnType insn) { in getRt2() argument
34 return getBits(insn, 10, 5); in getRt2()
37 static unsigned getRa(InsnType insn) { in getRa() argument
38 return getBits(insn, 10, 5); in getRa()
41 static unsigned getRd(InsnType insn) { in getRd() argument
42 return getBits(insn, 0, 5); in getRd()
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/frameworks/libs/binary_translation/assembler/
Dgen_asm_x86.py58 def _get_immediate_type(insn): argument
60 for arg in insn.get('args'):
68 def _get_params(insn): argument
71 for arg in insn.get('args'):
79 def _contains_mem(insn): argument
80 return any(asm_defs.is_mem_op(arg['class']) for arg in insn.get('args'))
83 def _get_template_name(insn): argument
84 name = insn.get('asm')
95 for insn in insns:
96 template, name = _get_template_name(insn)
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Dasm_defs.py129 def get_mem_macro_name(insn, addr_mode = None): argument
130 macro_name = insn.get('asm')
133 for arg in insn['args']:
155 def _expand_name(insn, stem, encoding = {}): argument
161 expanded_insn = copy.deepcopy(insn)
171 for insn in insns:
172 if insn.get('encodings'):
173 assert all((f not in insn) for f in ['stems', 'name', 'asm', 'mnemo'])
175 assert all('opcodes' in encoding for _, encoding in insn['encodings'].items())
176 expanded_insns.extend([_expand_name(insn, stem, encoding)
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Dgen_asm_tests_x86.py287 for insn in insns:
288 arc_name = insn['asm']
289 insn_name = insn['mnemo']
290 if len(insn['args']) and insn['args'][0]['class'] == 'Cond':
299 file, arc_name, insn_name + insn_suffix, insn['args'], fast_mode)
300 elif arc_name == 'Call' and insn['args'][1]['class'] != 'Label':
301 _gen_att_call_variants(file, insn['args'], fast_mode)
304 file, arc_name, insn_name, insn['args'], fast_mode)
445 for insn in insns:
446 _gen_arc_instruction_variants(file, insn['asm'], insn['args'], fast_mode)
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/frameworks/libs/binary_translation/backend/x86_64/
Dinsn_folding.cc32 void DefMap::MapDefRegs(const MachineInsn* insn) { in MapDefRegs() argument
33 for (int op = 0; op < insn->NumRegOperands(); ++op) { in MapDefRegs()
34 MachineReg reg = insn->RegAt(op); in MapDefRegs()
35 if (insn->RegKindAt(op).RegClass()->IsSubsetOf(&x86_64::kFLAGS)) { in MapDefRegs()
42 if (insn->RegKindAt(op).IsDef()) { in MapDefRegs()
43 Set(reg, insn); in MapDefRegs()
48 void DefMap::ProcessInsn(const MachineInsn* insn) { in ProcessInsn() argument
49 MapDefRegs(insn); in ProcessInsn()
64 const auto* insn = AsMachineInsnX86_64(general_insn); in IsRegImm() local
65 if (insn->opcode() == kMachineOpMovqRegImm) { in IsRegImm()
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Dcode_debug.cc63 string GetImplicitRegOperandDebugString(const MachineInsnX86_64* insn, int i) { in GetImplicitRegOperandDebugString() argument
64 return StringPrintf("(%s)", GetRegOperandDebugString(insn, i).c_str()); in GetImplicitRegOperandDebugString()
67 string GetAbsoluteMemOperandDebugString(const MachineInsnX86_64* insn) { in GetAbsoluteMemOperandDebugString() argument
68 return StringPrintf("[0x%x]", insn->disp()); in GetAbsoluteMemOperandDebugString()
71 string GetBaseDispMemOperandDebugString(const MachineInsnX86_64* insn, int i) { in GetBaseDispMemOperandDebugString() argument
72 return StringPrintf("[%s + 0x%x]", GetRegOperandDebugString(insn, i).c_str(), insn->disp()); in GetBaseDispMemOperandDebugString()
75 string GetIndexDispMemOperandDebugString(const MachineInsnX86_64* insn, int i) { in GetIndexDispMemOperandDebugString() argument
77 GetRegOperandDebugString(insn, i).c_str(), in GetIndexDispMemOperandDebugString()
78 ScaleToInt(insn->scale()), in GetIndexDispMemOperandDebugString()
79 insn->disp()); in GetIndexDispMemOperandDebugString()
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Dmachine_ir_opt.cc66 bool AreResultsUsed(const MachineInsn* insn, const RegUsageBitSet& is_reg_used) { in AreResultsUsed() argument
67 for (int i = 0; i < insn->NumRegOperands(); ++i) { in AreResultsUsed()
68 if (insn->RegKindAt(i).IsDef() && is_reg_used[insn->RegAt(i)]) { in AreResultsUsed()
75 void SetInsnResultsUnused(const MachineInsn* insn, RegUsageBitSet& is_reg_used) { in SetInsnResultsUnused() argument
76 for (int i = 0; i < insn->NumRegOperands(); ++i) { in SetInsnResultsUnused()
77 if (insn->RegKindAt(i).IsDef()) { in SetInsnResultsUnused()
78 is_reg_used.Reset(insn->RegAt(i)); in SetInsnResultsUnused()
83 void SetInsnArgumentsUsed(const MachineInsn* insn, RegUsageBitSet& is_reg_used) { in SetInsnArgumentsUsed() argument
84 for (int i = 0; i < insn->NumRegOperands(); ++i) { in SetInsnArgumentsUsed()
85 if (insn->RegKindAt(i).IsUse()) { in SetInsnArgumentsUsed()
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Drename_vregs_local_test.cc54 MachineInsn* insn = *insn_it; in TEST() local
55 EXPECT_EQ(vreg1, insn->RegAt(0)); in TEST()
58 insn = *insn_it; in TEST()
59 EXPECT_EQ(vreg2, insn->RegAt(0)); in TEST()
88 MachineInsn* insn = *insn_it; in TEST() local
89 MachineReg vreg2_renamed = insn->RegAt(0); in TEST()
93 insn = *insn_it; in TEST()
94 EXPECT_EQ(vreg2_renamed, insn->RegAt(1)); in TEST()
123 MachineInsn* insn = *insn_it; in TEST() local
124 EXPECT_EQ(vreg1, insn->RegAt(0)); in TEST()
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Drename_copy_uses.cc35 void RenameCopyUsesMap::RenameUseIfMapped(MachineInsn* insn, int i) { in RenameUseIfMapped() argument
39 if (insn->opcode() == kMachineOpCallImmArg || insn->RegKindAt(i).RegClass()->NumRegs() == 1) { in RenameUseIfMapped()
42 MachineReg reg = insn->RegAt(i); in RenameUseIfMapped()
49 insn->SetRegAt(i, mapped); in RenameUseIfMapped()
53 void RenameCopyUsesMap::ProcessDef(MachineInsn* insn, int i) { in ProcessDef() argument
54 MachineReg reg = insn->RegAt(i); in ProcessDef()
94 for (MachineInsn* insn : bb->insn_list()) { in RenameCopyUses()
95 for (int i = 0; i < insn->NumRegOperands(); ++i) { in RenameCopyUses()
97 if (insn->RegKindAt(i).IsDef()) { in RenameCopyUses()
98 map.ProcessDef(insn, i); in RenameCopyUses()
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Dloop_guest_context_optimizer.cc33 auto* insn = AsMachineInsnX86_64(*insn_it); in ReplaceGetAndUpdateMap() local
34 auto disp = insn->disp(); in ReplaceGetAndUpdateMap()
37 switch (insn->opcode()) { in ReplaceGetAndUpdateMap()
59 auto dst = insn->RegAt(0); in ReplaceGetAndUpdateMap()
60 auto copy_size = insn->opcode() == kMachineOpMovdqaXRegMemBaseDisp ? 16 : 8; in ReplaceGetAndUpdateMap()
68 auto* insn = AsMachineInsnX86_64(*insn_it); in ReplacePutAndUpdateMap() local
69 auto disp = insn->disp(); in ReplacePutAndUpdateMap()
72 switch (insn->opcode()) { in ReplacePutAndUpdateMap()
96 auto src = insn->RegAt(1); in ReplacePutAndUpdateMap()
97 auto copy_size = insn->opcode() == kMachineOpMovdqaMemBaseDispXReg ? 16 : 8; in ReplacePutAndUpdateMap()
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Dlocal_guest_context_optimizer.cc52 auto* insn = AsMachineInsnX86_64(*insn_it); in RemoveLocalGuestContextAccesses() local
53 if (insn->IsCPUStateGet()) { in RemoveLocalGuestContextAccesses()
55 } else if (insn->IsCPUStatePut()) { in RemoveLocalGuestContextAccesses()
63 auto* insn = AsMachineInsnX86_64(*insn_it); in ReplaceGetAndUpdateMap() local
64 auto dst = insn->RegAt(0); in ReplaceGetAndUpdateMap()
65 auto disp = insn->disp(); in ReplaceGetAndUpdateMap()
74 auto copy_size = insn->opcode() == kMachineOpMovdqaXRegMemBaseDisp ? 16 : 8; in ReplaceGetAndUpdateMap()
80 auto* insn = AsMachineInsnX86_64(*insn_it); in ReplacePutAndUpdateMap() local
81 auto src = insn->RegAt(1); in ReplacePutAndUpdateMap()
82 auto disp = insn->disp(); in ReplacePutAndUpdateMap()
Dliveness_analyzer.cc66 const MachineInsn* insn = *insn_it; in VisitBasicBlock() local
68 for (int i = 0; i < insn->NumRegOperands(); ++i) { in VisitBasicBlock()
69 if (insn->RegAt(i).IsVReg() && insn->RegKindAt(i).IsDef()) { in VisitBasicBlock()
70 running_liveness.Reset(insn->RegAt(i)); in VisitBasicBlock()
73 for (int i = 0; i < insn->NumRegOperands(); ++i) { in VisitBasicBlock()
74 if (insn->RegAt(i).IsVReg() && insn->RegKindAt(i).IsInput()) { in VisitBasicBlock()
75 running_liveness.Set(insn->RegAt(i)); in VisitBasicBlock()
Dinsn_folding_test.cc59 for (const auto* insn : bb->insn_list()) { in TryRegRegInsnFolding() local
60 def_map.ProcessInsn(insn); in TryRegRegInsnFolding()
67 const MachineInsn* insn = *insn_it; in TryRegRegInsnFolding() local
69 auto [is_folded, folded_insn] = insn_folding.TryFoldInsn(insn); in TryRegRegInsnFolding()
106 for (const auto* insn : bb->insn_list()) { in TryMovInsnFolding() local
107 def_map.ProcessInsn(insn); in TryMovInsnFolding()
114 const MachineInsn* insn = *insn_it; in TryMovInsnFolding() local
116 auto [is_folded, folded_insn] = insn_folding.TryFoldInsn(insn); in TryMovInsnFolding()
154 for (const auto* insn : bb->insn_list()) { in TEST() local
155 def_map.ProcessInsn(insn); in TEST()
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Dmachine_ir_check.cc87 for (auto* insn : bb->insn_list()) { in CheckControlTransferInsn() local
88 switch (insn->opcode()) { in CheckControlTransferInsn()
90 return insn == bb->insn_list().back(); in CheckControlTransferInsn()
92 return insn == bb->insn_list().back(); in CheckControlTransferInsn()
94 if (insn != bb->insn_list().back()) { in CheckControlTransferInsn()
97 const PseudoBranch* branch = reinterpret_cast<const PseudoBranch*>(insn); in CheckControlTransferInsn()
101 if (insn != bb->insn_list().back()) { in CheckControlTransferInsn()
104 const PseudoCondBranch* cond_branch = reinterpret_cast<const PseudoCondBranch*>(insn); in CheckControlTransferInsn()
Drename_vregs.cc28 for (auto* insn : bb->insn_list()) { in AssignNewVRegs() local
29 for (int i = 0; i < insn->NumRegOperands(); ++i) { in AssignNewVRegs()
30 auto reg = insn->RegAt(i); in AssignNewVRegs()
32 insn->SetRegAt(i, Get(reg, bb)); in AssignNewVRegs()
34 max_size = std::max(max_size, insn->RegKindAt(i).RegClass()->RegSize()); in AssignNewVRegs()
57 PseudoCopy* insn = in GenInterBasicBlockMove() local
63 succ_bb->insn_list().insert(succ_bb->insn_list().begin(), insn); in GenInterBasicBlockMove()
71 pred_bb->insn_list().insert(--pred_bb->insn_list().end(), insn); in GenInterBasicBlockMove()
Drename_vregs_local.cc55 MachineInsn* insn = *insn_it; in TryRenameRegOperand() local
56 MachineReg reg = insn->RegAt(operand_index); in TryRenameRegOperand()
62 if (insn->RegKindAt(operand_index).IsDef()) { in TryRenameRegOperand()
71 if (insn->RegKindAt(operand_index).IsUse()) { in TryRenameRegOperand()
75 insn->SetRegAt(operand_index, new_reg); in TryRenameRegOperand()
80 CHECK(insn->RegKindAt(operand_index).IsUse()); in TryRenameRegOperand()
83 insn->SetRegAt(operand_index, vreg_map.Get(reg)); in TryRenameRegOperand()
90 MachineInsn* insn = *insn_it; in RenameInsnListRegs() local
91 for (int i = 0; i < insn->NumRegOperands(); ++i) { in RenameInsnListRegs()
Dcontext_liveness_analyzer.cc61 auto* insn = AsMachineInsnX86_64(*insn_it); in VisitBasicBlock() local
62 if (insn->IsCPUStatePut()) { in VisitBasicBlock()
63 running_liveness.reset(insn->disp()); in VisitBasicBlock()
64 } else if (insn->IsCPUStateGet()) { in VisitBasicBlock()
65 running_liveness.set(insn->disp()); in VisitBasicBlock()
/frameworks/libs/binary_translation/backend/
Dgen_lir_lib.py150 def _check_insn_defs(insn, skip_unsupported=False): argument
154 for arg in insn.get('args'):
165 addr_mode = insn.get('addr_mode')
185 def _get_insn_operands(insn): argument
196 side_effects = insn['name'] in ('Int3', 'Lfence', 'Mfence', 'Sfence', 'UD2')
197 for arg in insn.get('args'):
211 addr_mode = insn.get('addr_mode')
235 def _get_insn_debug_operands(insn): argument
238 for arg in insn.get('args'):
253 addr_mode = insn.get('addr_mode')
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/frameworks/libs/binary_translation/backend/common/
Dlifetime_analysis.cc50 void VRegLifetimeAnalysis::TrySetMoveHint(const MachineInsn* insn) { in TrySetMoveHint() argument
51 if (!insn->is_copy()) { in TrySetMoveHint()
56 DCHECK_EQ(insn->NumRegOperands(), 2); in TrySetMoveHint()
57 MachineReg dst = insn->RegAt(0); in TrySetMoveHint()
61 MachineReg src = insn->RegAt(1); in TrySetMoveHint()
71 const MachineInsn* insn = pos.insn(); in AddInsn() local
77 for (int i = 0; i < insn->NumRegOperands(); ++i) { in AddInsn()
79 MachineReg r = insn->RegAt(i); in AddInsn()
85 const MachineRegKind& reg_kind = insn->RegKindAt(i); in AddInsn()
98 for (int i = 0; i < insn->NumRegOperands(); ++i) { in AddInsn()
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Dmachine_ir_debug.cc29 for (const auto* insn : insn_list) { in GetInsnListDebugString() local
31 out += insn->GetDebugString(); in GetInsnListDebugString()
52 std::string GetRegOperandDebugString(const MachineInsn* insn, int i) { in GetRegOperandDebugString() argument
53 MachineReg r = insn->RegAt(i); in GetRegOperandDebugString()
56 out += insn->RegKindAt(i).RegClass()->GetDebugName(); in GetRegOperandDebugString()
116 for (const auto* insn : bb->insn_list()) { in GetDebugStringForDot() local
117 str += insn->GetDebugString(); in GetDebugStringForDot()
/frameworks/libs/binary_translation/backend/include/berberis/backend/x86_64/
Dcode_debug.h30 std::string GetImplicitRegOperandDebugString(const MachineInsnX86_64* insn, int i);
31 std::string GetAbsoluteMemOperandDebugString(const MachineInsnX86_64* insn);
32 std::string GetBaseDispMemOperandDebugString(const MachineInsnX86_64* insn, int i);
33 std::string GetIndexDispMemOperandDebugString(const MachineInsnX86_64* insn, int i);
36 std::string GetBaseIndexDispMemOperandDebugString(const MachineInsnX86_64* insn, int i);
37 std::string GetImmOperandDebugString(const MachineInsnX86_64* insn);
38 std::string GetCondOperandDebugString(const MachineInsnX86_64* insn);
39 std::string GetLabelOperandDebugString(const MachineInsnX86_64* insn);
Dinsn_folding.h48 void ProcessInsn(const MachineInsn* insn);
52 void Set(MachineReg reg, const MachineInsn* insn) { in Set() argument
54 def_map_.at(reg.GetVRegIndex()) = std::pair(insn, index_); in Set()
57 void MapDefRegs(const MachineInsn* insn);
68 std::tuple<bool, MachineInsn*> TryFoldInsn(const MachineInsn* insn);
74 bool IsWritingSameFlagsValue(const MachineInsn* insn) const;
76 std::tuple<bool, MachineInsn*> TryFoldImmediateInput(const MachineInsn* insn);
77 std::tuple<bool, MachineInsn*> TryFoldRedundantMovl(const MachineInsn* insn);
78 MachineInsn* NewImmInsnFromRegInsn(const MachineInsn* insn, int32_t imm);
/frameworks/libs/binary_translation/backend/include/berberis/backend/common/
Dmachine_ir_builder.h41 InsnType* insn = ir_->template NewInsn<InsnType>(args...); in Gen() local
42 InsertInsn(insn); in Gen()
43 return insn; in Gen()
70 void InsertInsn(MachineInsn* insn) { bb_->insn_list().push_back(insn); } in InsertInsn() argument
Dlifetime.h39 MachineReg GetVReg() const { return pos_.insn()->RegAt(index_); } in GetVReg()
42 pos_.insn()->SetRegAt(index_, reg); in RewriteVReg()
48 if (pos_.insn()->is_copy() && !pos_.insn()->RegAt(0).IsSpilledReg()) { in RewriteVReg()
51 pos_.insn()->SetRegAt(1, spill); in RewriteVReg()
57 if (pos_.insn()->is_copy() && !pos_.insn()->RegAt(1).IsSpilledReg()) { in RewriteVReg()
60 pos_.insn()->SetRegAt(0, spill); in RewriteVReg()
68 const MachineRegClass* GetRegClass() const { return pos_.insn()->RegKindAt(index_).RegClass(); } in GetRegClass()
80 std::string GetInsnDebugString() const { return pos_.insn()->GetDebugString(); } in GetInsnDebugString()
82 bool IsUse() const { return pos_.insn()->RegKindAt(index_).IsUse(); } in IsUse()
84 bool IsDef() const { return pos_.insn()->RegKindAt(index_).IsDef(); } in IsDef()
/frameworks/libs/binary_translation/intrinsics/
Dgen_intrinsics.py1056 for insn in insns:
1057 insn['arch'] = arch
1059 for insn in insns:
1060 insn['macroassembler'] = macroassembler
1061 insns_map = dict((insn['name'], insn) for insn in insns)
1065 insn = insns_map[arch_intr['insn']]
1066 _add_asm_insn(intrs, arch_intr, insn)
1085 def _add_asm_insn(intrs, arch_intr, insn): argument
1096 assert 'variants' not in insn or insn['variants'] == arch_intr['variants']
1097 assert 'feature' not in insn or insn['feature'] == arch_intr['feature']
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