1 /*
2 * Copyright (C) 2015 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include <memory>
18 #include <vector>
19
20 #include "arch/instruction_set.h"
21 #include "base/macros.h"
22 #include "base/runtime_debug.h"
23 #include "cfi_test.h"
24 #include "driver/compiler_options.h"
25 #include "gtest/gtest.h"
26 #include "optimizing/code_generator.h"
27 #include "optimizing/optimizing_unit_test.h"
28 #include "read_barrier_config.h"
29 #include "utils/arm/assembler_arm_vixl.h"
30 #include "utils/assembler.h"
31
32 #include "optimizing/optimizing_cfi_test_expected.inc"
33
34 namespace vixl32 = vixl::aarch32;
35
36 namespace art HIDDEN {
37
38 class OptimizingCFITest : public CFITest, public OptimizingUnitTestHelper {
39 public:
40 // Enable this flag to generate the expected outputs.
41 static constexpr bool kGenerateExpected = false;
42
OptimizingCFITest()43 OptimizingCFITest()
44 : graph_(nullptr),
45 code_gen_(),
46 blocks_(GetAllocator()->Adapter()) {}
47
SetUpFrame(InstructionSet isa)48 void SetUpFrame(InstructionSet isa) {
49 OverrideInstructionSetFeatures(isa, "default");
50
51 // Ensure that slow-debug is off, so that there is no unexpected read-barrier check emitted.
52 SetRuntimeDebugFlagsEnabled(false);
53
54 // Setup simple context.
55 graph_ = CreateGraph();
56 // Generate simple frame with some spills.
57 code_gen_ = CodeGenerator::Create(graph_, *compiler_options_);
58 code_gen_->GetAssembler()->cfi().SetEnabled(true);
59 code_gen_->InitializeCodeGenerationData();
60 const int frame_size = 64;
61 int core_reg = 0;
62 int fp_reg = 0;
63 for (int i = 0; i < 2; i++) { // Two registers of each kind.
64 for (; core_reg < 32; core_reg++) {
65 if (code_gen_->IsCoreCalleeSaveRegister(core_reg)) {
66 auto location = Location::RegisterLocation(core_reg);
67 code_gen_->AddAllocatedRegister(location);
68 core_reg++;
69 break;
70 }
71 }
72 for (; fp_reg < 32; fp_reg++) {
73 if (code_gen_->IsFloatingPointCalleeSaveRegister(fp_reg)) {
74 auto location = Location::FpuRegisterLocation(fp_reg);
75 code_gen_->AddAllocatedRegister(location);
76 fp_reg++;
77 break;
78 }
79 }
80 }
81 code_gen_->block_order_ = &blocks_;
82 code_gen_->ComputeSpillMask();
83 code_gen_->SetFrameSize(frame_size);
84 code_gen_->GenerateFrameEntry();
85 }
86
Finish()87 void Finish() {
88 code_gen_->GenerateFrameExit();
89 code_gen_->Finalize();
90 }
91
Check(InstructionSet isa,const char * isa_str,const std::vector<uint8_t> & expected_asm,const std::vector<uint8_t> & expected_cfi)92 void Check(InstructionSet isa,
93 const char* isa_str,
94 const std::vector<uint8_t>& expected_asm,
95 const std::vector<uint8_t>& expected_cfi) {
96 // Get the outputs.
97 ArrayRef<const uint8_t> actual_asm = code_gen_->GetCode();
98 Assembler* opt_asm = code_gen_->GetAssembler();
99 ArrayRef<const uint8_t> actual_cfi(*(opt_asm->cfi().data()));
100
101 if (kGenerateExpected) {
102 GenerateExpected(stdout, isa, isa_str, actual_asm, actual_cfi);
103 } else {
104 EXPECT_EQ(ArrayRef<const uint8_t>(expected_asm), actual_asm);
105 EXPECT_EQ(ArrayRef<const uint8_t>(expected_cfi), actual_cfi);
106 }
107 }
108
TestImpl(InstructionSet isa,const char * isa_str,const std::vector<uint8_t> & expected_asm,const std::vector<uint8_t> & expected_cfi)109 void TestImpl(InstructionSet isa, const char*
110 isa_str,
111 const std::vector<uint8_t>& expected_asm,
112 const std::vector<uint8_t>& expected_cfi) {
113 SetUpFrame(isa);
114 Finish();
115 Check(isa, isa_str, expected_asm, expected_cfi);
116 }
117
GetCodeGenerator()118 CodeGenerator* GetCodeGenerator() {
119 return code_gen_.get();
120 }
121
122 private:
123 HGraph* graph_;
124 std::unique_ptr<CodeGenerator> code_gen_;
125 ArenaVector<HBasicBlock*> blocks_;
126 };
127
128 #define TEST_ISA(isa) \
129 TEST_F(OptimizingCFITest, isa) { \
130 std::vector<uint8_t> expected_asm( \
131 expected_asm_##isa, \
132 expected_asm_##isa + arraysize(expected_asm_##isa)); \
133 std::vector<uint8_t> expected_cfi( \
134 expected_cfi_##isa, \
135 expected_cfi_##isa + arraysize(expected_cfi_##isa)); \
136 TestImpl(InstructionSet::isa, #isa, expected_asm, expected_cfi); \
137 }
138
139 #ifdef ART_ENABLE_CODEGEN_arm
140 TEST_ISA(kThumb2)
141 #endif
142
143 #ifdef ART_ENABLE_CODEGEN_arm64
144 // Run the tests for ARM64 only if the Marking Register is reserved as the
145 // expected generated code saves and restore X21 and X22 (instead of
146 // X20 and X21), as X20 is used as Marking Register in the Baker read
147 // barrier configuration, and as such is removed from the set of
148 // callee-save registers in the ARM64 code generator of the Optimizing
149 // compiler.
150 #if defined(RESERVE_MARKING_REGISTER)
TEST_ISA(kArm64)151 TEST_ISA(kArm64)
152 #endif
153 #endif
154
155 #ifdef ART_ENABLE_CODEGEN_x86
156 TEST_ISA(kX86)
157 #endif
158
159 #ifdef ART_ENABLE_CODEGEN_x86_64
160 TEST_ISA(kX86_64)
161 #endif
162
163 #ifdef ART_ENABLE_CODEGEN_arm
164 TEST_F(OptimizingCFITest, kThumb2Adjust) {
165 using vixl32::r0;
166 std::vector<uint8_t> expected_asm(
167 expected_asm_kThumb2_adjust,
168 expected_asm_kThumb2_adjust + arraysize(expected_asm_kThumb2_adjust));
169 std::vector<uint8_t> expected_cfi(
170 expected_cfi_kThumb2_adjust,
171 expected_cfi_kThumb2_adjust + arraysize(expected_cfi_kThumb2_adjust));
172 SetUpFrame(InstructionSet::kThumb2);
173 #define __ down_cast<arm::ArmVIXLAssembler*>(GetCodeGenerator() \
174 ->GetAssembler())->GetVIXLAssembler()->
175 vixl32::Label target;
176 __ CompareAndBranchIfZero(r0, &target);
177 // Push the target out of range of CBZ.
178 for (size_t i = 0; i != 65; ++i) {
179 __ Ldr(r0, vixl32::MemOperand(r0));
180 }
181 __ Bind(&target);
182 #undef __
183 Finish();
184 Check(InstructionSet::kThumb2, "kThumb2_adjust", expected_asm, expected_cfi);
185 }
186 #endif
187
188 } // namespace art
189