1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __LINUX_KVM_RISCV_H 8 #define __LINUX_KVM_RISCV_H 9 #ifndef __ASSEMBLY__ 10 #include <linux/types.h> 11 #include <asm/bitsperlong.h> 12 #include <asm/ptrace.h> 13 #define __KVM_HAVE_IRQ_LINE 14 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 15 #define KVM_INTERRUPT_SET - 1U 16 #define KVM_INTERRUPT_UNSET - 2U 17 struct kvm_regs { 18 }; 19 struct kvm_fpu { 20 }; 21 struct kvm_debug_exit_arch { 22 }; 23 struct kvm_guest_debug_arch { 24 }; 25 struct kvm_sync_regs { 26 }; 27 struct kvm_sregs { 28 }; 29 struct kvm_riscv_config { 30 unsigned long isa; 31 unsigned long zicbom_block_size; 32 unsigned long mvendorid; 33 unsigned long marchid; 34 unsigned long mimpid; 35 unsigned long zicboz_block_size; 36 unsigned long satp_mode; 37 }; 38 struct kvm_riscv_core { 39 struct user_regs_struct regs; 40 unsigned long mode; 41 }; 42 #define KVM_RISCV_MODE_S 1 43 #define KVM_RISCV_MODE_U 0 44 struct kvm_riscv_csr { 45 unsigned long sstatus; 46 unsigned long sie; 47 unsigned long stvec; 48 unsigned long sscratch; 49 unsigned long sepc; 50 unsigned long scause; 51 unsigned long stval; 52 unsigned long sip; 53 unsigned long satp; 54 unsigned long scounteren; 55 unsigned long senvcfg; 56 }; 57 struct kvm_riscv_aia_csr { 58 unsigned long siselect; 59 unsigned long iprio1; 60 unsigned long iprio2; 61 unsigned long sieh; 62 unsigned long siph; 63 unsigned long iprio1h; 64 unsigned long iprio2h; 65 }; 66 struct kvm_riscv_smstateen_csr { 67 unsigned long sstateen0; 68 }; 69 struct kvm_riscv_timer { 70 __u64 frequency; 71 __u64 time; 72 __u64 compare; 73 __u64 state; 74 }; 75 enum KVM_RISCV_ISA_EXT_ID { 76 KVM_RISCV_ISA_EXT_A = 0, 77 KVM_RISCV_ISA_EXT_C, 78 KVM_RISCV_ISA_EXT_D, 79 KVM_RISCV_ISA_EXT_F, 80 KVM_RISCV_ISA_EXT_H, 81 KVM_RISCV_ISA_EXT_I, 82 KVM_RISCV_ISA_EXT_M, 83 KVM_RISCV_ISA_EXT_SVPBMT, 84 KVM_RISCV_ISA_EXT_SSTC, 85 KVM_RISCV_ISA_EXT_SVINVAL, 86 KVM_RISCV_ISA_EXT_ZIHINTPAUSE, 87 KVM_RISCV_ISA_EXT_ZICBOM, 88 KVM_RISCV_ISA_EXT_ZICBOZ, 89 KVM_RISCV_ISA_EXT_ZBB, 90 KVM_RISCV_ISA_EXT_SSAIA, 91 KVM_RISCV_ISA_EXT_V, 92 KVM_RISCV_ISA_EXT_SVNAPOT, 93 KVM_RISCV_ISA_EXT_ZBA, 94 KVM_RISCV_ISA_EXT_ZBS, 95 KVM_RISCV_ISA_EXT_ZICNTR, 96 KVM_RISCV_ISA_EXT_ZICSR, 97 KVM_RISCV_ISA_EXT_ZIFENCEI, 98 KVM_RISCV_ISA_EXT_ZIHPM, 99 KVM_RISCV_ISA_EXT_SMSTATEEN, 100 KVM_RISCV_ISA_EXT_ZICOND, 101 KVM_RISCV_ISA_EXT_ZBC, 102 KVM_RISCV_ISA_EXT_ZBKB, 103 KVM_RISCV_ISA_EXT_ZBKC, 104 KVM_RISCV_ISA_EXT_ZBKX, 105 KVM_RISCV_ISA_EXT_ZKND, 106 KVM_RISCV_ISA_EXT_ZKNE, 107 KVM_RISCV_ISA_EXT_ZKNH, 108 KVM_RISCV_ISA_EXT_ZKR, 109 KVM_RISCV_ISA_EXT_ZKSED, 110 KVM_RISCV_ISA_EXT_ZKSH, 111 KVM_RISCV_ISA_EXT_ZKT, 112 KVM_RISCV_ISA_EXT_ZVBB, 113 KVM_RISCV_ISA_EXT_ZVBC, 114 KVM_RISCV_ISA_EXT_ZVKB, 115 KVM_RISCV_ISA_EXT_ZVKG, 116 KVM_RISCV_ISA_EXT_ZVKNED, 117 KVM_RISCV_ISA_EXT_ZVKNHA, 118 KVM_RISCV_ISA_EXT_ZVKNHB, 119 KVM_RISCV_ISA_EXT_ZVKSED, 120 KVM_RISCV_ISA_EXT_ZVKSH, 121 KVM_RISCV_ISA_EXT_ZVKT, 122 KVM_RISCV_ISA_EXT_ZFH, 123 KVM_RISCV_ISA_EXT_ZFHMIN, 124 KVM_RISCV_ISA_EXT_ZIHINTNTL, 125 KVM_RISCV_ISA_EXT_ZVFH, 126 KVM_RISCV_ISA_EXT_ZVFHMIN, 127 KVM_RISCV_ISA_EXT_ZFA, 128 KVM_RISCV_ISA_EXT_ZTSO, 129 KVM_RISCV_ISA_EXT_ZACAS, 130 KVM_RISCV_ISA_EXT_MAX, 131 }; 132 enum KVM_RISCV_SBI_EXT_ID { 133 KVM_RISCV_SBI_EXT_V01 = 0, 134 KVM_RISCV_SBI_EXT_TIME, 135 KVM_RISCV_SBI_EXT_IPI, 136 KVM_RISCV_SBI_EXT_RFENCE, 137 KVM_RISCV_SBI_EXT_SRST, 138 KVM_RISCV_SBI_EXT_HSM, 139 KVM_RISCV_SBI_EXT_PMU, 140 KVM_RISCV_SBI_EXT_EXPERIMENTAL, 141 KVM_RISCV_SBI_EXT_VENDOR, 142 KVM_RISCV_SBI_EXT_DBCN, 143 KVM_RISCV_SBI_EXT_STA, 144 KVM_RISCV_SBI_EXT_MAX, 145 }; 146 struct kvm_riscv_sbi_sta { 147 unsigned long shmem_lo; 148 unsigned long shmem_hi; 149 }; 150 #define KVM_RISCV_TIMER_STATE_OFF 0 151 #define KVM_RISCV_TIMER_STATE_ON 1 152 #define KVM_REG_SIZE(id) (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) 153 #define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000 154 #define KVM_REG_RISCV_TYPE_SHIFT 24 155 #define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000 156 #define KVM_REG_RISCV_SUBTYPE_SHIFT 16 157 #define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT) 158 #define KVM_REG_RISCV_CONFIG_REG(name) (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long)) 159 #define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT) 160 #define KVM_REG_RISCV_CORE_REG(name) (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long)) 161 #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) 162 #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 163 #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 164 #define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 165 #define KVM_REG_RISCV_CSR_REG(name) (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) 166 #define KVM_REG_RISCV_CSR_AIA_REG(name) (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) 167 #define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) (offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long)) 168 #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) 169 #define KVM_REG_RISCV_TIMER_REG(name) (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64)) 170 #define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT) 171 #define KVM_REG_RISCV_FP_F_REG(name) (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32)) 172 #define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT) 173 #define KVM_REG_RISCV_FP_D_REG(name) (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64)) 174 #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) 175 #define KVM_REG_RISCV_ISA_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 176 #define KVM_REG_RISCV_ISA_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 177 #define KVM_REG_RISCV_ISA_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 178 #define KVM_REG_RISCV_ISA_MULTI_REG(__ext_id) ((__ext_id) / __BITS_PER_LONG) 179 #define KVM_REG_RISCV_ISA_MULTI_MASK(__ext_id) (1UL << ((__ext_id) % __BITS_PER_LONG)) 180 #define KVM_REG_RISCV_ISA_MULTI_REG_LAST KVM_REG_RISCV_ISA_MULTI_REG(KVM_RISCV_ISA_EXT_MAX - 1) 181 #define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT) 182 #define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 183 #define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) 184 #define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) 185 #define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) ((__ext_id) / __BITS_PER_LONG) 186 #define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) (1UL << ((__ext_id) % __BITS_PER_LONG)) 187 #define KVM_REG_RISCV_SBI_MULTI_REG_LAST KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1) 188 #define KVM_REG_RISCV_VECTOR (0x09 << KVM_REG_RISCV_TYPE_SHIFT) 189 #define KVM_REG_RISCV_VECTOR_CSR_REG(name) (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long)) 190 #define KVM_REG_RISCV_VECTOR_REG(n) ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long)) 191 #define KVM_REG_RISCV_SBI_STATE (0x0a << KVM_REG_RISCV_TYPE_SHIFT) 192 #define KVM_REG_RISCV_SBI_STA (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) 193 #define KVM_REG_RISCV_SBI_STA_REG(name) (offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long)) 194 #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000 195 #define KVM_DEV_RISCV_APLIC_SIZE 0x4000 196 #define KVM_DEV_RISCV_APLIC_MAX_HARTS 0x4000 197 #define KVM_DEV_RISCV_IMSIC_ALIGN 0x1000 198 #define KVM_DEV_RISCV_IMSIC_SIZE 0x1000 199 #define KVM_DEV_RISCV_AIA_GRP_CONFIG 0 200 #define KVM_DEV_RISCV_AIA_CONFIG_MODE 0 201 #define KVM_DEV_RISCV_AIA_CONFIG_IDS 1 202 #define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2 203 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3 204 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4 205 #define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5 206 #define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6 207 #define KVM_DEV_RISCV_AIA_MODE_EMUL 0 208 #define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1 209 #define KVM_DEV_RISCV_AIA_MODE_AUTO 2 210 #define KVM_DEV_RISCV_AIA_IDS_MIN 63 211 #define KVM_DEV_RISCV_AIA_IDS_MAX 2048 212 #define KVM_DEV_RISCV_AIA_SRCS_MAX 1024 213 #define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8 214 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24 215 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56 216 #define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16 217 #define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8 218 #define KVM_DEV_RISCV_AIA_GRP_ADDR 1 219 #define KVM_DEV_RISCV_AIA_ADDR_APLIC 0 220 #define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu)) 221 #define KVM_DEV_RISCV_AIA_ADDR_MAX (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS) 222 #define KVM_DEV_RISCV_AIA_GRP_CTRL 2 223 #define KVM_DEV_RISCV_AIA_CTRL_INIT 0 224 #define KVM_DEV_RISCV_AIA_GRP_APLIC 3 225 #define KVM_DEV_RISCV_AIA_GRP_IMSIC 4 226 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS 12 227 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1) 228 #define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu,__isel) (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)) 229 #define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr) ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK) 230 #define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr) ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) 231 #define KVM_NR_IRQCHIPS 1 232 #endif 233 #endif 234