1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __AMDGPU_DRM_H__ 8 #define __AMDGPU_DRM_H__ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #define DRM_AMDGPU_GEM_CREATE 0x00 14 #define DRM_AMDGPU_GEM_MMAP 0x01 15 #define DRM_AMDGPU_CTX 0x02 16 #define DRM_AMDGPU_BO_LIST 0x03 17 #define DRM_AMDGPU_CS 0x04 18 #define DRM_AMDGPU_INFO 0x05 19 #define DRM_AMDGPU_GEM_METADATA 0x06 20 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 21 #define DRM_AMDGPU_GEM_VA 0x08 22 #define DRM_AMDGPU_WAIT_CS 0x09 23 #define DRM_AMDGPU_GEM_OP 0x10 24 #define DRM_AMDGPU_GEM_USERPTR 0x11 25 #define DRM_AMDGPU_WAIT_FENCES 0x12 26 #define DRM_AMDGPU_VM 0x13 27 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 28 #define DRM_AMDGPU_SCHED 0x15 29 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 30 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 31 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 32 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 33 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 34 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 35 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 36 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 37 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 38 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 39 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 40 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 41 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 42 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 43 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 44 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 45 #define AMDGPU_GEM_DOMAIN_CPU 0x1 46 #define AMDGPU_GEM_DOMAIN_GTT 0x2 47 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 48 #define AMDGPU_GEM_DOMAIN_GDS 0x8 49 #define AMDGPU_GEM_DOMAIN_GWS 0x10 50 #define AMDGPU_GEM_DOMAIN_OA 0x20 51 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 52 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | AMDGPU_GEM_DOMAIN_DOORBELL) 53 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 54 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 55 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 56 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 57 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 58 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 59 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 60 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 61 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 62 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 63 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 64 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 65 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 66 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 67 #define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15) 68 struct drm_amdgpu_gem_create_in { 69 __u64 bo_size; 70 __u64 alignment; 71 __u64 domains; 72 __u64 domain_flags; 73 }; 74 struct drm_amdgpu_gem_create_out { 75 __u32 handle; 76 __u32 _pad; 77 }; 78 union drm_amdgpu_gem_create { 79 struct drm_amdgpu_gem_create_in in; 80 struct drm_amdgpu_gem_create_out out; 81 }; 82 #define AMDGPU_BO_LIST_OP_CREATE 0 83 #define AMDGPU_BO_LIST_OP_DESTROY 1 84 #define AMDGPU_BO_LIST_OP_UPDATE 2 85 struct drm_amdgpu_bo_list_in { 86 __u32 operation; 87 __u32 list_handle; 88 __u32 bo_number; 89 __u32 bo_info_size; 90 __u64 bo_info_ptr; 91 }; 92 struct drm_amdgpu_bo_list_entry { 93 __u32 bo_handle; 94 __u32 bo_priority; 95 }; 96 struct drm_amdgpu_bo_list_out { 97 __u32 list_handle; 98 __u32 _pad; 99 }; 100 union drm_amdgpu_bo_list { 101 struct drm_amdgpu_bo_list_in in; 102 struct drm_amdgpu_bo_list_out out; 103 }; 104 #define AMDGPU_CTX_OP_ALLOC_CTX 1 105 #define AMDGPU_CTX_OP_FREE_CTX 2 106 #define AMDGPU_CTX_OP_QUERY_STATE 3 107 #define AMDGPU_CTX_OP_QUERY_STATE2 4 108 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 109 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 110 #define AMDGPU_CTX_NO_RESET 0 111 #define AMDGPU_CTX_GUILTY_RESET 1 112 #define AMDGPU_CTX_INNOCENT_RESET 2 113 #define AMDGPU_CTX_UNKNOWN_RESET 3 114 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1 << 0) 115 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1 << 1) 116 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1 << 2) 117 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1 << 3) 118 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1 << 4) 119 #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1 << 5) 120 #define AMDGPU_CTX_PRIORITY_UNSET - 2048 121 #define AMDGPU_CTX_PRIORITY_VERY_LOW - 1023 122 #define AMDGPU_CTX_PRIORITY_LOW - 512 123 #define AMDGPU_CTX_PRIORITY_NORMAL 0 124 #define AMDGPU_CTX_PRIORITY_HIGH 512 125 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 126 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 127 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 128 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 129 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 130 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 131 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 132 struct drm_amdgpu_ctx_in { 133 __u32 op; 134 __u32 flags; 135 __u32 ctx_id; 136 __s32 priority; 137 }; 138 union drm_amdgpu_ctx_out { 139 struct { 140 __u32 ctx_id; 141 __u32 _pad; 142 } alloc; 143 struct { 144 __u64 flags; 145 __u32 hangs; 146 __u32 reset_status; 147 } state; 148 struct { 149 __u32 flags; 150 __u32 _pad; 151 } pstate; 152 }; 153 union drm_amdgpu_ctx { 154 struct drm_amdgpu_ctx_in in; 155 union drm_amdgpu_ctx_out out; 156 }; 157 #define AMDGPU_VM_OP_RESERVE_VMID 1 158 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 159 struct drm_amdgpu_vm_in { 160 __u32 op; 161 __u32 flags; 162 }; 163 struct drm_amdgpu_vm_out { 164 __u64 flags; 165 }; 166 union drm_amdgpu_vm { 167 struct drm_amdgpu_vm_in in; 168 struct drm_amdgpu_vm_out out; 169 }; 170 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 171 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 172 struct drm_amdgpu_sched_in { 173 __u32 op; 174 __u32 fd; 175 __s32 priority; 176 __u32 ctx_id; 177 }; 178 union drm_amdgpu_sched { 179 struct drm_amdgpu_sched_in in; 180 }; 181 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 182 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 183 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 184 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 185 struct drm_amdgpu_gem_userptr { 186 __u64 addr; 187 __u64 size; 188 __u32 flags; 189 __u32 handle; 190 }; 191 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 192 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 193 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 194 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 195 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 196 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 197 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 198 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 199 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 200 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 201 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 202 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 203 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 204 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 205 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 206 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 207 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 208 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 209 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 210 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 211 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 212 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 213 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 214 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 215 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 216 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 217 #define AMDGPU_TILING_SCANOUT_SHIFT 63 218 #define AMDGPU_TILING_SCANOUT_MASK 0x1 219 #define AMDGPU_TILING_SET(field,value) (((__u64) (value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT) 220 #define AMDGPU_TILING_GET(value,field) (((__u64) (value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK) 221 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 222 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 223 struct drm_amdgpu_gem_metadata { 224 __u32 handle; 225 __u32 op; 226 struct { 227 __u64 flags; 228 __u64 tiling_info; 229 __u32 data_size_bytes; 230 __u32 data[64]; 231 } data; 232 }; 233 struct drm_amdgpu_gem_mmap_in { 234 __u32 handle; 235 __u32 _pad; 236 }; 237 struct drm_amdgpu_gem_mmap_out { 238 __u64 addr_ptr; 239 }; 240 union drm_amdgpu_gem_mmap { 241 struct drm_amdgpu_gem_mmap_in in; 242 struct drm_amdgpu_gem_mmap_out out; 243 }; 244 struct drm_amdgpu_gem_wait_idle_in { 245 __u32 handle; 246 __u32 flags; 247 __u64 timeout; 248 }; 249 struct drm_amdgpu_gem_wait_idle_out { 250 __u32 status; 251 __u32 domain; 252 }; 253 union drm_amdgpu_gem_wait_idle { 254 struct drm_amdgpu_gem_wait_idle_in in; 255 struct drm_amdgpu_gem_wait_idle_out out; 256 }; 257 struct drm_amdgpu_wait_cs_in { 258 __u64 handle; 259 __u64 timeout; 260 __u32 ip_type; 261 __u32 ip_instance; 262 __u32 ring; 263 __u32 ctx_id; 264 }; 265 struct drm_amdgpu_wait_cs_out { 266 __u64 status; 267 }; 268 union drm_amdgpu_wait_cs { 269 struct drm_amdgpu_wait_cs_in in; 270 struct drm_amdgpu_wait_cs_out out; 271 }; 272 struct drm_amdgpu_fence { 273 __u32 ctx_id; 274 __u32 ip_type; 275 __u32 ip_instance; 276 __u32 ring; 277 __u64 seq_no; 278 }; 279 struct drm_amdgpu_wait_fences_in { 280 __u64 fences; 281 __u32 fence_count; 282 __u32 wait_all; 283 __u64 timeout_ns; 284 }; 285 struct drm_amdgpu_wait_fences_out { 286 __u32 status; 287 __u32 first_signaled; 288 }; 289 union drm_amdgpu_wait_fences { 290 struct drm_amdgpu_wait_fences_in in; 291 struct drm_amdgpu_wait_fences_out out; 292 }; 293 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 294 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 295 struct drm_amdgpu_gem_op { 296 __u32 handle; 297 __u32 op; 298 __u64 value; 299 }; 300 #define AMDGPU_VA_OP_MAP 1 301 #define AMDGPU_VA_OP_UNMAP 2 302 #define AMDGPU_VA_OP_CLEAR 3 303 #define AMDGPU_VA_OP_REPLACE 4 304 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 305 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 306 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 307 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 308 #define AMDGPU_VM_PAGE_PRT (1 << 4) 309 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 310 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 311 #define AMDGPU_VM_MTYPE_NC (1 << 5) 312 #define AMDGPU_VM_MTYPE_WC (2 << 5) 313 #define AMDGPU_VM_MTYPE_CC (3 << 5) 314 #define AMDGPU_VM_MTYPE_UC (4 << 5) 315 #define AMDGPU_VM_MTYPE_RW (5 << 5) 316 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 317 struct drm_amdgpu_gem_va { 318 __u32 handle; 319 __u32 _pad; 320 __u32 operation; 321 __u32 flags; 322 __u64 va_address; 323 __u64 offset_in_bo; 324 __u64 map_size; 325 }; 326 #define AMDGPU_HW_IP_GFX 0 327 #define AMDGPU_HW_IP_COMPUTE 1 328 #define AMDGPU_HW_IP_DMA 2 329 #define AMDGPU_HW_IP_UVD 3 330 #define AMDGPU_HW_IP_VCE 4 331 #define AMDGPU_HW_IP_UVD_ENC 5 332 #define AMDGPU_HW_IP_VCN_DEC 6 333 #define AMDGPU_HW_IP_VCN_ENC 7 334 #define AMDGPU_HW_IP_VCN_JPEG 8 335 #define AMDGPU_HW_IP_VPE 9 336 #define AMDGPU_HW_IP_NUM 10 337 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 338 #define AMDGPU_CHUNK_ID_IB 0x01 339 #define AMDGPU_CHUNK_ID_FENCE 0x02 340 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 341 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 342 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 343 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 344 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 345 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 346 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 347 #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 348 struct drm_amdgpu_cs_chunk { 349 __u32 chunk_id; 350 __u32 length_dw; 351 __u64 chunk_data; 352 }; 353 struct drm_amdgpu_cs_in { 354 __u32 ctx_id; 355 __u32 bo_list_handle; 356 __u32 num_chunks; 357 __u32 flags; 358 __u64 chunks; 359 }; 360 struct drm_amdgpu_cs_out { 361 __u64 handle; 362 }; 363 union drm_amdgpu_cs { 364 struct drm_amdgpu_cs_in in; 365 struct drm_amdgpu_cs_out out; 366 }; 367 #define AMDGPU_IB_FLAG_CE (1 << 0) 368 #define AMDGPU_IB_FLAG_PREAMBLE (1 << 1) 369 #define AMDGPU_IB_FLAG_PREEMPT (1 << 2) 370 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 371 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 372 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 373 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 374 struct drm_amdgpu_cs_chunk_ib { 375 __u32 _pad; 376 __u32 flags; 377 __u64 va_start; 378 __u32 ib_bytes; 379 __u32 ip_type; 380 __u32 ip_instance; 381 __u32 ring; 382 }; 383 struct drm_amdgpu_cs_chunk_dep { 384 __u32 ip_type; 385 __u32 ip_instance; 386 __u32 ring; 387 __u32 ctx_id; 388 __u64 handle; 389 }; 390 struct drm_amdgpu_cs_chunk_fence { 391 __u32 handle; 392 __u32 offset; 393 }; 394 struct drm_amdgpu_cs_chunk_sem { 395 __u32 handle; 396 }; 397 struct drm_amdgpu_cs_chunk_syncobj { 398 __u32 handle; 399 __u32 flags; 400 __u64 point; 401 }; 402 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 403 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 404 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 405 union drm_amdgpu_fence_to_handle { 406 struct { 407 struct drm_amdgpu_fence fence; 408 __u32 what; 409 __u32 pad; 410 } in; 411 struct { 412 __u32 handle; 413 } out; 414 }; 415 struct drm_amdgpu_cs_chunk_data { 416 union { 417 struct drm_amdgpu_cs_chunk_ib ib_data; 418 struct drm_amdgpu_cs_chunk_fence fence_data; 419 }; 420 }; 421 #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 422 struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 423 __u64 shadow_va; 424 __u64 csa_va; 425 __u64 gds_va; 426 __u64 flags; 427 }; 428 #define AMDGPU_IDS_FLAGS_FUSION 0x1 429 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 430 #define AMDGPU_IDS_FLAGS_TMZ 0x4 431 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 432 #define AMDGPU_INFO_ACCEL_WORKING 0x00 433 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 434 #define AMDGPU_INFO_HW_IP_INFO 0x02 435 #define AMDGPU_INFO_HW_IP_COUNT 0x03 436 #define AMDGPU_INFO_TIMESTAMP 0x05 437 #define AMDGPU_INFO_FW_VERSION 0x0e 438 #define AMDGPU_INFO_FW_VCE 0x1 439 #define AMDGPU_INFO_FW_UVD 0x2 440 #define AMDGPU_INFO_FW_GMC 0x03 441 #define AMDGPU_INFO_FW_GFX_ME 0x04 442 #define AMDGPU_INFO_FW_GFX_PFP 0x05 443 #define AMDGPU_INFO_FW_GFX_CE 0x06 444 #define AMDGPU_INFO_FW_GFX_RLC 0x07 445 #define AMDGPU_INFO_FW_GFX_MEC 0x08 446 #define AMDGPU_INFO_FW_SMC 0x0a 447 #define AMDGPU_INFO_FW_SDMA 0x0b 448 #define AMDGPU_INFO_FW_SOS 0x0c 449 #define AMDGPU_INFO_FW_ASD 0x0d 450 #define AMDGPU_INFO_FW_VCN 0x0e 451 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 452 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 453 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 454 #define AMDGPU_INFO_FW_DMCU 0x12 455 #define AMDGPU_INFO_FW_TA 0x13 456 #define AMDGPU_INFO_FW_DMCUB 0x14 457 #define AMDGPU_INFO_FW_TOC 0x15 458 #define AMDGPU_INFO_FW_CAP 0x16 459 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 460 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 461 #define AMDGPU_INFO_FW_MES_KIQ 0x19 462 #define AMDGPU_INFO_FW_MES 0x1a 463 #define AMDGPU_INFO_FW_IMU 0x1b 464 #define AMDGPU_INFO_FW_VPE 0x1c 465 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 466 #define AMDGPU_INFO_VRAM_USAGE 0x10 467 #define AMDGPU_INFO_GTT_USAGE 0x11 468 #define AMDGPU_INFO_GDS_CONFIG 0x13 469 #define AMDGPU_INFO_VRAM_GTT 0x14 470 #define AMDGPU_INFO_READ_MMR_REG 0x15 471 #define AMDGPU_INFO_DEV_INFO 0x16 472 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 473 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 474 #define AMDGPU_INFO_MEMORY 0x19 475 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 476 #define AMDGPU_INFO_VBIOS 0x1B 477 #define AMDGPU_INFO_VBIOS_SIZE 0x1 478 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 479 #define AMDGPU_INFO_VBIOS_INFO 0x3 480 #define AMDGPU_INFO_NUM_HANDLES 0x1C 481 #define AMDGPU_INFO_SENSOR 0x1D 482 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 483 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 484 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 485 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 486 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 487 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 488 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 489 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 490 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 491 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 492 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 493 #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc 494 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 495 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 496 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 497 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 498 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 499 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 500 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 501 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 502 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 503 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 504 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 505 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 506 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 507 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 508 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 509 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 510 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 511 #define AMDGPU_INFO_VIDEO_CAPS 0x21 512 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 513 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 514 #define AMDGPU_INFO_MAX_IBS 0x22 515 #define AMDGPU_INFO_GPUVM_FAULT 0x23 516 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 517 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 518 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 519 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 520 struct drm_amdgpu_query_fw { 521 __u32 fw_type; 522 __u32 ip_instance; 523 __u32 index; 524 __u32 _pad; 525 }; 526 struct drm_amdgpu_info { 527 __u64 return_pointer; 528 __u32 return_size; 529 __u32 query; 530 union { 531 struct { 532 __u32 id; 533 __u32 _pad; 534 } mode_crtc; 535 struct { 536 __u32 type; 537 __u32 ip_instance; 538 } query_hw_ip; 539 struct { 540 __u32 dword_offset; 541 __u32 count; 542 __u32 instance; 543 __u32 flags; 544 } read_mmr_reg; 545 struct drm_amdgpu_query_fw query_fw; 546 struct { 547 __u32 type; 548 __u32 offset; 549 } vbios_info; 550 struct { 551 __u32 type; 552 } sensor_info; 553 struct { 554 __u32 type; 555 } video_cap; 556 }; 557 }; 558 struct drm_amdgpu_info_gds { 559 __u32 gds_gfx_partition_size; 560 __u32 compute_partition_size; 561 __u32 gds_total_size; 562 __u32 gws_per_gfx_partition; 563 __u32 gws_per_compute_partition; 564 __u32 oa_per_gfx_partition; 565 __u32 oa_per_compute_partition; 566 __u32 _pad; 567 }; 568 struct drm_amdgpu_info_vram_gtt { 569 __u64 vram_size; 570 __u64 vram_cpu_accessible_size; 571 __u64 gtt_size; 572 }; 573 struct drm_amdgpu_heap_info { 574 __u64 total_heap_size; 575 __u64 usable_heap_size; 576 __u64 heap_usage; 577 __u64 max_allocation; 578 }; 579 struct drm_amdgpu_memory_info { 580 struct drm_amdgpu_heap_info vram; 581 struct drm_amdgpu_heap_info cpu_accessible_vram; 582 struct drm_amdgpu_heap_info gtt; 583 }; 584 struct drm_amdgpu_info_firmware { 585 __u32 ver; 586 __u32 feature; 587 }; 588 struct drm_amdgpu_info_vbios { 589 __u8 name[64]; 590 __u8 vbios_pn[64]; 591 __u32 version; 592 __u32 pad; 593 __u8 vbios_ver_str[32]; 594 __u8 date[32]; 595 }; 596 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 597 #define AMDGPU_VRAM_TYPE_GDDR1 1 598 #define AMDGPU_VRAM_TYPE_DDR2 2 599 #define AMDGPU_VRAM_TYPE_GDDR3 3 600 #define AMDGPU_VRAM_TYPE_GDDR4 4 601 #define AMDGPU_VRAM_TYPE_GDDR5 5 602 #define AMDGPU_VRAM_TYPE_HBM 6 603 #define AMDGPU_VRAM_TYPE_DDR3 7 604 #define AMDGPU_VRAM_TYPE_DDR4 8 605 #define AMDGPU_VRAM_TYPE_GDDR6 9 606 #define AMDGPU_VRAM_TYPE_DDR5 10 607 #define AMDGPU_VRAM_TYPE_LPDDR4 11 608 #define AMDGPU_VRAM_TYPE_LPDDR5 12 609 struct drm_amdgpu_info_device { 610 __u32 device_id; 611 __u32 chip_rev; 612 __u32 external_rev; 613 __u32 pci_rev; 614 __u32 family; 615 __u32 num_shader_engines; 616 __u32 num_shader_arrays_per_engine; 617 __u32 gpu_counter_freq; 618 __u64 max_engine_clock; 619 __u64 max_memory_clock; 620 __u32 cu_active_number; 621 __u32 cu_ao_mask; 622 __u32 cu_bitmap[4][4]; 623 __u32 enabled_rb_pipes_mask; 624 __u32 num_rb_pipes; 625 __u32 num_hw_gfx_contexts; 626 __u32 pcie_gen; 627 __u64 ids_flags; 628 __u64 virtual_address_offset; 629 __u64 virtual_address_max; 630 __u32 virtual_address_alignment; 631 __u32 pte_fragment_size; 632 __u32 gart_page_size; 633 __u32 ce_ram_size; 634 __u32 vram_type; 635 __u32 vram_bit_width; 636 __u32 vce_harvest_config; 637 __u32 gc_double_offchip_lds_buf; 638 __u64 prim_buf_gpu_addr; 639 __u64 pos_buf_gpu_addr; 640 __u64 cntl_sb_buf_gpu_addr; 641 __u64 param_buf_gpu_addr; 642 __u32 prim_buf_size; 643 __u32 pos_buf_size; 644 __u32 cntl_sb_buf_size; 645 __u32 param_buf_size; 646 __u32 wave_front_size; 647 __u32 num_shader_visible_vgprs; 648 __u32 num_cu_per_sh; 649 __u32 num_tcc_blocks; 650 __u32 gs_vgt_table_depth; 651 __u32 gs_prim_buffer_depth; 652 __u32 max_gs_waves_per_vgt; 653 __u32 pcie_num_lanes; 654 __u32 cu_ao_bitmap[4][4]; 655 __u64 high_va_offset; 656 __u64 high_va_max; 657 __u32 pa_sc_tile_steering_override; 658 __u64 tcc_disabled_mask; 659 __u64 min_engine_clock; 660 __u64 min_memory_clock; 661 __u32 tcp_cache_size; 662 __u32 num_sqc_per_wgp; 663 __u32 sqc_data_cache_size; 664 __u32 sqc_inst_cache_size; 665 __u32 gl1c_cache_size; 666 __u32 gl2c_cache_size; 667 __u64 mall_size; 668 __u32 enabled_rb_pipes_mask_hi; 669 __u32 shadow_size; 670 __u32 shadow_alignment; 671 __u32 csa_size; 672 __u32 csa_alignment; 673 }; 674 struct drm_amdgpu_info_hw_ip { 675 __u32 hw_ip_version_major; 676 __u32 hw_ip_version_minor; 677 __u64 capabilities_flags; 678 __u32 ib_start_alignment; 679 __u32 ib_size_alignment; 680 __u32 available_rings; 681 __u32 ip_discovery_version; 682 }; 683 struct drm_amdgpu_info_num_handles { 684 __u32 uvd_max_handles; 685 __u32 uvd_used_handles; 686 }; 687 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 688 struct drm_amdgpu_info_vce_clock_table_entry { 689 __u32 sclk; 690 __u32 mclk; 691 __u32 eclk; 692 __u32 pad; 693 }; 694 struct drm_amdgpu_info_vce_clock_table { 695 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 696 __u32 num_valid_entries; 697 __u32 pad; 698 }; 699 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 700 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 701 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 702 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 703 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 704 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 705 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 706 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 707 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 708 struct drm_amdgpu_info_video_codec_info { 709 __u32 valid; 710 __u32 max_width; 711 __u32 max_height; 712 __u32 max_pixels_per_frame; 713 __u32 max_level; 714 __u32 pad; 715 }; 716 struct drm_amdgpu_info_video_caps { 717 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 718 }; 719 #define AMDGPU_VMHUB_TYPE_MASK 0xff 720 #define AMDGPU_VMHUB_TYPE_SHIFT 0 721 #define AMDGPU_VMHUB_TYPE_GFX 0 722 #define AMDGPU_VMHUB_TYPE_MM0 1 723 #define AMDGPU_VMHUB_TYPE_MM1 2 724 #define AMDGPU_VMHUB_IDX_MASK 0xff00 725 #define AMDGPU_VMHUB_IDX_SHIFT 8 726 struct drm_amdgpu_info_gpuvm_fault { 727 __u64 addr; 728 __u32 status; 729 __u32 vmhub; 730 }; 731 #define AMDGPU_FAMILY_UNKNOWN 0 732 #define AMDGPU_FAMILY_SI 110 733 #define AMDGPU_FAMILY_CI 120 734 #define AMDGPU_FAMILY_KV 125 735 #define AMDGPU_FAMILY_VI 130 736 #define AMDGPU_FAMILY_CZ 135 737 #define AMDGPU_FAMILY_AI 141 738 #define AMDGPU_FAMILY_RV 142 739 #define AMDGPU_FAMILY_NV 143 740 #define AMDGPU_FAMILY_VGH 144 741 #define AMDGPU_FAMILY_GC_11_0_0 145 742 #define AMDGPU_FAMILY_YC 146 743 #define AMDGPU_FAMILY_GC_11_0_1 148 744 #define AMDGPU_FAMILY_GC_10_3_6 149 745 #define AMDGPU_FAMILY_GC_10_3_7 151 746 #define AMDGPU_FAMILY_GC_11_5_0 150 747 #ifdef __cplusplus 748 } 749 #endif 750 #endif 751