1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __LIMA_DRM_H__ 8 #define __LIMA_DRM_H__ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 enum drm_lima_param_gpu_id { 14 DRM_LIMA_PARAM_GPU_ID_UNKNOWN, 15 DRM_LIMA_PARAM_GPU_ID_MALI400, 16 DRM_LIMA_PARAM_GPU_ID_MALI450, 17 }; 18 enum drm_lima_param { 19 DRM_LIMA_PARAM_GPU_ID, 20 DRM_LIMA_PARAM_NUM_PP, 21 DRM_LIMA_PARAM_GP_VERSION, 22 DRM_LIMA_PARAM_PP_VERSION, 23 }; 24 struct drm_lima_get_param { 25 __u32 param; 26 __u32 pad; 27 __u64 value; 28 }; 29 #define LIMA_BO_FLAG_HEAP (1 << 0) 30 struct drm_lima_gem_create { 31 __u32 size; 32 __u32 flags; 33 __u32 handle; 34 __u32 pad; 35 }; 36 struct drm_lima_gem_info { 37 __u32 handle; 38 __u32 va; 39 __u64 offset; 40 }; 41 #define LIMA_SUBMIT_BO_READ 0x01 42 #define LIMA_SUBMIT_BO_WRITE 0x02 43 struct drm_lima_gem_submit_bo { 44 __u32 handle; 45 __u32 flags; 46 }; 47 #define LIMA_GP_FRAME_REG_NUM 6 48 struct drm_lima_gp_frame { 49 __u32 frame[LIMA_GP_FRAME_REG_NUM]; 50 }; 51 #define LIMA_PP_FRAME_REG_NUM 23 52 #define LIMA_PP_WB_REG_NUM 12 53 struct drm_lima_m400_pp_frame { 54 __u32 frame[LIMA_PP_FRAME_REG_NUM]; 55 __u32 num_pp; 56 __u32 wb[3 * LIMA_PP_WB_REG_NUM]; 57 __u32 plbu_array_address[4]; 58 __u32 fragment_stack_address[4]; 59 }; 60 struct drm_lima_m450_pp_frame { 61 __u32 frame[LIMA_PP_FRAME_REG_NUM]; 62 __u32 num_pp; 63 __u32 wb[3 * LIMA_PP_WB_REG_NUM]; 64 __u32 use_dlbu; 65 __u32 _pad; 66 union { 67 __u32 plbu_array_address[8]; 68 __u32 dlbu_regs[4]; 69 }; 70 __u32 fragment_stack_address[8]; 71 }; 72 #define LIMA_PIPE_GP 0x00 73 #define LIMA_PIPE_PP 0x01 74 #define LIMA_SUBMIT_FLAG_EXPLICIT_FENCE (1 << 0) 75 struct drm_lima_gem_submit { 76 __u32 ctx; 77 __u32 pipe; 78 __u32 nr_bos; 79 __u32 frame_size; 80 __u64 bos; 81 __u64 frame; 82 __u32 flags; 83 __u32 out_sync; 84 __u32 in_sync[2]; 85 }; 86 #define LIMA_GEM_WAIT_READ 0x01 87 #define LIMA_GEM_WAIT_WRITE 0x02 88 struct drm_lima_gem_wait { 89 __u32 handle; 90 __u32 op; 91 __s64 timeout_ns; 92 }; 93 struct drm_lima_ctx_create { 94 __u32 id; 95 __u32 _pad; 96 }; 97 struct drm_lima_ctx_free { 98 __u32 id; 99 __u32 _pad; 100 }; 101 #define DRM_LIMA_GET_PARAM 0x00 102 #define DRM_LIMA_GEM_CREATE 0x01 103 #define DRM_LIMA_GEM_INFO 0x02 104 #define DRM_LIMA_GEM_SUBMIT 0x03 105 #define DRM_LIMA_GEM_WAIT 0x04 106 #define DRM_LIMA_CTX_CREATE 0x05 107 #define DRM_LIMA_CTX_FREE 0x06 108 #define DRM_IOCTL_LIMA_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param) 109 #define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create) 110 #define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info) 111 #define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit) 112 #define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait) 113 #define DRM_IOCTL_LIMA_CTX_CREATE DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, struct drm_lima_ctx_create) 114 #define DRM_IOCTL_LIMA_CTX_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free) 115 #ifdef __cplusplus 116 } 117 #endif 118 #endif 119