1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __MSM_DRM_H__ 8 #define __MSM_DRM_H__ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #define MSM_PIPE_NONE 0x00 14 #define MSM_PIPE_2D0 0x01 15 #define MSM_PIPE_2D1 0x02 16 #define MSM_PIPE_3D0 0x10 17 #define MSM_PIPE_ID_MASK 0xffff 18 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 19 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 20 struct drm_msm_timespec { 21 __s64 tv_sec; 22 __s64 tv_nsec; 23 }; 24 #define MSM_PARAM_GPU_ID 0x01 25 #define MSM_PARAM_GMEM_SIZE 0x02 26 #define MSM_PARAM_CHIP_ID 0x03 27 #define MSM_PARAM_MAX_FREQ 0x04 28 #define MSM_PARAM_TIMESTAMP 0x05 29 #define MSM_PARAM_GMEM_BASE 0x06 30 #define MSM_PARAM_PRIORITIES 0x07 31 #define MSM_PARAM_PP_PGTABLE 0x08 32 #define MSM_PARAM_FAULTS 0x09 33 #define MSM_PARAM_SUSPENDS 0x0a 34 #define MSM_PARAM_SYSPROF 0x0b 35 #define MSM_PARAM_COMM 0x0c 36 #define MSM_PARAM_CMDLINE 0x0d 37 #define MSM_PARAM_VA_START 0x0e 38 #define MSM_PARAM_VA_SIZE 0x0f 39 #define MSM_PARAM_HIGHEST_BANK_BIT 0x10 40 #define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES 41 struct drm_msm_param { 42 __u32 pipe; 43 __u32 param; 44 __u64 value; 45 __u32 len; 46 __u32 pad; 47 }; 48 #define MSM_BO_SCANOUT 0x00000001 49 #define MSM_BO_GPU_READONLY 0x00000002 50 #define MSM_BO_CACHE_MASK 0x000f0000 51 #define MSM_BO_CACHED 0x00010000 52 #define MSM_BO_WC 0x00020000 53 #define MSM_BO_UNCACHED 0x00040000 54 #define MSM_BO_CACHED_COHERENT 0x080000 55 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHE_MASK) 56 struct drm_msm_gem_new { 57 __u64 size; 58 __u32 flags; 59 __u32 handle; 60 }; 61 #define MSM_INFO_GET_OFFSET 0x00 62 #define MSM_INFO_GET_IOVA 0x01 63 #define MSM_INFO_SET_NAME 0x02 64 #define MSM_INFO_GET_NAME 0x03 65 #define MSM_INFO_SET_IOVA 0x04 66 #define MSM_INFO_GET_FLAGS 0x05 67 #define MSM_INFO_SET_METADATA 0x06 68 #define MSM_INFO_GET_METADATA 0x07 69 struct drm_msm_gem_info { 70 __u32 handle; 71 __u32 info; 72 __u64 value; 73 __u32 len; 74 __u32 pad; 75 }; 76 #define MSM_PREP_READ 0x01 77 #define MSM_PREP_WRITE 0x02 78 #define MSM_PREP_NOSYNC 0x04 79 #define MSM_PREP_BOOST 0x08 80 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC | MSM_PREP_BOOST | 0) 81 struct drm_msm_gem_cpu_prep { 82 __u32 handle; 83 __u32 op; 84 struct drm_msm_timespec timeout; 85 }; 86 struct drm_msm_gem_cpu_fini { 87 __u32 handle; 88 }; 89 struct drm_msm_gem_submit_reloc { 90 __u32 submit_offset; 91 #ifdef __cplusplus 92 __u32 _or; 93 #else 94 __u32 or; 95 #endif 96 __s32 shift; 97 __u32 reloc_idx; 98 __u64 reloc_offset; 99 }; 100 #define MSM_SUBMIT_CMD_BUF 0x0001 101 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 102 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 103 struct drm_msm_gem_submit_cmd { 104 __u32 type; 105 __u32 submit_idx; 106 __u32 submit_offset; 107 __u32 size; 108 __u32 pad; 109 __u32 nr_relocs; 110 __u64 relocs; 111 }; 112 #define MSM_SUBMIT_BO_READ 0x0001 113 #define MSM_SUBMIT_BO_WRITE 0x0002 114 #define MSM_SUBMIT_BO_DUMP 0x0004 115 #define MSM_SUBMIT_BO_NO_IMPLICIT 0x0008 116 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE | MSM_SUBMIT_BO_DUMP | MSM_SUBMIT_BO_NO_IMPLICIT) 117 struct drm_msm_gem_submit_bo { 118 __u32 flags; 119 __u32 handle; 120 __u64 presumed; 121 }; 122 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 123 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 124 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 125 #define MSM_SUBMIT_SUDO 0x10000000 126 #define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 127 #define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 128 #define MSM_SUBMIT_FENCE_SN_IN 0x02000000 129 #define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | MSM_SUBMIT_SUDO | MSM_SUBMIT_SYNCOBJ_IN | MSM_SUBMIT_SYNCOBJ_OUT | MSM_SUBMIT_FENCE_SN_IN | 0) 130 #define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 131 #define MSM_SUBMIT_SYNCOBJ_FLAGS (MSM_SUBMIT_SYNCOBJ_RESET | 0) 132 struct drm_msm_gem_submit_syncobj { 133 __u32 handle; 134 __u32 flags; 135 __u64 point; 136 }; 137 struct drm_msm_gem_submit { 138 __u32 flags; 139 __u32 fence; 140 __u32 nr_bos; 141 __u32 nr_cmds; 142 __u64 bos; 143 __u64 cmds; 144 __s32 fence_fd; 145 __u32 queueid; 146 __u64 in_syncobjs; 147 __u64 out_syncobjs; 148 __u32 nr_in_syncobjs; 149 __u32 nr_out_syncobjs; 150 __u32 syncobj_stride; 151 __u32 pad; 152 }; 153 #define MSM_WAIT_FENCE_BOOST 0x00000001 154 #define MSM_WAIT_FENCE_FLAGS (MSM_WAIT_FENCE_BOOST | 0) 155 struct drm_msm_wait_fence { 156 __u32 fence; 157 __u32 flags; 158 struct drm_msm_timespec timeout; 159 __u32 queueid; 160 }; 161 #define MSM_MADV_WILLNEED 0 162 #define MSM_MADV_DONTNEED 1 163 #define __MSM_MADV_PURGED 2 164 struct drm_msm_gem_madvise { 165 __u32 handle; 166 __u32 madv; 167 __u32 retained; 168 }; 169 #define MSM_SUBMITQUEUE_FLAGS (0) 170 struct drm_msm_submitqueue { 171 __u32 flags; 172 __u32 prio; 173 __u32 id; 174 }; 175 #define MSM_SUBMITQUEUE_PARAM_FAULTS 0 176 struct drm_msm_submitqueue_query { 177 __u64 data; 178 __u32 id; 179 __u32 param; 180 __u32 len; 181 __u32 pad; 182 }; 183 #define DRM_MSM_GET_PARAM 0x00 184 #define DRM_MSM_SET_PARAM 0x01 185 #define DRM_MSM_GEM_NEW 0x02 186 #define DRM_MSM_GEM_INFO 0x03 187 #define DRM_MSM_GEM_CPU_PREP 0x04 188 #define DRM_MSM_GEM_CPU_FINI 0x05 189 #define DRM_MSM_GEM_SUBMIT 0x06 190 #define DRM_MSM_WAIT_FENCE 0x07 191 #define DRM_MSM_GEM_MADVISE 0x08 192 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A 193 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 194 #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C 195 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 196 #define DRM_IOCTL_MSM_SET_PARAM DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param) 197 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 198 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 199 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 200 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 201 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 202 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 203 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 204 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 205 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) 206 #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query) 207 #ifdef __cplusplus 208 } 209 #endif 210 #endif 211