1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _V3D_DRM_H_ 8 #define _V3D_DRM_H_ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #define DRM_V3D_SUBMIT_CL 0x00 14 #define DRM_V3D_WAIT_BO 0x01 15 #define DRM_V3D_CREATE_BO 0x02 16 #define DRM_V3D_MMAP_BO 0x03 17 #define DRM_V3D_GET_PARAM 0x04 18 #define DRM_V3D_GET_BO_OFFSET 0x05 19 #define DRM_V3D_SUBMIT_TFU 0x06 20 #define DRM_V3D_SUBMIT_CSD 0x07 21 #define DRM_V3D_PERFMON_CREATE 0x08 22 #define DRM_V3D_PERFMON_DESTROY 0x09 23 #define DRM_V3D_PERFMON_GET_VALUES 0x0a 24 #define DRM_V3D_SUBMIT_CPU 0x0b 25 #define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl) 26 #define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo) 27 #define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo) 28 #define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo) 29 #define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param) 30 #define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset) 31 #define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu) 32 #define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd) 33 #define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, struct drm_v3d_perfmon_create) 34 #define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, struct drm_v3d_perfmon_destroy) 35 #define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, struct drm_v3d_perfmon_get_values) 36 #define DRM_IOCTL_V3D_SUBMIT_CPU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CPU, struct drm_v3d_submit_cpu) 37 #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01 38 #define DRM_V3D_SUBMIT_EXTENSION 0x02 39 struct drm_v3d_extension { 40 __u64 next; 41 __u32 id; 42 #define DRM_V3D_EXT_ID_MULTI_SYNC 0x01 43 #define DRM_V3D_EXT_ID_CPU_INDIRECT_CSD 0x02 44 #define DRM_V3D_EXT_ID_CPU_TIMESTAMP_QUERY 0x03 45 #define DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY 0x04 46 #define DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY 0x05 47 #define DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY 0x06 48 #define DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY 0x07 49 __u32 flags; 50 }; 51 struct drm_v3d_sem { 52 __u32 handle; 53 __u32 flags; 54 __u64 point; 55 __u64 mbz[2]; 56 }; 57 enum v3d_queue { 58 V3D_BIN, 59 V3D_RENDER, 60 V3D_TFU, 61 V3D_CSD, 62 V3D_CACHE_CLEAN, 63 V3D_CPU, 64 }; 65 struct drm_v3d_multi_sync { 66 struct drm_v3d_extension base; 67 __u64 in_syncs; 68 __u64 out_syncs; 69 __u32 in_sync_count; 70 __u32 out_sync_count; 71 __u32 wait_stage; 72 __u32 pad; 73 }; 74 struct drm_v3d_submit_cl { 75 __u32 bcl_start; 76 __u32 bcl_end; 77 __u32 rcl_start; 78 __u32 rcl_end; 79 __u32 in_sync_bcl; 80 __u32 in_sync_rcl; 81 __u32 out_sync; 82 __u32 qma; 83 __u32 qms; 84 __u32 qts; 85 __u64 bo_handles; 86 __u32 bo_handle_count; 87 __u32 flags; 88 __u32 perfmon_id; 89 __u32 pad; 90 __u64 extensions; 91 }; 92 struct drm_v3d_wait_bo { 93 __u32 handle; 94 __u32 pad; 95 __u64 timeout_ns; 96 }; 97 struct drm_v3d_create_bo { 98 __u32 size; 99 __u32 flags; 100 __u32 handle; 101 __u32 offset; 102 }; 103 struct drm_v3d_mmap_bo { 104 __u32 handle; 105 __u32 flags; 106 __u64 offset; 107 }; 108 enum drm_v3d_param { 109 DRM_V3D_PARAM_V3D_UIFCFG, 110 DRM_V3D_PARAM_V3D_HUB_IDENT1, 111 DRM_V3D_PARAM_V3D_HUB_IDENT2, 112 DRM_V3D_PARAM_V3D_HUB_IDENT3, 113 DRM_V3D_PARAM_V3D_CORE0_IDENT0, 114 DRM_V3D_PARAM_V3D_CORE0_IDENT1, 115 DRM_V3D_PARAM_V3D_CORE0_IDENT2, 116 DRM_V3D_PARAM_SUPPORTS_TFU, 117 DRM_V3D_PARAM_SUPPORTS_CSD, 118 DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH, 119 DRM_V3D_PARAM_SUPPORTS_PERFMON, 120 DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT, 121 DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE, 122 }; 123 struct drm_v3d_get_param { 124 __u32 param; 125 __u32 pad; 126 __u64 value; 127 }; 128 struct drm_v3d_get_bo_offset { 129 __u32 handle; 130 __u32 offset; 131 }; 132 struct drm_v3d_submit_tfu { 133 __u32 icfg; 134 __u32 iia; 135 __u32 iis; 136 __u32 ica; 137 __u32 iua; 138 __u32 ioa; 139 __u32 ios; 140 __u32 coef[4]; 141 __u32 bo_handles[4]; 142 __u32 in_sync; 143 __u32 out_sync; 144 __u32 flags; 145 __u64 extensions; 146 struct { 147 __u32 ioc; 148 __u32 pad; 149 } v71; 150 }; 151 struct drm_v3d_submit_csd { 152 __u32 cfg[7]; 153 __u32 coef[4]; 154 __u64 bo_handles; 155 __u32 bo_handle_count; 156 __u32 in_sync; 157 __u32 out_sync; 158 __u32 perfmon_id; 159 __u64 extensions; 160 __u32 flags; 161 __u32 pad; 162 }; 163 struct drm_v3d_indirect_csd { 164 struct drm_v3d_extension base; 165 struct drm_v3d_submit_csd submit; 166 __u32 indirect; 167 __u32 offset; 168 __u32 wg_size; 169 __u32 wg_uniform_offsets[3]; 170 }; 171 struct drm_v3d_timestamp_query { 172 struct drm_v3d_extension base; 173 __u64 offsets; 174 __u64 syncs; 175 __u32 count; 176 __u32 pad; 177 }; 178 struct drm_v3d_reset_timestamp_query { 179 struct drm_v3d_extension base; 180 __u64 syncs; 181 __u32 offset; 182 __u32 count; 183 }; 184 struct drm_v3d_copy_timestamp_query { 185 struct drm_v3d_extension base; 186 __u8 do_64bit; 187 __u8 do_partial; 188 __u8 availability_bit; 189 __u8 pad; 190 __u32 offset; 191 __u32 stride; 192 __u32 count; 193 __u64 offsets; 194 __u64 syncs; 195 }; 196 struct drm_v3d_reset_performance_query { 197 struct drm_v3d_extension base; 198 __u64 syncs; 199 __u32 count; 200 __u32 nperfmons; 201 __u64 kperfmon_ids; 202 }; 203 struct drm_v3d_copy_performance_query { 204 struct drm_v3d_extension base; 205 __u8 do_64bit; 206 __u8 do_partial; 207 __u8 availability_bit; 208 __u8 pad; 209 __u32 offset; 210 __u32 stride; 211 __u32 nperfmons; 212 __u32 ncounters; 213 __u32 count; 214 __u64 syncs; 215 __u64 kperfmon_ids; 216 }; 217 struct drm_v3d_submit_cpu { 218 __u64 bo_handles; 219 __u32 bo_handle_count; 220 __u32 flags; 221 __u64 extensions; 222 }; 223 enum { 224 V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS, 225 V3D_PERFCNT_FEP_VALID_PRIMS, 226 V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS, 227 V3D_PERFCNT_FEP_VALID_QUADS, 228 V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL, 229 V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL, 230 V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS, 231 V3D_PERFCNT_TLB_QUADS_ZERO_COV, 232 V3D_PERFCNT_TLB_QUADS_NONZERO_COV, 233 V3D_PERFCNT_TLB_QUADS_WRITTEN, 234 V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD, 235 V3D_PERFCNT_PTB_PRIM_CLIP, 236 V3D_PERFCNT_PTB_PRIM_REV, 237 V3D_PERFCNT_QPU_IDLE_CYCLES, 238 V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER, 239 V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG, 240 V3D_PERFCNT_QPU_CYCLES_VALID_INSTR, 241 V3D_PERFCNT_QPU_CYCLES_TMU_STALL, 242 V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL, 243 V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL, 244 V3D_PERFCNT_QPU_IC_HIT, 245 V3D_PERFCNT_QPU_IC_MISS, 246 V3D_PERFCNT_QPU_UC_HIT, 247 V3D_PERFCNT_QPU_UC_MISS, 248 V3D_PERFCNT_TMU_TCACHE_ACCESS, 249 V3D_PERFCNT_TMU_TCACHE_MISS, 250 V3D_PERFCNT_VPM_VDW_STALL, 251 V3D_PERFCNT_VPM_VCD_STALL, 252 V3D_PERFCNT_BIN_ACTIVE, 253 V3D_PERFCNT_RDR_ACTIVE, 254 V3D_PERFCNT_L2T_HITS, 255 V3D_PERFCNT_L2T_MISSES, 256 V3D_PERFCNT_CYCLE_COUNT, 257 V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER, 258 V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT, 259 V3D_PERFCNT_PTB_PRIMS_BINNED, 260 V3D_PERFCNT_AXI_WRITES_WATCH_0, 261 V3D_PERFCNT_AXI_READS_WATCH_0, 262 V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0, 263 V3D_PERFCNT_AXI_READ_STALLS_WATCH_0, 264 V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0, 265 V3D_PERFCNT_AXI_READ_BYTES_WATCH_0, 266 V3D_PERFCNT_AXI_WRITES_WATCH_1, 267 V3D_PERFCNT_AXI_READS_WATCH_1, 268 V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1, 269 V3D_PERFCNT_AXI_READ_STALLS_WATCH_1, 270 V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1, 271 V3D_PERFCNT_AXI_READ_BYTES_WATCH_1, 272 V3D_PERFCNT_TLB_PARTIAL_QUADS, 273 V3D_PERFCNT_TMU_CONFIG_ACCESSES, 274 V3D_PERFCNT_L2T_NO_ID_STALL, 275 V3D_PERFCNT_L2T_COM_QUE_STALL, 276 V3D_PERFCNT_L2T_TMU_WRITES, 277 V3D_PERFCNT_TMU_ACTIVE_CYCLES, 278 V3D_PERFCNT_TMU_STALLED_CYCLES, 279 V3D_PERFCNT_CLE_ACTIVE, 280 V3D_PERFCNT_L2T_TMU_READS, 281 V3D_PERFCNT_L2T_CLE_READS, 282 V3D_PERFCNT_L2T_VCD_READS, 283 V3D_PERFCNT_L2T_TMUCFG_READS, 284 V3D_PERFCNT_L2T_SLC0_READS, 285 V3D_PERFCNT_L2T_SLC1_READS, 286 V3D_PERFCNT_L2T_SLC2_READS, 287 V3D_PERFCNT_L2T_TMU_W_MISSES, 288 V3D_PERFCNT_L2T_TMU_R_MISSES, 289 V3D_PERFCNT_L2T_CLE_MISSES, 290 V3D_PERFCNT_L2T_VCD_MISSES, 291 V3D_PERFCNT_L2T_TMUCFG_MISSES, 292 V3D_PERFCNT_L2T_SLC0_MISSES, 293 V3D_PERFCNT_L2T_SLC1_MISSES, 294 V3D_PERFCNT_L2T_SLC2_MISSES, 295 V3D_PERFCNT_CORE_MEM_WRITES, 296 V3D_PERFCNT_L2T_MEM_WRITES, 297 V3D_PERFCNT_PTB_MEM_WRITES, 298 V3D_PERFCNT_TLB_MEM_WRITES, 299 V3D_PERFCNT_CORE_MEM_READS, 300 V3D_PERFCNT_L2T_MEM_READS, 301 V3D_PERFCNT_PTB_MEM_READS, 302 V3D_PERFCNT_PSE_MEM_READS, 303 V3D_PERFCNT_TLB_MEM_READS, 304 V3D_PERFCNT_GMP_MEM_READS, 305 V3D_PERFCNT_PTB_W_MEM_WORDS, 306 V3D_PERFCNT_TLB_W_MEM_WORDS, 307 V3D_PERFCNT_PSE_R_MEM_WORDS, 308 V3D_PERFCNT_TLB_R_MEM_WORDS, 309 V3D_PERFCNT_TMU_MRU_HITS, 310 V3D_PERFCNT_COMPUTE_ACTIVE, 311 V3D_PERFCNT_NUM, 312 }; 313 #define DRM_V3D_MAX_PERF_COUNTERS 32 314 struct drm_v3d_perfmon_create { 315 __u32 id; 316 __u32 ncounters; 317 __u8 counters[DRM_V3D_MAX_PERF_COUNTERS]; 318 }; 319 struct drm_v3d_perfmon_destroy { 320 __u32 id; 321 }; 322 struct drm_v3d_perfmon_get_values { 323 __u32 id; 324 __u32 pad; 325 __u64 values_ptr; 326 }; 327 #ifdef __cplusplus 328 } 329 #endif 330 #endif 331