1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _UAPI_VC4_DRM_H_ 8 #define _UAPI_VC4_DRM_H_ 9 #include "drm.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #define DRM_VC4_SUBMIT_CL 0x00 14 #define DRM_VC4_WAIT_SEQNO 0x01 15 #define DRM_VC4_WAIT_BO 0x02 16 #define DRM_VC4_CREATE_BO 0x03 17 #define DRM_VC4_MMAP_BO 0x04 18 #define DRM_VC4_CREATE_SHADER_BO 0x05 19 #define DRM_VC4_GET_HANG_STATE 0x06 20 #define DRM_VC4_GET_PARAM 0x07 21 #define DRM_VC4_SET_TILING 0x08 22 #define DRM_VC4_GET_TILING 0x09 23 #define DRM_VC4_LABEL_BO 0x0a 24 #define DRM_VC4_GEM_MADVISE 0x0b 25 #define DRM_VC4_PERFMON_CREATE 0x0c 26 #define DRM_VC4_PERFMON_DESTROY 0x0d 27 #define DRM_VC4_PERFMON_GET_VALUES 0x0e 28 #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) 29 #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) 30 #define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) 31 #define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) 32 #define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) 33 #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) 34 #define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) 35 #define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) 36 #define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling) 37 #define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling) 38 #define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo) 39 #define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise) 40 #define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create) 41 #define DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy) 42 #define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values) 43 struct drm_vc4_submit_rcl_surface { 44 __u32 hindex; 45 __u32 offset; 46 __u16 bits; 47 #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) 48 __u16 flags; 49 }; 50 struct drm_vc4_submit_cl { 51 __u64 bin_cl; 52 __u64 shader_rec; 53 __u64 uniforms; 54 __u64 bo_handles; 55 __u32 bin_cl_size; 56 __u32 shader_rec_size; 57 __u32 shader_rec_count; 58 __u32 uniforms_size; 59 __u32 bo_handle_count; 60 __u16 width; 61 __u16 height; 62 __u8 min_x_tile; 63 __u8 min_y_tile; 64 __u8 max_x_tile; 65 __u8 max_y_tile; 66 struct drm_vc4_submit_rcl_surface color_read; 67 struct drm_vc4_submit_rcl_surface color_write; 68 struct drm_vc4_submit_rcl_surface zs_read; 69 struct drm_vc4_submit_rcl_surface zs_write; 70 struct drm_vc4_submit_rcl_surface msaa_color_write; 71 struct drm_vc4_submit_rcl_surface msaa_zs_write; 72 __u32 clear_color[2]; 73 __u32 clear_z; 74 __u8 clear_s; 75 __u32 pad : 24; 76 #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) 77 #define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1) 78 #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2) 79 #define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3) 80 __u32 flags; 81 __u64 seqno; 82 __u32 perfmonid; 83 __u32 in_sync; 84 __u32 out_sync; 85 __u32 pad2; 86 }; 87 struct drm_vc4_wait_seqno { 88 __u64 seqno; 89 __u64 timeout_ns; 90 }; 91 struct drm_vc4_wait_bo { 92 __u32 handle; 93 __u32 pad; 94 __u64 timeout_ns; 95 }; 96 struct drm_vc4_create_bo { 97 __u32 size; 98 __u32 flags; 99 __u32 handle; 100 __u32 pad; 101 }; 102 struct drm_vc4_mmap_bo { 103 __u32 handle; 104 __u32 flags; 105 __u64 offset; 106 }; 107 struct drm_vc4_create_shader_bo { 108 __u32 size; 109 __u32 flags; 110 __u64 data; 111 __u32 handle; 112 __u32 pad; 113 }; 114 struct drm_vc4_get_hang_state_bo { 115 __u32 handle; 116 __u32 paddr; 117 __u32 size; 118 __u32 pad; 119 }; 120 struct drm_vc4_get_hang_state { 121 __u64 bo; 122 __u32 bo_count; 123 __u32 start_bin, start_render; 124 __u32 ct0ca, ct0ea; 125 __u32 ct1ca, ct1ea; 126 __u32 ct0cs, ct1cs; 127 __u32 ct0ra0, ct1ra0; 128 __u32 bpca, bpcs; 129 __u32 bpoa, bpos; 130 __u32 vpmbase; 131 __u32 dbge; 132 __u32 fdbgo; 133 __u32 fdbgb; 134 __u32 fdbgr; 135 __u32 fdbgs; 136 __u32 errstat; 137 __u32 pad[16]; 138 }; 139 #define DRM_VC4_PARAM_V3D_IDENT0 0 140 #define DRM_VC4_PARAM_V3D_IDENT1 1 141 #define DRM_VC4_PARAM_V3D_IDENT2 2 142 #define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3 143 #define DRM_VC4_PARAM_SUPPORTS_ETC1 4 144 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 145 #define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6 146 #define DRM_VC4_PARAM_SUPPORTS_MADVISE 7 147 #define DRM_VC4_PARAM_SUPPORTS_PERFMON 8 148 struct drm_vc4_get_param { 149 __u32 param; 150 __u32 pad; 151 __u64 value; 152 }; 153 struct drm_vc4_get_tiling { 154 __u32 handle; 155 __u32 flags; 156 __u64 modifier; 157 }; 158 struct drm_vc4_set_tiling { 159 __u32 handle; 160 __u32 flags; 161 __u64 modifier; 162 }; 163 struct drm_vc4_label_bo { 164 __u32 handle; 165 __u32 len; 166 __u64 name; 167 }; 168 #define VC4_MADV_WILLNEED 0 169 #define VC4_MADV_DONTNEED 1 170 #define __VC4_MADV_PURGED 2 171 #define __VC4_MADV_NOTSUPP 3 172 struct drm_vc4_gem_madvise { 173 __u32 handle; 174 __u32 madv; 175 __u32 retained; 176 __u32 pad; 177 }; 178 enum { 179 VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER, 180 VC4_PERFCNT_FEP_VALID_PRIMS_RENDER, 181 VC4_PERFCNT_FEP_CLIPPED_QUADS, 182 VC4_PERFCNT_FEP_VALID_QUADS, 183 VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL, 184 VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL, 185 VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL, 186 VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE, 187 VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE, 188 VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF, 189 VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT, 190 VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING, 191 VC4_PERFCNT_PSE_PRIMS_REVERSED, 192 VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES, 193 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING, 194 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING, 195 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST, 196 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS, 197 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD, 198 VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS, 199 VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT, 200 VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS, 201 VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT, 202 VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS, 203 VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED, 204 VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS, 205 VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED, 206 VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED, 207 VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT, 208 VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS, 209 VC4_PERFCNT_NUM_EVENTS, 210 }; 211 #define DRM_VC4_MAX_PERF_COUNTERS 16 212 struct drm_vc4_perfmon_create { 213 __u32 id; 214 __u32 ncounters; 215 __u8 events[DRM_VC4_MAX_PERF_COUNTERS]; 216 }; 217 struct drm_vc4_perfmon_destroy { 218 __u32 id; 219 }; 220 struct drm_vc4_perfmon_get_values { 221 __u32 id; 222 __u64 values_ptr; 223 }; 224 #ifdef __cplusplus 225 } 226 #endif 227 #endif 228