1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _UAPI_LINUX_DPLL_H 8 #define _UAPI_LINUX_DPLL_H 9 #define DPLL_FAMILY_NAME "dpll" 10 #define DPLL_FAMILY_VERSION 1 11 enum dpll_mode { 12 DPLL_MODE_MANUAL = 1, 13 DPLL_MODE_AUTOMATIC, 14 __DPLL_MODE_MAX, 15 DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1) 16 }; 17 enum dpll_lock_status { 18 DPLL_LOCK_STATUS_UNLOCKED = 1, 19 DPLL_LOCK_STATUS_LOCKED, 20 DPLL_LOCK_STATUS_LOCKED_HO_ACQ, 21 DPLL_LOCK_STATUS_HOLDOVER, 22 __DPLL_LOCK_STATUS_MAX, 23 DPLL_LOCK_STATUS_MAX = (__DPLL_LOCK_STATUS_MAX - 1) 24 }; 25 enum dpll_lock_status_error { 26 DPLL_LOCK_STATUS_ERROR_NONE = 1, 27 DPLL_LOCK_STATUS_ERROR_UNDEFINED, 28 DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN, 29 DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH, 30 __DPLL_LOCK_STATUS_ERROR_MAX, 31 DPLL_LOCK_STATUS_ERROR_MAX = (__DPLL_LOCK_STATUS_ERROR_MAX - 1) 32 }; 33 #define DPLL_TEMP_DIVIDER 1000 34 enum dpll_type { 35 DPLL_TYPE_PPS = 1, 36 DPLL_TYPE_EEC, 37 __DPLL_TYPE_MAX, 38 DPLL_TYPE_MAX = (__DPLL_TYPE_MAX - 1) 39 }; 40 enum dpll_pin_type { 41 DPLL_PIN_TYPE_MUX = 1, 42 DPLL_PIN_TYPE_EXT, 43 DPLL_PIN_TYPE_SYNCE_ETH_PORT, 44 DPLL_PIN_TYPE_INT_OSCILLATOR, 45 DPLL_PIN_TYPE_GNSS, 46 __DPLL_PIN_TYPE_MAX, 47 DPLL_PIN_TYPE_MAX = (__DPLL_PIN_TYPE_MAX - 1) 48 }; 49 enum dpll_pin_direction { 50 DPLL_PIN_DIRECTION_INPUT = 1, 51 DPLL_PIN_DIRECTION_OUTPUT, 52 __DPLL_PIN_DIRECTION_MAX, 53 DPLL_PIN_DIRECTION_MAX = (__DPLL_PIN_DIRECTION_MAX - 1) 54 }; 55 #define DPLL_PIN_FREQUENCY_1_HZ 1 56 #define DPLL_PIN_FREQUENCY_10_KHZ 10000 57 #define DPLL_PIN_FREQUENCY_77_5_KHZ 77500 58 #define DPLL_PIN_FREQUENCY_10_MHZ 10000000 59 enum dpll_pin_state { 60 DPLL_PIN_STATE_CONNECTED = 1, 61 DPLL_PIN_STATE_DISCONNECTED, 62 DPLL_PIN_STATE_SELECTABLE, 63 __DPLL_PIN_STATE_MAX, 64 DPLL_PIN_STATE_MAX = (__DPLL_PIN_STATE_MAX - 1) 65 }; 66 enum dpll_pin_capabilities { 67 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE = 1, 68 DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE = 2, 69 DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4, 70 }; 71 #define DPLL_PHASE_OFFSET_DIVIDER 1000 72 enum dpll_a { 73 DPLL_A_ID = 1, 74 DPLL_A_MODULE_NAME, 75 DPLL_A_PAD, 76 DPLL_A_CLOCK_ID, 77 DPLL_A_MODE, 78 DPLL_A_MODE_SUPPORTED, 79 DPLL_A_LOCK_STATUS, 80 DPLL_A_TEMP, 81 DPLL_A_TYPE, 82 DPLL_A_LOCK_STATUS_ERROR, 83 __DPLL_A_MAX, 84 DPLL_A_MAX = (__DPLL_A_MAX - 1) 85 }; 86 enum dpll_a_pin { 87 DPLL_A_PIN_ID = 1, 88 DPLL_A_PIN_PARENT_ID, 89 DPLL_A_PIN_MODULE_NAME, 90 DPLL_A_PIN_PAD, 91 DPLL_A_PIN_CLOCK_ID, 92 DPLL_A_PIN_BOARD_LABEL, 93 DPLL_A_PIN_PANEL_LABEL, 94 DPLL_A_PIN_PACKAGE_LABEL, 95 DPLL_A_PIN_TYPE, 96 DPLL_A_PIN_DIRECTION, 97 DPLL_A_PIN_FREQUENCY, 98 DPLL_A_PIN_FREQUENCY_SUPPORTED, 99 DPLL_A_PIN_FREQUENCY_MIN, 100 DPLL_A_PIN_FREQUENCY_MAX, 101 DPLL_A_PIN_PRIO, 102 DPLL_A_PIN_STATE, 103 DPLL_A_PIN_CAPABILITIES, 104 DPLL_A_PIN_PARENT_DEVICE, 105 DPLL_A_PIN_PARENT_PIN, 106 DPLL_A_PIN_PHASE_ADJUST_MIN, 107 DPLL_A_PIN_PHASE_ADJUST_MAX, 108 DPLL_A_PIN_PHASE_ADJUST, 109 DPLL_A_PIN_PHASE_OFFSET, 110 DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, 111 __DPLL_A_PIN_MAX, 112 DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1) 113 }; 114 enum dpll_cmd { 115 DPLL_CMD_DEVICE_ID_GET = 1, 116 DPLL_CMD_DEVICE_GET, 117 DPLL_CMD_DEVICE_SET, 118 DPLL_CMD_DEVICE_CREATE_NTF, 119 DPLL_CMD_DEVICE_DELETE_NTF, 120 DPLL_CMD_DEVICE_CHANGE_NTF, 121 DPLL_CMD_PIN_ID_GET, 122 DPLL_CMD_PIN_GET, 123 DPLL_CMD_PIN_SET, 124 DPLL_CMD_PIN_CREATE_NTF, 125 DPLL_CMD_PIN_DELETE_NTF, 126 DPLL_CMD_PIN_CHANGE_NTF, 127 __DPLL_CMD_MAX, 128 DPLL_CMD_MAX = (__DPLL_CMD_MAX - 1) 129 }; 130 #define DPLL_MCGRP_MONITOR "monitor" 131 #endif 132