1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _UAPI_LINUX_PSCI_H 8 #define _UAPI_LINUX_PSCI_H 9 #define PSCI_0_2_FN_BASE 0x84000000 10 #define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) 11 #define PSCI_0_2_64BIT 0x40000000 12 #define PSCI_0_2_FN64_BASE (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT) 13 #define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) 14 #define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0) 15 #define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1) 16 #define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2) 17 #define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3) 18 #define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4) 19 #define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5) 20 #define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6) 21 #define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7) 22 #define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8) 23 #define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9) 24 #define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) 25 #define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) 26 #define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) 27 #define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5) 28 #define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) 29 #define PSCI_1_0_FN_PSCI_FEATURES PSCI_0_2_FN(10) 30 #define PSCI_1_0_FN_CPU_FREEZE PSCI_0_2_FN(11) 31 #define PSCI_1_0_FN_CPU_DEFAULT_SUSPEND PSCI_0_2_FN(12) 32 #define PSCI_1_0_FN_NODE_HW_STATE PSCI_0_2_FN(13) 33 #define PSCI_1_0_FN_SYSTEM_SUSPEND PSCI_0_2_FN(14) 34 #define PSCI_1_0_FN_SET_SUSPEND_MODE PSCI_0_2_FN(15) 35 #define PSCI_1_0_FN_STAT_RESIDENCY PSCI_0_2_FN(16) 36 #define PSCI_1_0_FN_STAT_COUNT PSCI_0_2_FN(17) 37 #define PSCI_1_1_FN_SYSTEM_RESET2 PSCI_0_2_FN(18) 38 #define PSCI_1_1_FN_MEM_PROTECT PSCI_0_2_FN(19) 39 #define PSCI_1_1_FN_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN(20) 40 #define PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND PSCI_0_2_FN64(12) 41 #define PSCI_1_0_FN64_NODE_HW_STATE PSCI_0_2_FN64(13) 42 #define PSCI_1_0_FN64_SYSTEM_SUSPEND PSCI_0_2_FN64(14) 43 #define PSCI_1_0_FN64_STAT_RESIDENCY PSCI_0_2_FN64(16) 44 #define PSCI_1_0_FN64_STAT_COUNT PSCI_0_2_FN64(17) 45 #define PSCI_1_1_FN64_SYSTEM_RESET2 PSCI_0_2_FN64(18) 46 #define PSCI_1_1_FN64_MEM_PROTECT_CHECK_RANGE PSCI_0_2_FN64(20) 47 #define PSCI_0_2_POWER_STATE_ID_MASK 0xffff 48 #define PSCI_0_2_POWER_STATE_ID_SHIFT 0 49 #define PSCI_0_2_POWER_STATE_TYPE_SHIFT 16 50 #define PSCI_0_2_POWER_STATE_TYPE_MASK (0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT) 51 #define PSCI_0_2_POWER_STATE_AFFL_SHIFT 24 52 #define PSCI_0_2_POWER_STATE_AFFL_MASK (0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) 53 #define PSCI_1_0_EXT_POWER_STATE_ID_MASK 0xfffffff 54 #define PSCI_1_0_EXT_POWER_STATE_ID_SHIFT 0 55 #define PSCI_1_0_EXT_POWER_STATE_TYPE_SHIFT 30 56 #define PSCI_1_0_EXT_POWER_STATE_TYPE_MASK (0x1 << PSCI_1_0_EXT_POWER_STATE_TYPE_SHIFT) 57 #define PSCI_0_2_AFFINITY_LEVEL_ON 0 58 #define PSCI_0_2_AFFINITY_LEVEL_OFF 1 59 #define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING 2 60 #define PSCI_0_2_TOS_UP_MIGRATE 0 61 #define PSCI_0_2_TOS_UP_NO_MIGRATE 1 62 #define PSCI_0_2_TOS_MP 2 63 #define PSCI_1_1_RESET_TYPE_SYSTEM_WARM_RESET 0 64 #define PSCI_1_1_RESET_TYPE_VENDOR_START 0x80000000U 65 #define PSCI_VERSION_MAJOR_SHIFT 16 66 #define PSCI_VERSION_MINOR_MASK ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1) 67 #define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK 68 #define PSCI_VERSION_MAJOR(ver) (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT) 69 #define PSCI_VERSION_MINOR(ver) ((ver) & PSCI_VERSION_MINOR_MASK) 70 #define PSCI_VERSION(maj,min) ((((maj) << PSCI_VERSION_MAJOR_SHIFT) & PSCI_VERSION_MAJOR_MASK) | ((min) & PSCI_VERSION_MINOR_MASK)) 71 #define PSCI_1_0_FEATURES_CPU_SUSPEND_PF_SHIFT 1 72 #define PSCI_1_0_FEATURES_CPU_SUSPEND_PF_MASK (0x1 << PSCI_1_0_FEATURES_CPU_SUSPEND_PF_SHIFT) 73 #define PSCI_1_0_OS_INITIATED BIT(0) 74 #define PSCI_1_0_SUSPEND_MODE_PC 0 75 #define PSCI_1_0_SUSPEND_MODE_OSI 1 76 #define PSCI_RET_SUCCESS 0 77 #define PSCI_RET_NOT_SUPPORTED - 1 78 #define PSCI_RET_INVALID_PARAMS - 2 79 #define PSCI_RET_DENIED - 3 80 #define PSCI_RET_ALREADY_ON - 4 81 #define PSCI_RET_ON_PENDING - 5 82 #define PSCI_RET_INTERNAL_FAILURE - 6 83 #define PSCI_RET_NOT_PRESENT - 7 84 #define PSCI_RET_DISABLED - 8 85 #define PSCI_RET_INVALID_ADDRESS - 9 86 #endif 87