1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef VIRTIO_GPU_HW_H 8 #define VIRTIO_GPU_HW_H 9 #include <linux/types.h> 10 #define VIRTIO_GPU_F_VIRGL 0 11 #define VIRTIO_GPU_F_EDID 1 12 #define VIRTIO_GPU_F_RESOURCE_UUID 2 13 #define VIRTIO_GPU_F_RESOURCE_BLOB 3 14 #define VIRTIO_GPU_F_CONTEXT_INIT 4 15 enum virtio_gpu_ctrl_type { 16 VIRTIO_GPU_UNDEFINED = 0, 17 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100, 18 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D, 19 VIRTIO_GPU_CMD_RESOURCE_UNREF, 20 VIRTIO_GPU_CMD_SET_SCANOUT, 21 VIRTIO_GPU_CMD_RESOURCE_FLUSH, 22 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D, 23 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING, 24 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, 25 VIRTIO_GPU_CMD_GET_CAPSET_INFO, 26 VIRTIO_GPU_CMD_GET_CAPSET, 27 VIRTIO_GPU_CMD_GET_EDID, 28 VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID, 29 VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB, 30 VIRTIO_GPU_CMD_SET_SCANOUT_BLOB, 31 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200, 32 VIRTIO_GPU_CMD_CTX_DESTROY, 33 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, 34 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE, 35 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D, 36 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, 37 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D, 38 VIRTIO_GPU_CMD_SUBMIT_3D, 39 VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB, 40 VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB, 41 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300, 42 VIRTIO_GPU_CMD_MOVE_CURSOR, 43 VIRTIO_GPU_RESP_OK_NODATA = 0x1100, 44 VIRTIO_GPU_RESP_OK_DISPLAY_INFO, 45 VIRTIO_GPU_RESP_OK_CAPSET_INFO, 46 VIRTIO_GPU_RESP_OK_CAPSET, 47 VIRTIO_GPU_RESP_OK_EDID, 48 VIRTIO_GPU_RESP_OK_RESOURCE_UUID, 49 VIRTIO_GPU_RESP_OK_MAP_INFO, 50 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200, 51 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY, 52 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID, 53 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID, 54 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID, 55 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER, 56 }; 57 enum virtio_gpu_shm_id { 58 VIRTIO_GPU_SHM_ID_UNDEFINED = 0, 59 VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1 60 }; 61 #define VIRTIO_GPU_FLAG_FENCE (1 << 0) 62 #define VIRTIO_GPU_FLAG_INFO_RING_IDX (1 << 1) 63 struct virtio_gpu_ctrl_hdr { 64 __le32 type; 65 __le32 flags; 66 __le64 fence_id; 67 __le32 ctx_id; 68 __u8 ring_idx; 69 __u8 padding[3]; 70 }; 71 struct virtio_gpu_cursor_pos { 72 __le32 scanout_id; 73 __le32 x; 74 __le32 y; 75 __le32 padding; 76 }; 77 struct virtio_gpu_update_cursor { 78 struct virtio_gpu_ctrl_hdr hdr; 79 struct virtio_gpu_cursor_pos pos; 80 __le32 resource_id; 81 __le32 hot_x; 82 __le32 hot_y; 83 __le32 padding; 84 }; 85 struct virtio_gpu_rect { 86 __le32 x; 87 __le32 y; 88 __le32 width; 89 __le32 height; 90 }; 91 struct virtio_gpu_resource_unref { 92 struct virtio_gpu_ctrl_hdr hdr; 93 __le32 resource_id; 94 __le32 padding; 95 }; 96 struct virtio_gpu_resource_create_2d { 97 struct virtio_gpu_ctrl_hdr hdr; 98 __le32 resource_id; 99 __le32 format; 100 __le32 width; 101 __le32 height; 102 }; 103 struct virtio_gpu_set_scanout { 104 struct virtio_gpu_ctrl_hdr hdr; 105 struct virtio_gpu_rect r; 106 __le32 scanout_id; 107 __le32 resource_id; 108 }; 109 struct virtio_gpu_resource_flush { 110 struct virtio_gpu_ctrl_hdr hdr; 111 struct virtio_gpu_rect r; 112 __le32 resource_id; 113 __le32 padding; 114 }; 115 struct virtio_gpu_transfer_to_host_2d { 116 struct virtio_gpu_ctrl_hdr hdr; 117 struct virtio_gpu_rect r; 118 __le64 offset; 119 __le32 resource_id; 120 __le32 padding; 121 }; 122 struct virtio_gpu_mem_entry { 123 __le64 addr; 124 __le32 length; 125 __le32 padding; 126 }; 127 struct virtio_gpu_resource_attach_backing { 128 struct virtio_gpu_ctrl_hdr hdr; 129 __le32 resource_id; 130 __le32 nr_entries; 131 }; 132 struct virtio_gpu_resource_detach_backing { 133 struct virtio_gpu_ctrl_hdr hdr; 134 __le32 resource_id; 135 __le32 padding; 136 }; 137 #define VIRTIO_GPU_MAX_SCANOUTS 16 138 struct virtio_gpu_resp_display_info { 139 struct virtio_gpu_ctrl_hdr hdr; 140 struct virtio_gpu_display_one { 141 struct virtio_gpu_rect r; 142 __le32 enabled; 143 __le32 flags; 144 } pmodes[VIRTIO_GPU_MAX_SCANOUTS]; 145 }; 146 struct virtio_gpu_box { 147 __le32 x, y, z; 148 __le32 w, h, d; 149 }; 150 struct virtio_gpu_transfer_host_3d { 151 struct virtio_gpu_ctrl_hdr hdr; 152 struct virtio_gpu_box box; 153 __le64 offset; 154 __le32 resource_id; 155 __le32 level; 156 __le32 stride; 157 __le32 layer_stride; 158 }; 159 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0) 160 struct virtio_gpu_resource_create_3d { 161 struct virtio_gpu_ctrl_hdr hdr; 162 __le32 resource_id; 163 __le32 target; 164 __le32 format; 165 __le32 bind; 166 __le32 width; 167 __le32 height; 168 __le32 depth; 169 __le32 array_size; 170 __le32 last_level; 171 __le32 nr_samples; 172 __le32 flags; 173 __le32 padding; 174 }; 175 #define VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK 0x000000ff 176 struct virtio_gpu_ctx_create { 177 struct virtio_gpu_ctrl_hdr hdr; 178 __le32 nlen; 179 __le32 context_init; 180 char debug_name[64]; 181 }; 182 struct virtio_gpu_ctx_destroy { 183 struct virtio_gpu_ctrl_hdr hdr; 184 }; 185 struct virtio_gpu_ctx_resource { 186 struct virtio_gpu_ctrl_hdr hdr; 187 __le32 resource_id; 188 __le32 padding; 189 }; 190 struct virtio_gpu_cmd_submit { 191 struct virtio_gpu_ctrl_hdr hdr; 192 __le32 size; 193 __le32 padding; 194 }; 195 #define VIRTIO_GPU_CAPSET_VIRGL 1 196 #define VIRTIO_GPU_CAPSET_VIRGL2 2 197 #define VIRTIO_GPU_CAPSET_VENUS 4 198 struct virtio_gpu_get_capset_info { 199 struct virtio_gpu_ctrl_hdr hdr; 200 __le32 capset_index; 201 __le32 padding; 202 }; 203 struct virtio_gpu_resp_capset_info { 204 struct virtio_gpu_ctrl_hdr hdr; 205 __le32 capset_id; 206 __le32 capset_max_version; 207 __le32 capset_max_size; 208 __le32 padding; 209 }; 210 struct virtio_gpu_get_capset { 211 struct virtio_gpu_ctrl_hdr hdr; 212 __le32 capset_id; 213 __le32 capset_version; 214 }; 215 struct virtio_gpu_resp_capset { 216 struct virtio_gpu_ctrl_hdr hdr; 217 __u8 capset_data[]; 218 }; 219 struct virtio_gpu_cmd_get_edid { 220 struct virtio_gpu_ctrl_hdr hdr; 221 __le32 scanout; 222 __le32 padding; 223 }; 224 struct virtio_gpu_resp_edid { 225 struct virtio_gpu_ctrl_hdr hdr; 226 __le32 size; 227 __le32 padding; 228 __u8 edid[1024]; 229 }; 230 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) 231 struct virtio_gpu_config { 232 __le32 events_read; 233 __le32 events_clear; 234 __le32 num_scanouts; 235 __le32 num_capsets; 236 }; 237 enum virtio_gpu_formats { 238 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1, 239 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2, 240 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3, 241 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4, 242 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67, 243 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68, 244 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121, 245 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134, 246 }; 247 struct virtio_gpu_resource_assign_uuid { 248 struct virtio_gpu_ctrl_hdr hdr; 249 __le32 resource_id; 250 __le32 padding; 251 }; 252 struct virtio_gpu_resp_resource_uuid { 253 struct virtio_gpu_ctrl_hdr hdr; 254 __u8 uuid[16]; 255 }; 256 struct virtio_gpu_resource_create_blob { 257 struct virtio_gpu_ctrl_hdr hdr; 258 __le32 resource_id; 259 #define VIRTIO_GPU_BLOB_MEM_GUEST 0x0001 260 #define VIRTIO_GPU_BLOB_MEM_HOST3D 0x0002 261 #define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST 0x0003 262 #define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE 0x0001 263 #define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE 0x0002 264 #define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004 265 __le32 blob_mem; 266 __le32 blob_flags; 267 __le32 nr_entries; 268 __le64 blob_id; 269 __le64 size; 270 }; 271 struct virtio_gpu_set_scanout_blob { 272 struct virtio_gpu_ctrl_hdr hdr; 273 struct virtio_gpu_rect r; 274 __le32 scanout_id; 275 __le32 resource_id; 276 __le32 width; 277 __le32 height; 278 __le32 format; 279 __le32 padding; 280 __le32 strides[4]; 281 __le32 offsets[4]; 282 }; 283 struct virtio_gpu_resource_map_blob { 284 struct virtio_gpu_ctrl_hdr hdr; 285 __le32 resource_id; 286 __le32 padding; 287 __le64 offset; 288 }; 289 #define VIRTIO_GPU_MAP_CACHE_MASK 0x0f 290 #define VIRTIO_GPU_MAP_CACHE_NONE 0x00 291 #define VIRTIO_GPU_MAP_CACHE_CACHED 0x01 292 #define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02 293 #define VIRTIO_GPU_MAP_CACHE_WC 0x03 294 struct virtio_gpu_resp_map_info { 295 struct virtio_gpu_ctrl_hdr hdr; 296 __u32 map_info; 297 __u32 padding; 298 }; 299 struct virtio_gpu_resource_unmap_blob { 300 struct virtio_gpu_ctrl_hdr hdr; 301 __le32 resource_id; 302 __le32 padding; 303 }; 304 #endif 305