1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef VIRTIO_SND_IF_H 8 #define VIRTIO_SND_IF_H 9 #include <linux/virtio_types.h> 10 enum { 11 VIRTIO_SND_F_CTLS = 0 12 }; 13 struct virtio_snd_config { 14 __le32 jacks; 15 __le32 streams; 16 __le32 chmaps; 17 __le32 controls; 18 }; 19 enum { 20 VIRTIO_SND_VQ_CONTROL = 0, 21 VIRTIO_SND_VQ_EVENT, 22 VIRTIO_SND_VQ_TX, 23 VIRTIO_SND_VQ_RX, 24 VIRTIO_SND_VQ_MAX 25 }; 26 enum { 27 VIRTIO_SND_D_OUTPUT = 0, 28 VIRTIO_SND_D_INPUT 29 }; 30 enum { 31 VIRTIO_SND_R_JACK_INFO = 1, 32 VIRTIO_SND_R_JACK_REMAP, 33 VIRTIO_SND_R_PCM_INFO = 0x0100, 34 VIRTIO_SND_R_PCM_SET_PARAMS, 35 VIRTIO_SND_R_PCM_PREPARE, 36 VIRTIO_SND_R_PCM_RELEASE, 37 VIRTIO_SND_R_PCM_START, 38 VIRTIO_SND_R_PCM_STOP, 39 VIRTIO_SND_R_CHMAP_INFO = 0x0200, 40 VIRTIO_SND_R_CTL_INFO = 0x0300, 41 VIRTIO_SND_R_CTL_ENUM_ITEMS, 42 VIRTIO_SND_R_CTL_READ, 43 VIRTIO_SND_R_CTL_WRITE, 44 VIRTIO_SND_R_CTL_TLV_READ, 45 VIRTIO_SND_R_CTL_TLV_WRITE, 46 VIRTIO_SND_R_CTL_TLV_COMMAND, 47 VIRTIO_SND_EVT_JACK_CONNECTED = 0x1000, 48 VIRTIO_SND_EVT_JACK_DISCONNECTED, 49 VIRTIO_SND_EVT_PCM_PERIOD_ELAPSED = 0x1100, 50 VIRTIO_SND_EVT_PCM_XRUN, 51 VIRTIO_SND_EVT_CTL_NOTIFY = 0x1200, 52 VIRTIO_SND_S_OK = 0x8000, 53 VIRTIO_SND_S_BAD_MSG, 54 VIRTIO_SND_S_NOT_SUPP, 55 VIRTIO_SND_S_IO_ERR 56 }; 57 struct virtio_snd_hdr { 58 __le32 code; 59 }; 60 struct virtio_snd_event { 61 struct virtio_snd_hdr hdr; 62 __le32 data; 63 }; 64 struct virtio_snd_query_info { 65 struct virtio_snd_hdr hdr; 66 __le32 start_id; 67 __le32 count; 68 __le32 size; 69 }; 70 struct virtio_snd_info { 71 __le32 hda_fn_nid; 72 }; 73 struct virtio_snd_jack_hdr { 74 struct virtio_snd_hdr hdr; 75 __le32 jack_id; 76 }; 77 enum { 78 VIRTIO_SND_JACK_F_REMAP = 0 79 }; 80 struct virtio_snd_jack_info { 81 struct virtio_snd_info hdr; 82 __le32 features; 83 __le32 hda_reg_defconf; 84 __le32 hda_reg_caps; 85 __u8 connected; 86 __u8 padding[7]; 87 }; 88 struct virtio_snd_jack_remap { 89 struct virtio_snd_jack_hdr hdr; 90 __le32 association; 91 __le32 sequence; 92 }; 93 struct virtio_snd_pcm_hdr { 94 struct virtio_snd_hdr hdr; 95 __le32 stream_id; 96 }; 97 enum { 98 VIRTIO_SND_PCM_F_SHMEM_HOST = 0, 99 VIRTIO_SND_PCM_F_SHMEM_GUEST, 100 VIRTIO_SND_PCM_F_MSG_POLLING, 101 VIRTIO_SND_PCM_F_EVT_SHMEM_PERIODS, 102 VIRTIO_SND_PCM_F_EVT_XRUNS 103 }; 104 enum { 105 VIRTIO_SND_PCM_FMT_IMA_ADPCM = 0, 106 VIRTIO_SND_PCM_FMT_MU_LAW, 107 VIRTIO_SND_PCM_FMT_A_LAW, 108 VIRTIO_SND_PCM_FMT_S8, 109 VIRTIO_SND_PCM_FMT_U8, 110 VIRTIO_SND_PCM_FMT_S16, 111 VIRTIO_SND_PCM_FMT_U16, 112 VIRTIO_SND_PCM_FMT_S18_3, 113 VIRTIO_SND_PCM_FMT_U18_3, 114 VIRTIO_SND_PCM_FMT_S20_3, 115 VIRTIO_SND_PCM_FMT_U20_3, 116 VIRTIO_SND_PCM_FMT_S24_3, 117 VIRTIO_SND_PCM_FMT_U24_3, 118 VIRTIO_SND_PCM_FMT_S20, 119 VIRTIO_SND_PCM_FMT_U20, 120 VIRTIO_SND_PCM_FMT_S24, 121 VIRTIO_SND_PCM_FMT_U24, 122 VIRTIO_SND_PCM_FMT_S32, 123 VIRTIO_SND_PCM_FMT_U32, 124 VIRTIO_SND_PCM_FMT_FLOAT, 125 VIRTIO_SND_PCM_FMT_FLOAT64, 126 VIRTIO_SND_PCM_FMT_DSD_U8, 127 VIRTIO_SND_PCM_FMT_DSD_U16, 128 VIRTIO_SND_PCM_FMT_DSD_U32, 129 VIRTIO_SND_PCM_FMT_IEC958_SUBFRAME 130 }; 131 enum { 132 VIRTIO_SND_PCM_RATE_5512 = 0, 133 VIRTIO_SND_PCM_RATE_8000, 134 VIRTIO_SND_PCM_RATE_11025, 135 VIRTIO_SND_PCM_RATE_16000, 136 VIRTIO_SND_PCM_RATE_22050, 137 VIRTIO_SND_PCM_RATE_32000, 138 VIRTIO_SND_PCM_RATE_44100, 139 VIRTIO_SND_PCM_RATE_48000, 140 VIRTIO_SND_PCM_RATE_64000, 141 VIRTIO_SND_PCM_RATE_88200, 142 VIRTIO_SND_PCM_RATE_96000, 143 VIRTIO_SND_PCM_RATE_176400, 144 VIRTIO_SND_PCM_RATE_192000, 145 VIRTIO_SND_PCM_RATE_384000 146 }; 147 struct virtio_snd_pcm_info { 148 struct virtio_snd_info hdr; 149 __le32 features; 150 __le64 formats; 151 __le64 rates; 152 __u8 direction; 153 __u8 channels_min; 154 __u8 channels_max; 155 __u8 padding[5]; 156 }; 157 struct virtio_snd_pcm_set_params { 158 struct virtio_snd_pcm_hdr hdr; 159 __le32 buffer_bytes; 160 __le32 period_bytes; 161 __le32 features; 162 __u8 channels; 163 __u8 format; 164 __u8 rate; 165 __u8 padding; 166 }; 167 struct virtio_snd_pcm_xfer { 168 __le32 stream_id; 169 }; 170 struct virtio_snd_pcm_status { 171 __le32 status; 172 __le32 latency_bytes; 173 }; 174 struct virtio_snd_chmap_hdr { 175 struct virtio_snd_hdr hdr; 176 __le32 chmap_id; 177 }; 178 enum { 179 VIRTIO_SND_CHMAP_NONE = 0, 180 VIRTIO_SND_CHMAP_NA, 181 VIRTIO_SND_CHMAP_MONO, 182 VIRTIO_SND_CHMAP_FL, 183 VIRTIO_SND_CHMAP_FR, 184 VIRTIO_SND_CHMAP_RL, 185 VIRTIO_SND_CHMAP_RR, 186 VIRTIO_SND_CHMAP_FC, 187 VIRTIO_SND_CHMAP_LFE, 188 VIRTIO_SND_CHMAP_SL, 189 VIRTIO_SND_CHMAP_SR, 190 VIRTIO_SND_CHMAP_RC, 191 VIRTIO_SND_CHMAP_FLC, 192 VIRTIO_SND_CHMAP_FRC, 193 VIRTIO_SND_CHMAP_RLC, 194 VIRTIO_SND_CHMAP_RRC, 195 VIRTIO_SND_CHMAP_FLW, 196 VIRTIO_SND_CHMAP_FRW, 197 VIRTIO_SND_CHMAP_FLH, 198 VIRTIO_SND_CHMAP_FCH, 199 VIRTIO_SND_CHMAP_FRH, 200 VIRTIO_SND_CHMAP_TC, 201 VIRTIO_SND_CHMAP_TFL, 202 VIRTIO_SND_CHMAP_TFR, 203 VIRTIO_SND_CHMAP_TFC, 204 VIRTIO_SND_CHMAP_TRL, 205 VIRTIO_SND_CHMAP_TRR, 206 VIRTIO_SND_CHMAP_TRC, 207 VIRTIO_SND_CHMAP_TFLC, 208 VIRTIO_SND_CHMAP_TFRC, 209 VIRTIO_SND_CHMAP_TSL, 210 VIRTIO_SND_CHMAP_TSR, 211 VIRTIO_SND_CHMAP_LLFE, 212 VIRTIO_SND_CHMAP_RLFE, 213 VIRTIO_SND_CHMAP_BC, 214 VIRTIO_SND_CHMAP_BLC, 215 VIRTIO_SND_CHMAP_BRC 216 }; 217 #define VIRTIO_SND_CHMAP_MAX_SIZE 18 218 struct virtio_snd_chmap_info { 219 struct virtio_snd_info hdr; 220 __u8 direction; 221 __u8 channels; 222 __u8 positions[VIRTIO_SND_CHMAP_MAX_SIZE]; 223 }; 224 struct virtio_snd_ctl_hdr { 225 struct virtio_snd_hdr hdr; 226 __le32 control_id; 227 }; 228 enum { 229 VIRTIO_SND_CTL_ROLE_UNDEFINED = 0, 230 VIRTIO_SND_CTL_ROLE_VOLUME, 231 VIRTIO_SND_CTL_ROLE_MUTE, 232 VIRTIO_SND_CTL_ROLE_GAIN 233 }; 234 enum { 235 VIRTIO_SND_CTL_TYPE_BOOLEAN = 0, 236 VIRTIO_SND_CTL_TYPE_INTEGER, 237 VIRTIO_SND_CTL_TYPE_INTEGER64, 238 VIRTIO_SND_CTL_TYPE_ENUMERATED, 239 VIRTIO_SND_CTL_TYPE_BYTES, 240 VIRTIO_SND_CTL_TYPE_IEC958 241 }; 242 enum { 243 VIRTIO_SND_CTL_ACCESS_READ = 0, 244 VIRTIO_SND_CTL_ACCESS_WRITE, 245 VIRTIO_SND_CTL_ACCESS_VOLATILE, 246 VIRTIO_SND_CTL_ACCESS_INACTIVE, 247 VIRTIO_SND_CTL_ACCESS_TLV_READ, 248 VIRTIO_SND_CTL_ACCESS_TLV_WRITE, 249 VIRTIO_SND_CTL_ACCESS_TLV_COMMAND 250 }; 251 struct virtio_snd_ctl_info { 252 struct virtio_snd_info hdr; 253 __le32 role; 254 __le32 type; 255 __le32 access; 256 __le32 count; 257 __le32 index; 258 __u8 name[44]; 259 union { 260 struct { 261 __le32 min; 262 __le32 max; 263 __le32 step; 264 } integer; 265 struct { 266 __le64 min; 267 __le64 max; 268 __le64 step; 269 } integer64; 270 struct { 271 __le32 items; 272 } enumerated; 273 } value; 274 }; 275 struct virtio_snd_ctl_enum_item { 276 __u8 item[64]; 277 }; 278 struct virtio_snd_ctl_iec958 { 279 __u8 status[24]; 280 __u8 subcode[147]; 281 __u8 pad; 282 __u8 dig_subframe[4]; 283 }; 284 struct virtio_snd_ctl_value { 285 union { 286 __le32 integer[128]; 287 __le64 integer64[64]; 288 __le32 enumerated[128]; 289 __u8 bytes[512]; 290 struct virtio_snd_ctl_iec958 iec958; 291 } value; 292 }; 293 enum { 294 VIRTIO_SND_CTL_EVT_MASK_VALUE = 0, 295 VIRTIO_SND_CTL_EVT_MASK_INFO, 296 VIRTIO_SND_CTL_EVT_MASK_TLV 297 }; 298 struct virtio_snd_ctl_event { 299 struct virtio_snd_hdr hdr; 300 __le16 control_id; 301 __le16 mask; 302 }; 303 #endif 304