1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _SIW_USER_H 8 #define _SIW_USER_H 9 #include <linux/types.h> 10 #define SIW_NODE_DESC_COMMON "Software iWARP stack" 11 #define SIW_ABI_VERSION 1 12 #define SIW_MAX_SGE 6 13 #define SIW_UOBJ_MAX_KEY 0x08FFFF 14 #define SIW_INVAL_UOBJ_KEY (SIW_UOBJ_MAX_KEY + 1) 15 struct siw_uresp_create_cq { 16 __u32 cq_id; 17 __u32 num_cqe; 18 __aligned_u64 cq_key; 19 }; 20 struct siw_uresp_create_qp { 21 __u32 qp_id; 22 __u32 num_sqe; 23 __u32 num_rqe; 24 __u32 pad; 25 __aligned_u64 sq_key; 26 __aligned_u64 rq_key; 27 }; 28 struct siw_ureq_reg_mr { 29 __u8 stag_key; 30 __u8 reserved[3]; 31 __u32 pad; 32 }; 33 struct siw_uresp_reg_mr { 34 __u32 stag; 35 __u32 pad; 36 }; 37 struct siw_uresp_create_srq { 38 __u32 num_rqe; 39 __u32 pad; 40 __aligned_u64 srq_key; 41 }; 42 struct siw_uresp_alloc_ctx { 43 __u32 dev_id; 44 __u32 pad; 45 }; 46 enum siw_opcode { 47 SIW_OP_WRITE, 48 SIW_OP_READ, 49 SIW_OP_READ_LOCAL_INV, 50 SIW_OP_SEND, 51 SIW_OP_SEND_WITH_IMM, 52 SIW_OP_SEND_REMOTE_INV, 53 SIW_OP_FETCH_AND_ADD, 54 SIW_OP_COMP_AND_SWAP, 55 SIW_OP_RECEIVE, 56 SIW_OP_READ_RESPONSE, 57 SIW_OP_INVAL_STAG, 58 SIW_OP_REG_MR, 59 SIW_NUM_OPCODES 60 }; 61 struct siw_sge { 62 __aligned_u64 laddr; 63 __u32 length; 64 __u32 lkey; 65 }; 66 #define SIW_MAX_INLINE (sizeof(struct siw_sge) * (SIW_MAX_SGE - 1)) 67 #if SIW_MAX_SGE < 2 68 #error "SIW_MAX_SGE must be at least 2" 69 #endif 70 enum siw_wqe_flags { 71 SIW_WQE_VALID = 1, 72 SIW_WQE_INLINE = (1 << 1), 73 SIW_WQE_SIGNALLED = (1 << 2), 74 SIW_WQE_SOLICITED = (1 << 3), 75 SIW_WQE_READ_FENCE = (1 << 4), 76 SIW_WQE_REM_INVAL = (1 << 5), 77 SIW_WQE_COMPLETED = (1 << 6) 78 }; 79 struct siw_sqe { 80 __aligned_u64 id; 81 __u16 flags; 82 __u8 num_sge; 83 __u8 opcode; 84 __u32 rkey; 85 union { 86 __aligned_u64 raddr; 87 __aligned_u64 base_mr; 88 }; 89 union { 90 struct siw_sge sge[SIW_MAX_SGE]; 91 __aligned_u64 access; 92 }; 93 }; 94 struct siw_rqe { 95 __aligned_u64 id; 96 __u16 flags; 97 __u8 num_sge; 98 __u8 opcode; 99 __u32 unused; 100 struct siw_sge sge[SIW_MAX_SGE]; 101 }; 102 enum siw_notify_flags { 103 SIW_NOTIFY_NOT = (0), 104 SIW_NOTIFY_SOLICITED = (1 << 0), 105 SIW_NOTIFY_NEXT_COMPLETION = (1 << 1), 106 SIW_NOTIFY_MISSED_EVENTS = (1 << 2), 107 SIW_NOTIFY_ALL = SIW_NOTIFY_SOLICITED | SIW_NOTIFY_NEXT_COMPLETION | SIW_NOTIFY_MISSED_EVENTS 108 }; 109 enum siw_wc_status { 110 SIW_WC_SUCCESS, 111 SIW_WC_LOC_LEN_ERR, 112 SIW_WC_LOC_PROT_ERR, 113 SIW_WC_LOC_QP_OP_ERR, 114 SIW_WC_WR_FLUSH_ERR, 115 SIW_WC_BAD_RESP_ERR, 116 SIW_WC_LOC_ACCESS_ERR, 117 SIW_WC_REM_ACCESS_ERR, 118 SIW_WC_REM_INV_REQ_ERR, 119 SIW_WC_GENERAL_ERR, 120 SIW_NUM_WC_STATUS 121 }; 122 struct siw_cqe { 123 __aligned_u64 id; 124 __u8 flags; 125 __u8 opcode; 126 __u16 status; 127 __u32 bytes; 128 union { 129 __aligned_u64 imm_data; 130 __u32 inval_stag; 131 }; 132 union { 133 struct ib_qp * base_qp; 134 __aligned_u64 qp_id; 135 }; 136 }; 137 struct siw_cq_ctrl { 138 __u32 flags; 139 __u32 pad; 140 }; 141 #endif 142