1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __SAMSUNG_DRM_H__ 8 #define __SAMSUNG_DRM_H__ 9 #ifdef __linux__ 10 #include <linux/types.h> 11 #endif 12 #include <drm/drm.h> 13 #include <drm/drm_fourcc_gs101.h> 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 #define DRM_SAMSUNG_HDR_EOTF_LUT_LEN 129 18 #define DRM_SAMSUNG_HDR_EOTF_V2P2_LUT_LEN 20 19 struct hdr_eotf_lut { 20 __u16 posx[DRM_SAMSUNG_HDR_EOTF_LUT_LEN]; 21 __u32 posy[DRM_SAMSUNG_HDR_EOTF_LUT_LEN]; 22 }; 23 struct hdr_v2p2_element { 24 __u16 even; 25 __u16 odd; 26 }; 27 struct hdr_eotf_lut_v2p2 { 28 struct hdr_v2p2_element ts[DRM_SAMSUNG_HDR_EOTF_V2P2_LUT_LEN]; 29 struct hdr_v2p2_element vs[DRM_SAMSUNG_HDR_EOTF_V2P2_LUT_LEN]; 30 __u16 scaler; 31 bool lut_en; 32 }; 33 #define DRM_SAMSUNG_HDR_OETF_LUT_LEN 33 34 #define DRM_SAMSUNG_HDR_OETF_V2P2_LUT_LEN 24 35 struct hdr_oetf_lut { 36 __u16 posx[DRM_SAMSUNG_HDR_OETF_LUT_LEN]; 37 __u16 posy[DRM_SAMSUNG_HDR_OETF_LUT_LEN]; 38 }; 39 struct hdr_oetf_lut_v2p2 { 40 struct hdr_v2p2_element ts[DRM_SAMSUNG_HDR_OETF_V2P2_LUT_LEN]; 41 struct hdr_v2p2_element vs[DRM_SAMSUNG_HDR_OETF_V2P2_LUT_LEN]; 42 }; 43 #define DRM_SAMSUNG_HDR_GM_DIMENS 3 44 struct hdr_gm_data { 45 __u32 coeffs[DRM_SAMSUNG_HDR_GM_DIMENS * DRM_SAMSUNG_HDR_GM_DIMENS]; 46 __u32 offsets[DRM_SAMSUNG_HDR_GM_DIMENS]; 47 }; 48 #define DRM_SAMSUNG_HDR_TM_LUT_LEN 33 49 #define DRM_SAMSUNG_HDR_TM_V2P2_LUT_LEN 24 50 struct hdr_tm_data { 51 __u16 coeff_r; 52 __u16 coeff_g; 53 __u16 coeff_b; 54 __u16 rng_x_min; 55 __u16 rng_x_max; 56 __u16 rng_y_min; 57 __u16 rng_y_max; 58 __u16 posx[DRM_SAMSUNG_HDR_TM_LUT_LEN]; 59 __u32 posy[DRM_SAMSUNG_HDR_TM_LUT_LEN]; 60 }; 61 struct hdr_tm_data_v2p2 { 62 __u16 coeff_00; 63 __u16 coeff_01; 64 __u16 coeff_02; 65 __u16 ymix_tf; 66 __u16 ymix_vf; 67 __u16 ymix_slope; 68 __u16 ymix_dv; 69 struct hdr_v2p2_element ts[DRM_SAMSUNG_HDR_TM_V2P2_LUT_LEN]; 70 struct hdr_v2p2_element vs[DRM_SAMSUNG_HDR_TM_V2P2_LUT_LEN]; 71 }; 72 #define DRM_SAMSUNG_CGC_LUT_REG_CNT 2457 73 struct cgc_lut { 74 __u32 r_values[DRM_SAMSUNG_CGC_LUT_REG_CNT]; 75 __u32 g_values[DRM_SAMSUNG_CGC_LUT_REG_CNT]; 76 __u32 b_values[DRM_SAMSUNG_CGC_LUT_REG_CNT]; 77 }; 78 #define DRM_SAMSUNG_CGC_DMA_LUT_ENTRY_CNT 4913 79 struct cgc_dma_lut { 80 __u16 r_value; 81 __u16 g_value; 82 __u16 b_value; 83 }; 84 #define DRM_SAMSUNG_MATRIX_DIMENS 3 85 struct exynos_matrix { 86 __u16 coeffs[DRM_SAMSUNG_MATRIX_DIMENS * DRM_SAMSUNG_MATRIX_DIMENS]; 87 __u16 offsets[DRM_SAMSUNG_MATRIX_DIMENS]; 88 }; 89 struct dpp_size_range { 90 __u32 min; 91 __u32 max; 92 __u32 align; 93 }; 94 struct dpp_restriction { 95 struct dpp_size_range src_f_w; 96 struct dpp_size_range src_f_h; 97 struct dpp_size_range src_w; 98 struct dpp_size_range src_h; 99 __u32 src_x_align; 100 __u32 src_y_align; 101 struct dpp_size_range dst_f_w; 102 struct dpp_size_range dst_f_h; 103 struct dpp_size_range dst_w; 104 struct dpp_size_range dst_h; 105 __u32 dst_x_align; 106 __u32 dst_y_align; 107 struct dpp_size_range blk_w; 108 struct dpp_size_range blk_h; 109 __u32 blk_x_align; 110 __u32 blk_y_align; 111 __u32 src_h_rot_max; 112 __u32 scale_down; 113 __u32 scale_up; 114 }; 115 struct dpp_ch_restriction { 116 __s32 id; 117 __u64 attr; 118 struct dpp_restriction restriction; 119 }; 120 struct dither_config { 121 __u8 en : 1; 122 __u8 mode : 1; 123 __u8 frame_con : 1; 124 __u8 frame_offset : 2; 125 __u8 table_sel_r : 1; 126 __u8 table_sel_g : 1; 127 __u8 table_sel_b : 1; 128 __u32 reserved : 24; 129 }; 130 struct attribute_range { 131 __u32 min; 132 __u32 max; 133 }; 134 struct brightness_attribute { 135 struct attribute_range nits; 136 struct attribute_range level; 137 struct attribute_range percentage; 138 }; 139 struct brightness_capability { 140 struct brightness_attribute normal; 141 struct brightness_attribute hbm; 142 }; 143 struct tui_hw_buffer { 144 __u64 fb_physical; 145 __u64 fb_size; 146 } __attribute__((packed)); 147 #define EXYNOS_START_TUI 0x10 148 #define EXYNOS_FINISH_TUI 0x11 149 #define EXYNOS_TUI_REQUEST_BUFFER 0x20 150 #define EXYNOS_TUI_RELEASE_BUFFER 0x21 151 struct histogram_roi { 152 __u16 start_x; 153 __u16 start_y; 154 __u16 hsize; 155 __u16 vsize; 156 }; 157 struct histogram_weights { 158 __u16 weight_r; 159 __u16 weight_g; 160 __u16 weight_b; 161 }; 162 #define HISTOGRAM_BIN_COUNT 256 163 struct histogram_bins { 164 __u16 data[HISTOGRAM_BIN_COUNT]; 165 }; 166 enum histogram_prog_pos { 167 POST_DQE, 168 PRE_DQE, 169 }; 170 enum histogram_flags { 171 HISTOGRAM_FLAGS_BLOCKED_ROI = 0x20, 172 }; 173 struct histogram_channel_config { 174 struct histogram_roi roi; 175 struct histogram_weights weights; 176 enum histogram_prog_pos pos; 177 __u32 threshold; 178 struct histogram_roi blocked_roi; 179 __u32 flags; 180 }; 181 #define EXYNOS_DRM_HISTOGRAM_EVENT 0x80000000 182 #define EXYNOS_DRM_HISTOGRAM_CHANNEL_EVENT 0x80000001 183 struct exynos_drm_histogram_event { 184 struct drm_event base; 185 struct histogram_bins bins; 186 __u32 crtc_id; 187 }; 188 struct exynos_drm_histogram_channel_event { 189 struct drm_event base; 190 struct histogram_bins bins; 191 __u16 crtc_id; 192 __u16 hist_id; 193 }; 194 #define EXYNOS_HISTOGRAM_REQUEST 0x0 195 #define EXYNOS_HISTOGRAM_CANCEL 0x1 196 #define EXYNOS_HISTOGRAM_CHANNEL_REQUEST 0x20 197 #define EXYNOS_HISTOGRAM_CHANNEL_CANCEL 0x21 198 #define EXYNOS_HISTOGRAM_CHANNEL_DATA_REQUEST 0x30 199 struct exynos_drm_histogram_channel_request { 200 __u32 crtc_id; 201 __u32 hist_id; 202 }; 203 struct exynos_drm_histogram_channel_data_request { 204 __u16 crtc_id; 205 __u16 hist_id; 206 struct histogram_bins * bins; 207 }; 208 #define DRM_IOCTL_EXYNOS_HISTOGRAM_REQUEST DRM_IOW(DRM_COMMAND_BASE + EXYNOS_HISTOGRAM_REQUEST, __u32) 209 #define DRM_IOCTL_EXYNOS_HISTOGRAM_CANCEL DRM_IOW(DRM_COMMAND_BASE + EXYNOS_HISTOGRAM_CANCEL, __u32) 210 #define DRM_IOCTL_EXYNOS_HISTOGRAM_CHANNEL_REQUEST DRM_IOW(DRM_COMMAND_BASE + EXYNOS_HISTOGRAM_CHANNEL_REQUEST, struct exynos_drm_histogram_channel_request) 211 #define DRM_IOCTL_EXYNOS_HISTOGRAM_CHANNEL_CANCEL DRM_IOW(DRM_COMMAND_BASE + EXYNOS_HISTOGRAM_CHANNEL_CANCEL, struct exynos_drm_histogram_channel_request) 212 #define DRM_IOCTL_EXYNOS_HISTOGRAM_CHANNEL_DATA_REQUEST DRM_IOW(DRM_COMMAND_BASE + EXYNOS_HISTOGRAM_CHANNEL_DATA_REQUEST, struct exynos_drm_histogram_channel_data_request) 213 #ifdef __cplusplus 214 } 215 #endif 216 #endif 217